Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00053
Alexander Janta-Polczynski, M. Robitaille
Automated fiber to V/U-groove assemblies offer a robust and cost-effective solution to interface single mode fibers to silicon photonic integrated circuits; however, the handling and assembly of long pigtails attached to photonic packages pose significant challenges. An integrated high-bandwidth optical connector with a latching mechanism secured to the module could eliminate these packaging challenges and provide an attractive alternative for photonic products. A multi-fiber interface integrating a standard single mode fiber mechanical transfer connector to a co-package photonics module is studied here. The geometric configuration exploits the fiber bending to accommodate the strain and control the stress at both anchor points throughout temperature excursions. We demonstrate the benefits of using fibers longer than 25mm for the selected configuration. A fiber exit angle of a few degrees can provide some advantages in controlling the fiber buckling direction and reducing the fiber pistoning. It may however, along with other factors, be detrimental to the internal stress at reflow temperatures.
{"title":"Integrated Connector for Silicon Photonic Co-package Optics with Strain Relief Accommodation Through Fiber Bending","authors":"Alexander Janta-Polczynski, M. Robitaille","doi":"10.1109/ECTC32696.2021.00053","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00053","url":null,"abstract":"Automated fiber to V/U-groove assemblies offer a robust and cost-effective solution to interface single mode fibers to silicon photonic integrated circuits; however, the handling and assembly of long pigtails attached to photonic packages pose significant challenges. An integrated high-bandwidth optical connector with a latching mechanism secured to the module could eliminate these packaging challenges and provide an attractive alternative for photonic products. A multi-fiber interface integrating a standard single mode fiber mechanical transfer connector to a co-package photonics module is studied here. The geometric configuration exploits the fiber bending to accommodate the strain and control the stress at both anchor points throughout temperature excursions. We demonstrate the benefits of using fibers longer than 25mm for the selected configuration. A fiber exit angle of a few degrees can provide some advantages in controlling the fiber buckling direction and reducing the fiber pistoning. It may however, along with other factors, be detrimental to the internal stress at reflow temperatures.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129683295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00207
Biao Cai, Kevin Mcilvain, Junyan Tang, Kyle Giesen, Zhaoqing Chen, Hongqing Zhang, B. Beaman, Chris Steffen, Zhineng Fan, Victor Mahran, Luis Fukazawa, Roc Lv
Differential DIMM (DDIMM) is being defined in JEDEC and uses OMI as a host interface with the data transfer rate being specified at 25.6Gb/s at present and at 51.2Gb/s in the future. A prior 2019∼20 study [13] of full channel simulation and electrical test with initial DDR4 DDIMM engineering samples demonstrated the feasibility to achieve BER 10^-15 at 25.6Gb/s OMI bus data rate. In this study, the test result in production environment with much larger DDR4 DDIMM sample size will be analyzed for 25.6Gb/s OMI channel robustness. In addition, this study will explore the OMI bus data rate scale to 32Gb/s with the full channel time domain eye diagram analysis with BER at 10^-15. The prior studies in 2018∼20 [1], [13] concluded that the typical Copper Clad Laminate (CCL) and prepreg material used in the industry standard U/R/LR DIMM leads to signal integrity degradation relative to a better reference material at 25.6Gb/s OMI bus data rate while the improved DDIMM PCB stack-up with hybrid laminate material set has shown adequate margin. The DDIMM PCB stack-ups of this study include this hybrid material as baseline and lower loss Megtron 6 like material sets. DDIMM will be paired with the Storage Networking Industry Association (SNIA) SFF-TA-1002 high speed connector. The signal integrity challenges of DDIMM PCB contact interface to SFF-TA-1002 connector have been highlighted in the prior studies in 2018∼20[1], [13]. This study will discuss the contact interface robustness. In summary, this paper will present DDR4 DDIMM 25.6Gb/s OMI channel robustness study and the OMI channel scalability study to 32Gb/s which is planned for DDR5 DDIMM at product launch.
{"title":"Differential DIMM OpenCAPI Memory Interface High Speed Channel Robustness and Scalability Study","authors":"Biao Cai, Kevin Mcilvain, Junyan Tang, Kyle Giesen, Zhaoqing Chen, Hongqing Zhang, B. Beaman, Chris Steffen, Zhineng Fan, Victor Mahran, Luis Fukazawa, Roc Lv","doi":"10.1109/ECTC32696.2021.00207","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00207","url":null,"abstract":"Differential DIMM (DDIMM) is being defined in JEDEC and uses OMI as a host interface with the data transfer rate being specified at 25.6Gb/s at present and at 51.2Gb/s in the future. A prior 2019∼20 study [13] of full channel simulation and electrical test with initial DDR4 DDIMM engineering samples demonstrated the feasibility to achieve BER 10^-15 at 25.6Gb/s OMI bus data rate. In this study, the test result in production environment with much larger DDR4 DDIMM sample size will be analyzed for 25.6Gb/s OMI channel robustness. In addition, this study will explore the OMI bus data rate scale to 32Gb/s with the full channel time domain eye diagram analysis with BER at 10^-15. The prior studies in 2018∼20 [1], [13] concluded that the typical Copper Clad Laminate (CCL) and prepreg material used in the industry standard U/R/LR DIMM leads to signal integrity degradation relative to a better reference material at 25.6Gb/s OMI bus data rate while the improved DDIMM PCB stack-up with hybrid laminate material set has shown adequate margin. The DDIMM PCB stack-ups of this study include this hybrid material as baseline and lower loss Megtron 6 like material sets. DDIMM will be paired with the Storage Networking Industry Association (SNIA) SFF-TA-1002 high speed connector. The signal integrity challenges of DDIMM PCB contact interface to SFF-TA-1002 connector have been highlighted in the prior studies in 2018∼20[1], [13]. This study will discuss the contact interface robustness. In summary, this paper will present DDR4 DDIMM 25.6Gb/s OMI channel robustness study and the OMI channel scalability study to 32Gb/s which is planned for DDR5 DDIMM at product launch.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129915084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00366
M. A. Hoque, M. A. Haq, J. Suhling, P. Lall
Solder joints in electronic packages often experience fatigue failures due to cyclic mechanical stresses and strains in fluctuating temperature environments. These stresses and strains are induced by mismatches in coefficients of thermal expansion, and lead to damage accumulation that contributes to crack initiation, crack propagation, and eventually to failure. In our previous paper at ECTC 2020, we investigated the accumulation of damage in several solder materials (SAC305, $text{SAC} +text{Bi}$, and $text{SAC} +text{Bi}-text{Ni}-text{Sb}$) during mechanical cycling at room temperature. Circular cross-sectioned solder specimens were first reflowed, and these samples were then mechanically cycled for various durations using a Micro-Mechanical tester. Cyclic stress-strain, monotonic stress-strain, and creep tests were then conducted on the prior cycled samples. The cyclic stress-strain curves obtained were studied to observe the degradation of hysteresis loop properties (peak stress, hysteresis loop area, and plastic strain range) with mechanical cycling. The monotonic stress-strain and creep test data were plotted, and several mechanical properties were characterized for various levels of cycling. Using the data from these tests, we have been able to characterize and quantify the cycling induced damage through the observed degradations of several mechanical properties (elastic modulus, yield strength, ultimate strength, and creep strain rate) with the amount of prior cycling. All of the mechanical cyclic testing in our prior work and the work of others has been performed at room temperature ($mathrm{T}=25 {}^{circ} mathrm{C}$), and thus cannot be easily extended to thermal cycling applications. In our current work, we have extended our prior study to examine mechanical cycling at elevated temperature. In particular, we have examined lead free solders subjected to high temperature mechanical cycling at $mathrm{T}=100 {}^{circ} mathrm{C}$ and $mathrm{T}=125$ °C. Two solder alloys, SAC305 and $text{SAC} +text{Bi}$ (SAC_Q), have been investigated. In this paper, we report on the findings for SAC305 cycled at $mathrm{T}=100 {}^{circ} mathrm{C}$, and compare to the analogous results obtained for cycling at $mathrm{T}=25 {}^{circ} mathrm{C}$. Initially, small uniaxial cylindrical samples were prepared and reflowed in a reflow oven. These specimens were then mechanically cycled for various durations at $mathrm{T}=100$ °C. The measured cyclic stress-strain curves were then used to characterize the degradation of hysteresis loop properties (peak stress, hysteresis loop area, and plastic strain range) with high temperature mechanical cycling. As expected, the SAC305 samples cycled at elevated temperature demonstrated a lower peak stress and smaller loop area relative to the results for analogous specimens cycled at room temperature and the same strain range. Uniaxial tensile tests and creep tests at room temperature were also conducted on specimens that ha
{"title":"Mechanical Behavior and Microstructure Evolution in Lead Free Solders Subjected to Mechanical Cycling at Elevated Temperatures","authors":"M. A. Hoque, M. A. Haq, J. Suhling, P. Lall","doi":"10.1109/ECTC32696.2021.00366","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00366","url":null,"abstract":"Solder joints in electronic packages often experience fatigue failures due to cyclic mechanical stresses and strains in fluctuating temperature environments. These stresses and strains are induced by mismatches in coefficients of thermal expansion, and lead to damage accumulation that contributes to crack initiation, crack propagation, and eventually to failure. In our previous paper at ECTC 2020, we investigated the accumulation of damage in several solder materials (SAC305, $text{SAC} +text{Bi}$, and $text{SAC} +text{Bi}-text{Ni}-text{Sb}$) during mechanical cycling at room temperature. Circular cross-sectioned solder specimens were first reflowed, and these samples were then mechanically cycled for various durations using a Micro-Mechanical tester. Cyclic stress-strain, monotonic stress-strain, and creep tests were then conducted on the prior cycled samples. The cyclic stress-strain curves obtained were studied to observe the degradation of hysteresis loop properties (peak stress, hysteresis loop area, and plastic strain range) with mechanical cycling. The monotonic stress-strain and creep test data were plotted, and several mechanical properties were characterized for various levels of cycling. Using the data from these tests, we have been able to characterize and quantify the cycling induced damage through the observed degradations of several mechanical properties (elastic modulus, yield strength, ultimate strength, and creep strain rate) with the amount of prior cycling. All of the mechanical cyclic testing in our prior work and the work of others has been performed at room temperature ($mathrm{T}=25 {}^{circ} mathrm{C}$), and thus cannot be easily extended to thermal cycling applications. In our current work, we have extended our prior study to examine mechanical cycling at elevated temperature. In particular, we have examined lead free solders subjected to high temperature mechanical cycling at $mathrm{T}=100 {}^{circ} mathrm{C}$ and $mathrm{T}=125$ °C. Two solder alloys, SAC305 and $text{SAC} +text{Bi}$ (SAC_Q), have been investigated. In this paper, we report on the findings for SAC305 cycled at $mathrm{T}=100 {}^{circ} mathrm{C}$, and compare to the analogous results obtained for cycling at $mathrm{T}=25 {}^{circ} mathrm{C}$. Initially, small uniaxial cylindrical samples were prepared and reflowed in a reflow oven. These specimens were then mechanically cycled for various durations at $mathrm{T}=100$ °C. The measured cyclic stress-strain curves were then used to characterize the degradation of hysteresis loop properties (peak stress, hysteresis loop area, and plastic strain range) with high temperature mechanical cycling. As expected, the SAC305 samples cycled at elevated temperature demonstrated a lower peak stress and smaller loop area relative to the results for analogous specimens cycled at room temperature and the same strain range. Uniaxial tensile tests and creep tests at room temperature were also conducted on specimens that ha","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126700523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00137
Sangung Park, Jin-ho Yoon, Byoung Woong Moon, H. Jeong, Se Young Jeong, Seung Jae Lee, Kisu Joo
We demonstrated the new strip-level EMI shielding process with a spray method. Test PKGs having dimension of 300um width and l, 200um height were fabricated to evaluate feasibility of strip-level EMI shielding. As a result, spray can coat the total area of trench inner side wall with the special spray coating material and optimized spray parameters. Moreover, we measured the near-field shielding effectiveness(SE) of sputtering and spray films. 5.9um-thick sputtering one and 5.4um-thick Ag ink sprayed were prepared and measured in near E- and H-field in the range of 30MHz∼1.5GHz. In E-field, The SE results showed 21dB at 800MHz and 55dB at 100MHz. In H-field, the SE result of 5.4um-thick Ag ink was 1∼2dB higher than 5.9um-thick Sus/Cu/Sus film.
{"title":"Study on EMI Shielding at the PCB Strip Level with Conformal Spray Coating Process","authors":"Sangung Park, Jin-ho Yoon, Byoung Woong Moon, H. Jeong, Se Young Jeong, Seung Jae Lee, Kisu Joo","doi":"10.1109/ECTC32696.2021.00137","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00137","url":null,"abstract":"We demonstrated the new strip-level EMI shielding process with a spray method. Test PKGs having dimension of 300um width and l, 200um height were fabricated to evaluate feasibility of strip-level EMI shielding. As a result, spray can coat the total area of trench inner side wall with the special spray coating material and optimized spray parameters. Moreover, we measured the near-field shielding effectiveness(SE) of sputtering and spray films. 5.9um-thick sputtering one and 5.4um-thick Ag ink sprayed were prepared and measured in near E- and H-field in the range of 30MHz∼1.5GHz. In E-field, The SE results showed 21dB at 800MHz and 55dB at 100MHz. In H-field, the SE result of 5.4um-thick Ag ink was 1∼2dB higher than 5.9um-thick Sus/Cu/Sus film.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127014362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00215
Liangbiao Chen, Xuejun Fan, Yong Liu
Board-level reliability of wafer level chip scale package (WLCSP) is studied by both experiments and numerical modeling in this paper. The test condition is unbiased highly accelerated stress test (UHAST) followed by electrical inspections. One sample failed the test, and failure analysis showed that the failed sample has solder joint degradation and back metal peeling issues. To understand the failure mechanism, nonlinear hygro-thermal-mechanical modeling was performed. To simulate the moisture-induced stresses, the equivalent diffusion expansion coefficient (CDE) method is adopted. Simplification are made for UHAST condition with uniform moisture distribution but without the vapor pressure effects at equilibrium. A total of 7 numerical cases were studied and compared. The simulation results showed that the solder joint plastic strains increases significantly after mounting to the PCB and applying the UHAST conditions. This is mainly due to the CTE and CDE mismatch between the PCB and the device. On the other hand, the peeling stresses at the die and back metal decrease after PCB mounting under UHAST compared to device-only scenario. It is assumed that there is loss of adhesion between the die and the back metal under extreme moisture conditions. Finally, the simulation confirmed that reducing back coating thickness can effectively reduce both the solder joint plastic strains and metal-silicon interfacial stresses, thus providing a feasible solution to enhance the reliability of the package.
{"title":"Testing and Modeling of Board Level Reliability of WLCSP under UHAST Conditions","authors":"Liangbiao Chen, Xuejun Fan, Yong Liu","doi":"10.1109/ECTC32696.2021.00215","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00215","url":null,"abstract":"Board-level reliability of wafer level chip scale package (WLCSP) is studied by both experiments and numerical modeling in this paper. The test condition is unbiased highly accelerated stress test (UHAST) followed by electrical inspections. One sample failed the test, and failure analysis showed that the failed sample has solder joint degradation and back metal peeling issues. To understand the failure mechanism, nonlinear hygro-thermal-mechanical modeling was performed. To simulate the moisture-induced stresses, the equivalent diffusion expansion coefficient (CDE) method is adopted. Simplification are made for UHAST condition with uniform moisture distribution but without the vapor pressure effects at equilibrium. A total of 7 numerical cases were studied and compared. The simulation results showed that the solder joint plastic strains increases significantly after mounting to the PCB and applying the UHAST conditions. This is mainly due to the CTE and CDE mismatch between the PCB and the device. On the other hand, the peeling stresses at the die and back metal decrease after PCB mounting under UHAST compared to device-only scenario. It is assumed that there is loss of adhesion between the die and the back metal under extreme moisture conditions. Finally, the simulation confirmed that reducing back coating thickness can effectively reduce both the solder joint plastic strains and metal-silicon interfacial stresses, thus providing a feasible solution to enhance the reliability of the package.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129284194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00077
Liangxing Hu, S. Goh, J. Tao, Y. Lim, P. Zhao, Michael Joo Zhong Lim, C. S. Tan
In this article, we report in-depth parametric study of argon/nitrogen plasma-activated copper surfaces for copper-copper die-to-die direct bonding carried out at room temperature in cleanroom ambient condition. Surface analyses (e.g. water contact angle and X-ray photoelectron spectroscopy) are performed on the control, argon or nitrogen plasma-activated copper surfaces. The results reveal that a thin layer of copper nitride is formed on the copper surface with the nitrogen plasma treatment, which is a potentially effective passivation layer to control the surface oxidation. By fine-tuning the argon or nitrogen plasma (exposure time, plasma power and plasma species), a bonding strength of ∼6 MPa is achieved, and the bonded interface has a specific contact resistivity of $sim 6.0times 10^{-4} Omega cdot text{cm}^{2}$. Therefore, an optimal plasma recipe is obtained for argon/nitrogen plasma-activated copper-copper direct bonding. This bonding technique is suitable for high-throughput three-dimensional wafer bonding and advanced packaging.
{"title":"In-Depth Parametric Study of Ar or N2 Plasma Activated Cu Surfaces for Cu-Cu Direct Bonding","authors":"Liangxing Hu, S. Goh, J. Tao, Y. Lim, P. Zhao, Michael Joo Zhong Lim, C. S. Tan","doi":"10.1109/ECTC32696.2021.00077","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00077","url":null,"abstract":"In this article, we report in-depth parametric study of argon/nitrogen plasma-activated copper surfaces for copper-copper die-to-die direct bonding carried out at room temperature in cleanroom ambient condition. Surface analyses (e.g. water contact angle and X-ray photoelectron spectroscopy) are performed on the control, argon or nitrogen plasma-activated copper surfaces. The results reveal that a thin layer of copper nitride is formed on the copper surface with the nitrogen plasma treatment, which is a potentially effective passivation layer to control the surface oxidation. By fine-tuning the argon or nitrogen plasma (exposure time, plasma power and plasma species), a bonding strength of ∼6 MPa is achieved, and the bonded interface has a specific contact resistivity of $sim 6.0times 10^{-4} Omega cdot text{cm}^{2}$. Therefore, an optimal plasma recipe is obtained for argon/nitrogen plasma-activated copper-copper direct bonding. This bonding technique is suitable for high-throughput three-dimensional wafer bonding and advanced packaging.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130575218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00015
Sang Kyu Kim, Sangwook Park, S. Cha, Sang Nam Jung, Gyongbum Kim, D. Oh, Joonsung Kim, Sang-Uk Kim, Seok Won Lee
The state of the art high-speed digital systems for artificial intelligence, 5G mobile communication, and network servers demand enormous amount of data transmission, wider bandwidth, and faster data rate than the conventional technology. This requires packages to incorporate interconnects with very high density, but to provide cost effective manufacturing process and better performance at the same time. The new hybrid package platform based on the panel level package (PLP) interposer mounted on the high density interconnect (HDI) substrate can be a promising solution for these requirements. The PLP interposer can provide fine pitch to support considerable number of signal traces while the HDI substrate can be served as relatively inexpensive interconnects after fanning-out signals out of the interposer. Another merit of the PLP interposer is to provide lower inductance from bump to package decoupling capacitors when implementing land side capacitors underneath the PLP interposer because the PLP can have thinner substrate thickness than the Ajinomoto build-up film (ABF). The ABF interposer can be an alternative to the PLP interposer. Although the ABF interposer has thicker copper and dielectric layers than the PLP interposer, it can achieve lower resistance for the required characteristic impedance of the high-speed IO. However, the presence of joint balls between the interposer and the HDI substrate can introduce additional impedance discontinuities, which can degrade the signal integrity. Hence, optimized package design and analysis are key factors for designing such package platforms. In this paper, the PLP interposer, the ABF interposer, and the conventional package are compared for the package structure and the design optimization perspectives. Each package platform topology is illustrated, its merits and risks are discussed. For the design optimization, the traces on the interposers and the substrates are described by simple T-line models while the LC model is adopted for vertical structures including vias, pads, and balls. The benefit of using the simple model is to provide the package design guide for the performance optimization of the package and to minimize the number of package design iterations. The package design improvement will be illustrated by the insertion loss, return loss, and time domain reflectometry (TDR). Our model provides an efficient way to improve package performance, and shows good correlations with the real design.
{"title":"Package Design Optimization of the Fan-out Interposer System","authors":"Sang Kyu Kim, Sangwook Park, S. Cha, Sang Nam Jung, Gyongbum Kim, D. Oh, Joonsung Kim, Sang-Uk Kim, Seok Won Lee","doi":"10.1109/ECTC32696.2021.00015","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00015","url":null,"abstract":"The state of the art high-speed digital systems for artificial intelligence, 5G mobile communication, and network servers demand enormous amount of data transmission, wider bandwidth, and faster data rate than the conventional technology. This requires packages to incorporate interconnects with very high density, but to provide cost effective manufacturing process and better performance at the same time. The new hybrid package platform based on the panel level package (PLP) interposer mounted on the high density interconnect (HDI) substrate can be a promising solution for these requirements. The PLP interposer can provide fine pitch to support considerable number of signal traces while the HDI substrate can be served as relatively inexpensive interconnects after fanning-out signals out of the interposer. Another merit of the PLP interposer is to provide lower inductance from bump to package decoupling capacitors when implementing land side capacitors underneath the PLP interposer because the PLP can have thinner substrate thickness than the Ajinomoto build-up film (ABF). The ABF interposer can be an alternative to the PLP interposer. Although the ABF interposer has thicker copper and dielectric layers than the PLP interposer, it can achieve lower resistance for the required characteristic impedance of the high-speed IO. However, the presence of joint balls between the interposer and the HDI substrate can introduce additional impedance discontinuities, which can degrade the signal integrity. Hence, optimized package design and analysis are key factors for designing such package platforms. In this paper, the PLP interposer, the ABF interposer, and the conventional package are compared for the package structure and the design optimization perspectives. Each package platform topology is illustrated, its merits and risks are discussed. For the design optimization, the traces on the interposers and the substrates are described by simple T-line models while the LC model is adopted for vertical structures including vias, pads, and balls. The benefit of using the simple model is to provide the package design guide for the performance optimization of the package and to minimize the number of package design iterations. The package design improvement will be illustrated by the insertion loss, return loss, and time domain reflectometry (TDR). Our model provides an efficient way to improve package performance, and shows good correlations with the real design.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123357236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00181
F. Eid, Aastha Uppal, J. Swan
This paper presents cold spray as a nascent semiconductor packaging capability with promising thermomechanical applications. Cold spray enables fast, low temperature, solid-state additive manufacturing of die backside coatings with near-bulk properties and low contact resistances. With appropriate process and material optimization, those coatings can reduce package warpage at reflow temperatures and improve heat spreading from die hotspots, enabling higher processor power and performance. Experiments and simulations are presented which demonstrate the advantages of the proposed die backside cold spray architecture and the breakthrough capabilities of the cold spray process itself, positioning cold spray as a powerful new packaging tool with far-reaching potential.
{"title":"Cold Spray: A Disruptive Technology for Enabling Novel Packaging Thermomechanical Solutions","authors":"F. Eid, Aastha Uppal, J. Swan","doi":"10.1109/ECTC32696.2021.00181","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00181","url":null,"abstract":"This paper presents cold spray as a nascent semiconductor packaging capability with promising thermomechanical applications. Cold spray enables fast, low temperature, solid-state additive manufacturing of die backside coatings with near-bulk properties and low contact resistances. With appropriate process and material optimization, those coatings can reduce package warpage at reflow temperatures and improve heat spreading from die hotspots, enabling higher processor power and performance. Experiments and simulations are presented which demonstrate the advantages of the proposed die backside cold spray architecture and the breakthrough capabilities of the cold spray process itself, positioning cold spray as a powerful new packaging tool with far-reaching potential.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120852178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00159
S. Yeh, P. Lin, C. Hsu, Y. S. Lin, J. H. Wang, P. Lai, C. H. Chen, Y. Lee, M. Yew, S. Cheng, S. Jeng
In order to ensure good performance and long-term reliability of fan-out package, the interfacial strength of Underfill (UF) and polymer (PM) lamination plays an important role because of physical strength and electrical requirement. Accordingly, the present study presents a combined experimental and finite element modeling approach for quantitatively determining the interfacial adhesive strength of UF-PM structures. In the proposed approach, four points bending (FPB) testing is used to evaluate the adhesion strength between UF-PM. The test results are used to determine the critical strain energy release rate ($G_{c}$) at the UF-PM interface. The experimental results are then taken as a reference for finite element (FE) simulations. The virtual crack closure technique (VCCT) in FE model is introduced here for risk assessment such as delamination or crack risk at the interface of UF-PM. In general, the results confirm that the proposed predictive modeling approach provides an effective means of evaluating the delamination risk in UF-PM systems. As such, it provides a convenient and cost-effective method for evaluating the new material interface of UF-PM.
{"title":"Fracture Modeling and Characterization of Underfill/Polymer Interfacial Adhesion in RDL Interposer Package","authors":"S. Yeh, P. Lin, C. Hsu, Y. S. Lin, J. H. Wang, P. Lai, C. H. Chen, Y. Lee, M. Yew, S. Cheng, S. Jeng","doi":"10.1109/ECTC32696.2021.00159","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00159","url":null,"abstract":"In order to ensure good performance and long-term reliability of fan-out package, the interfacial strength of Underfill (UF) and polymer (PM) lamination plays an important role because of physical strength and electrical requirement. Accordingly, the present study presents a combined experimental and finite element modeling approach for quantitatively determining the interfacial adhesive strength of UF-PM structures. In the proposed approach, four points bending (FPB) testing is used to evaluate the adhesion strength between UF-PM. The test results are used to determine the critical strain energy release rate ($G_{c}$) at the UF-PM interface. The experimental results are then taken as a reference for finite element (FE) simulations. The virtual crack closure technique (VCCT) in FE model is introduced here for risk assessment such as delamination or crack risk at the interface of UF-PM. In general, the results confirm that the proposed predictive modeling approach provides an effective means of evaluating the delamination risk in UF-PM systems. As such, it provides a convenient and cost-effective method for evaluating the new material interface of UF-PM.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114215772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00260
Sridhar Sivapurapu, R. Chen, M. Rehman, Kimiyuki Kanno, Takenori Kakutani, M. Letz, Fuhan Liu, S. Sitaraman, M. Swaminathan
Glass has been shown to be a capable core substrate material for high frequency applications. In this paper we examine the capabilities of ultra-thin glass as a flexible material that can be used for high frequency flexible applications. The two stack-ups discussed in this paper are $60 mumathrm{m}$ in total thickness with a core glass substrate (Schott AF32) of $30 mumathrm{m}$ thickness. One stack-up uses $15 mumathrm{m}$ JSR GT-N01 as a buildup dielectric and the other uses $15 mumathrm{m}$ Taiyo Photo Imageable Dielectric. Since neither of these stack-ups have previously been electrically characterized, this paper characterizes both stack-ups up to 110 GHz using microstrip ring resonators (MRRs) and conductor backed coplanar waveguides (CBCPWs). Based on the characterization results, these stack-ups compare favorably against other stack-ups used for applications in this frequency range. After completing the electrical characterization, the Taiyo PID stack-up is also mechanically characterized for its flexibility using Free Arc Bending. The Free Arc Bending test shows that the ultra-thin glass stack-up is suitable for high frequency bending applications as the tested samples are capable of bending up to a separation of 33% of the sample's total length, displaying the capabilities of this ultra-thin glass substrate as a good candidate for a flexible substrate.
玻璃已被证明是一个有能力的核心基板材料的高频应用。在本文中，我们研究了超薄玻璃作为一种可用于高频柔性应用的柔性材料的能力。本文讨论的两个堆叠层的总厚度为$60 mu mathm {m}$，核心玻璃基板(Schott AF32)的厚度为$30 mu mathm {m}$。一个堆叠使用$15 mumathrm{m}$ JSR GT-N01作为累积介质，另一个使用$15 mumathrm{m}$ Taiyo照片可成像介质。由于这两种堆叠先前都没有电特性，因此本文使用微带环形谐振器(mrr)和导体背侧共面波导(cbcpw)表征了高达110 GHz的堆叠。根据表征结果，这些堆叠与用于该频率范围内应用的其他堆叠相比具有优势。在完成电气特性之后，Taiyo PID堆叠也因其使用自由电弧弯曲的灵活性而具有机械特性。自由弧弯曲测试表明，超薄玻璃堆叠适用于高频弯曲应用，因为测试样品能够弯曲到样品总长度的33%，显示了这种超薄玻璃基板作为柔性基板的良好候选的能力。
{"title":"Flexible and Ultra-Thin Glass Substrates for RF Applications","authors":"Sridhar Sivapurapu, R. Chen, M. Rehman, Kimiyuki Kanno, Takenori Kakutani, M. Letz, Fuhan Liu, S. Sitaraman, M. Swaminathan","doi":"10.1109/ECTC32696.2021.00260","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00260","url":null,"abstract":"Glass has been shown to be a capable core substrate material for high frequency applications. In this paper we examine the capabilities of ultra-thin glass as a flexible material that can be used for high frequency flexible applications. The two stack-ups discussed in this paper are $60 mumathrm{m}$ in total thickness with a core glass substrate (Schott AF32) of $30 mumathrm{m}$ thickness. One stack-up uses $15 mumathrm{m}$ JSR GT-N01 as a buildup dielectric and the other uses $15 mumathrm{m}$ Taiyo Photo Imageable Dielectric. Since neither of these stack-ups have previously been electrically characterized, this paper characterizes both stack-ups up to 110 GHz using microstrip ring resonators (MRRs) and conductor backed coplanar waveguides (CBCPWs). Based on the characterization results, these stack-ups compare favorably against other stack-ups used for applications in this frequency range. After completing the electrical characterization, the Taiyo PID stack-up is also mechanically characterized for its flexibility using Free Arc Bending. The Free Arc Bending test shows that the ultra-thin glass stack-up is suitable for high frequency bending applications as the tested samples are capable of bending up to a separation of 33% of the sample's total length, displaying the capabilities of this ultra-thin glass substrate as a good candidate for a flexible substrate.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114338904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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