Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00256
B. Kumari, Rahul Kumar, Manodipan Sahoo, Rohit Sharma
In this paper, we report qualitative comparative signal integrity analysis of self-heated Ferric Chloride ($FeCl_{3}$) doped Top Contacted Multilayer Vertical Graphene Nanoribbon (TC-MLVGNR) interconnect and its comparison with copper and $FeCl_{3}$ doped Top Contacted Multilayer Horizontal Graphene Nanoribbon (TC-MLHGNR) interconnects. A coupled three-line interconnect system is utilized in this study. The dimensions of interconnects are taken as per the IRDS-2018 roadmap for 7nm technology node. In realistic scenario, roughness is present on interconnect surfaces and it plays a major role at lower technology nodes. Roughness is inevitable during the fabrication process. It helps to provide the adhesion between dielectric and interconnect. So to capture the realistic scenario, we are considering rough Multilayer Graphene Nanoribbon (MLGNR) interconnects to compare with conventional rough copper interconnects. When compared to rough copper, smooth copper and TC-MLHGNR interconnects, delay of TC-MLVGNR interconnect is reduced by 59%, 51% and 62%, respectively. Even if we consider self-heating, its performance is better than rough copper, smooth copper and TC-MLHGNR interconnects by 26%, 11% and 54%, respectively. It is worth noting that rough TC-MLHGNRs induce the highest delay especially when self-heating effect is considered. Also, this study proves that TC-MLVGNR interconnects outperform TC-MLHGNR interconnects in terms of thermal efficiency by 15% thus making it a potential interconnect candidate for ultra-scaled technology nodes.
{"title":"Performance Analysis of Self Heated Multilayer Vertical Graphene Nanoribbon Interconnects","authors":"B. Kumari, Rahul Kumar, Manodipan Sahoo, Rohit Sharma","doi":"10.1109/ECTC32696.2021.00256","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00256","url":null,"abstract":"In this paper, we report qualitative comparative signal integrity analysis of self-heated Ferric Chloride ($FeCl_{3}$) doped Top Contacted Multilayer Vertical Graphene Nanoribbon (TC-MLVGNR) interconnect and its comparison with copper and $FeCl_{3}$ doped Top Contacted Multilayer Horizontal Graphene Nanoribbon (TC-MLHGNR) interconnects. A coupled three-line interconnect system is utilized in this study. The dimensions of interconnects are taken as per the IRDS-2018 roadmap for 7nm technology node. In realistic scenario, roughness is present on interconnect surfaces and it plays a major role at lower technology nodes. Roughness is inevitable during the fabrication process. It helps to provide the adhesion between dielectric and interconnect. So to capture the realistic scenario, we are considering rough Multilayer Graphene Nanoribbon (MLGNR) interconnects to compare with conventional rough copper interconnects. When compared to rough copper, smooth copper and TC-MLHGNR interconnects, delay of TC-MLVGNR interconnect is reduced by 59%, 51% and 62%, respectively. Even if we consider self-heating, its performance is better than rough copper, smooth copper and TC-MLHGNR interconnects by 26%, 11% and 54%, respectively. It is worth noting that rough TC-MLHGNRs induce the highest delay especially when self-heating effect is considered. Also, this study proves that TC-MLVGNR interconnects outperform TC-MLHGNR interconnects in terms of thermal efficiency by 15% thus making it a potential interconnect candidate for ultra-scaled technology nodes.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125532735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00144
Sajay Bhuvanendran Nair Gourikutty, J. Alton, Desmond Yeo, Kok Keng Chua, Sharon Lim Seow Huang, S. Bhattacharya
Advanced wafer-level packaging has been successfully used in state-of-the-art FPGA ICs, smart-phone application processors, and GPU units to provide power-performance-form factor boosts that are not obtainable by conventional packaging. In addition, very fine pitch interconnects approaches such as high-density fan-out on organic substrates and fine pitch silicon interposers enable the need for heterogeneous integration and scaling demand. However, this increased the intricacy of package architecture which leads to a higher possibility of failures making it challenging to attain high yield in volume production. Therefore, high failure analysis success is required in this area and without accurate fault localization, failure analysis is difficult and often reliant on a best-guess approach which tends to be time-consuming and relatively expensive to be implemented. In this work, we demonstrated a rapid methodology for non-destructive accurate defect isolation at various levels of the advanced ICs preventing potential artifacts. First, fault isolation is verified on a 2.5D advanced package where an open fault is successfully localized after the micro-bump in the die side metal layer. Secondly, the methodology is validated by employing fine pitch interposer chip samples by isolating defects including high resistance fault in RDL metal lines.
{"title":"Case studies of accurate fault localization in advanced packages","authors":"Sajay Bhuvanendran Nair Gourikutty, J. Alton, Desmond Yeo, Kok Keng Chua, Sharon Lim Seow Huang, S. Bhattacharya","doi":"10.1109/ECTC32696.2021.00144","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00144","url":null,"abstract":"Advanced wafer-level packaging has been successfully used in state-of-the-art FPGA ICs, smart-phone application processors, and GPU units to provide power-performance-form factor boosts that are not obtainable by conventional packaging. In addition, very fine pitch interconnects approaches such as high-density fan-out on organic substrates and fine pitch silicon interposers enable the need for heterogeneous integration and scaling demand. However, this increased the intricacy of package architecture which leads to a higher possibility of failures making it challenging to attain high yield in volume production. Therefore, high failure analysis success is required in this area and without accurate fault localization, failure analysis is difficult and often reliant on a best-guess approach which tends to be time-consuming and relatively expensive to be implemented. In this work, we demonstrated a rapid methodology for non-destructive accurate defect isolation at various levels of the advanced ICs preventing potential artifacts. First, fault isolation is verified on a 2.5D advanced package where an open fault is successfully localized after the micro-bump in the die side metal layer. Secondly, the methodology is validated by employing fine pitch interposer chip samples by isolating defects including high resistance fault in RDL metal lines.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125673173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00245
A. Alam, M. Molter, A. Kapoor, B. Gaonkar, S. Benedict, L. Macyszyn, M. S. Joseph, S. Iyer
A elegant extremely flexible Fan-Out Wafer-Level Packaging (FOWLP) based fully integrated bipolar multi-channel (up to 12 channels) surface electromyography (sEMG) device and assembly is demonstrated for intraoperative neurological monitoring (IONM) for complex spine surgeries and post-op physiological monitoring. It includes twenty gold-capped vertically corrugated flexible dry copper electrodes, Bluetooth wireless data transfer, a multichannel sEMG data acquisition and processing dielet, rechargeable energy storage and an ergonomic reusable adhesive for ease of use. This completely biocompatible and wearable system is highly flexible, thin (1 mm), light weight (< 5 g) and can be used to monitor neuro-muscular activations for IONM as well as for general physiological monitoring.
{"title":"Flexible heterogeneously integrated low form factor wireless multi-channel surface electromyography (sEMG) device","authors":"A. Alam, M. Molter, A. Kapoor, B. Gaonkar, S. Benedict, L. Macyszyn, M. S. Joseph, S. Iyer","doi":"10.1109/ECTC32696.2021.00245","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00245","url":null,"abstract":"A elegant extremely flexible Fan-Out Wafer-Level Packaging (FOWLP) based fully integrated bipolar multi-channel (up to 12 channels) surface electromyography (sEMG) device and assembly is demonstrated for intraoperative neurological monitoring (IONM) for complex spine surgeries and post-op physiological monitoring. It includes twenty gold-capped vertically corrugated flexible dry copper electrodes, Bluetooth wireless data transfer, a multichannel sEMG data acquisition and processing dielet, rechargeable energy storage and an ergonomic reusable adhesive for ease of use. This completely biocompatible and wearable system is highly flexible, thin (1 mm), light weight (< 5 g) and can be used to monitor neuro-muscular activations for IONM as well as for general physiological monitoring.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116462269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00093
H. Nishikawa, Jianhao Wang, K. Kariya, N. Masago
To meet the increasing demand of the next-generation power conversion circuit on the high-power density, high operating temperature and miniaturization, many novel packaging methods have been investigation. Due to high remelting temperature and low cost transient liquid phase (TLP) bonding technology shows the great potential. In this paper, ENIG-finished Cu disks were bonded by In-coated Cu sheet through TLP bonding at 250°C and the shear test as well as fracture analysis during thermal aging was conducted. The bonded joint with the Cu2In, Au-In-Cu and Ni2In3IMC interface showed a strength of 19.85 MPa, although some defects could be observed. During thermal aging, the Cu2In and Ni2In3coarsened and the interface became more compact. It was very interesting that the shear strength of joint was increased by 81.21 after 1008 h thermal aging at 250°C. Although the fracture location was changed during thermal aging, the fracture surface always showed brittle characteristics.
为了满足下一代功率转换电路对高功率密度、高工作温度和小型化日益增长的要求，人们研究了许多新的封装方法。瞬态液相(TLP)键合技术由于重熔温度高、成本低而显示出巨大的发展潜力。本文采用In-coated Cu sheet在250℃下通过TLP焊接enigg -finished Cu disks，并进行了剪切试验和热时效过程中的断裂分析。与Cu2In、Au-In-Cu和Ni2In3IMC界面结合的接头强度为19.85 MPa，但存在一定缺陷。在热时效过程中，Cu2In和ni2in3晶粒变粗，界面变得更加致密。在250℃热时效1008 h后，接头的抗剪强度提高了81.21倍。在热时效过程中，虽然断口位置发生了变化，但断口表面始终呈现脆性特征。
{"title":"The reliability of ENIG joint bonded by In-coated Cu sheet","authors":"H. Nishikawa, Jianhao Wang, K. Kariya, N. Masago","doi":"10.1109/ECTC32696.2021.00093","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00093","url":null,"abstract":"To meet the increasing demand of the next-generation power conversion circuit on the high-power density, high operating temperature and miniaturization, many novel packaging methods have been investigation. Due to high remelting temperature and low cost transient liquid phase (TLP) bonding technology shows the great potential. In this paper, ENIG-finished Cu disks were bonded by In-coated Cu sheet through TLP bonding at 250°C and the shear test as well as fracture analysis during thermal aging was conducted. The bonded joint with the Cu2In, Au-In-Cu and Ni2In3IMC interface showed a strength of 19.85 MPa, although some defects could be observed. During thermal aging, the Cu2In and Ni2In3coarsened and the interface became more compact. It was very interesting that the shear strength of joint was increased by 81.21 after 1008 h thermal aging at 250°C. Although the fracture location was changed during thermal aging, the fracture surface always showed brittle characteristics.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122466756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00118
S. Yoneda, Kenya Adachi, K. Kobayashi, Daisaku Matsukawa, Mamoru Sasaki, T. Itabashi, Toshiaki Shirasaka, T. Shibata
Cu/insulating material hybrid bonding technology was a promising process for high performance three-dimensional integrated package. A novel polyimide (PI) and thermal compression bonding (TCB) process were proposed for chip to wafer hybrid bonding. The new PI was developed by re-designing key components of the formulation. It showed high adhesion after TCB and high reliability performance. For the PI to PI bonding process evaluation, there were not any visible voids after pre-bonding at 250-350 °C and after TCB at 300 °C. Cu/PI co-planarization process was confirmed, and the PI showed a practical removal rate even though the PI was cured at high temperature. Furthermore, the PI showed highly smooth surface after CMP.
{"title":"A Novel Photosensitive Polyimide Adhesive Material for Hybrid Bonding Processing","authors":"S. Yoneda, Kenya Adachi, K. Kobayashi, Daisaku Matsukawa, Mamoru Sasaki, T. Itabashi, Toshiaki Shirasaka, T. Shibata","doi":"10.1109/ECTC32696.2021.00118","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00118","url":null,"abstract":"Cu/insulating material hybrid bonding technology was a promising process for high performance three-dimensional integrated package. A novel polyimide (PI) and thermal compression bonding (TCB) process were proposed for chip to wafer hybrid bonding. The new PI was developed by re-designing key components of the formulation. It showed high adhesion after TCB and high reliability performance. For the PI to PI bonding process evaluation, there were not any visible voids after pre-bonding at 250-350 °C and after TCB at 300 °C. Cu/PI co-planarization process was confirmed, and the PI showed a practical removal rate even though the PI was cured at high temperature. Furthermore, the PI showed highly smooth surface after CMP.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122098034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00170
Mike Tsai, Ryan Chiu, Ming-fan Tsai, Eric He, Erico Yang, Tim Chang, Frank Chu, J. Chen
Double Side SiP is hot packaging solution by using double side SMT technology and dual side molding to shrink the overall module size. The calculation of package size can be reduce over 40% PCB placement area from 8 x 8mm to 6 x 6mm. Based on module level warpage and thermal dissipation performance point of view, the simulation and experiment including the molding process study with difference molding compound selection DOE to verify Double Side SiP warpage performance. The advantage of Double Side SiP, simplify PKG I/O Count (10% reduction based on PMIC of portable), to improve power supply efficiency and reduce noise emission. From electrical integration point of view, due to shorter signal transmission path to get good electrical performance (SI & PI) than other side by side flip chip base structure. From thermal performance, high thermal solution can be improved $mathrm{24}sim mathrm{38}%$. The Double Side SiP module can provide an advanced solution to address the module size, cost, performance, and time-to-market requirement for 5G and IoT marketing. The performance verification in this paper will proceed simulation and measurement. The reliability testing verification was including the TCT, HTSL and u-HAST (Temperature Cycle Test, High Temperature Storage Test, un-bias HAST) results as a verification for Double Side SiP structure. Finally, this paper have Double Side SiP structure and feasibility data for future 5G and IoT devices application.
{"title":"Heterogeneous Integration of Double Side SiP for IoT and 5G Application","authors":"Mike Tsai, Ryan Chiu, Ming-fan Tsai, Eric He, Erico Yang, Tim Chang, Frank Chu, J. Chen","doi":"10.1109/ECTC32696.2021.00170","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00170","url":null,"abstract":"Double Side SiP is hot packaging solution by using double side SMT technology and dual side molding to shrink the overall module size. The calculation of package size can be reduce over 40% PCB placement area from 8 x 8mm to 6 x 6mm. Based on module level warpage and thermal dissipation performance point of view, the simulation and experiment including the molding process study with difference molding compound selection DOE to verify Double Side SiP warpage performance. The advantage of Double Side SiP, simplify PKG I/O Count (10% reduction based on PMIC of portable), to improve power supply efficiency and reduce noise emission. From electrical integration point of view, due to shorter signal transmission path to get good electrical performance (SI & PI) than other side by side flip chip base structure. From thermal performance, high thermal solution can be improved $mathrm{24}sim mathrm{38}%$. The Double Side SiP module can provide an advanced solution to address the module size, cost, performance, and time-to-market requirement for 5G and IoT marketing. The performance verification in this paper will proceed simulation and measurement. The reliability testing verification was including the TCT, HTSL and u-HAST (Temperature Cycle Test, High Temperature Storage Test, un-bias HAST) results as a verification for Double Side SiP structure. Finally, this paper have Double Side SiP structure and feasibility data for future 5G and IoT devices application.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116624565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00058
C. Okoro, S. Jayaraman, S. Pollard
This work aims at understanding thermo-mechanically induced cracks in through-glass via (TGV) made in Corning® HPFS® Fused Silica glass substrate, as well as to study the effect of thermal shock on the propagation of cracks. Two types of thermo-mechanically induced cracks were observed; radial cracks formed during heating and circumferential cracks that are formed during cooling. These cracks were initiated as a result of high tensile stresses in the circumferential and radial directions respectively. Thermal shock was found to lead to the growth of radial cracks. After 1000 cycles, catastrophic failures occurred due to the networking of radial cracks from adjacent vias. This suggests that TGV pitch dimension is a critical parameter that needs to be considered in order to limit catastrophic failures. On the other hand, no crack growth was observed for circumferential cracks in the in-plane direction, even after 1000 cycles of thermal shock. These results indicate that the prevention of radial and circumferential crack formation is the most critical step in mitigating risk of failure concerns, thus, the need for optimized crack-free metallized TGV solutions. Through TGV shape re-design, control of Cu metallization thickness as well as the use of lower annealing heating rate, these thermo-mechanically driven cracks were successfully mitigated in a previously reported work.
{"title":"Monitoring of the Effect of Thermal Shock on Crack Growth in Copper Through-Glass Via Substrates","authors":"C. Okoro, S. Jayaraman, S. Pollard","doi":"10.1109/ECTC32696.2021.00058","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00058","url":null,"abstract":"This work aims at understanding thermo-mechanically induced cracks in through-glass via (TGV) made in Corning® HPFS® Fused Silica glass substrate, as well as to study the effect of thermal shock on the propagation of cracks. Two types of thermo-mechanically induced cracks were observed; radial cracks formed during heating and circumferential cracks that are formed during cooling. These cracks were initiated as a result of high tensile stresses in the circumferential and radial directions respectively. Thermal shock was found to lead to the growth of radial cracks. After 1000 cycles, catastrophic failures occurred due to the networking of radial cracks from adjacent vias. This suggests that TGV pitch dimension is a critical parameter that needs to be considered in order to limit catastrophic failures. On the other hand, no crack growth was observed for circumferential cracks in the in-plane direction, even after 1000 cycles of thermal shock. These results indicate that the prevention of radial and circumferential crack formation is the most critical step in mitigating risk of failure concerns, thus, the need for optimized crack-free metallized TGV solutions. Through TGV shape re-design, control of Cu metallization thickness as well as the use of lower annealing heating rate, these thermo-mechanically driven cracks were successfully mitigated in a previously reported work.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116739069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00218
R. Höhne, K. Meier, A. Dasgupta, D. Leslie, K. Bock
In this work, fatigue damage caused to solder joints in printed wiring assemblies due to the superposition of harmonic vibration and temperature is studied along with different damage superposition approaches. In this work, a non-linear interactive damage superposition method is used, with temperature-dependent vibration damage coefficients that are interpolated from isothermal vibration experiments at selected temperatures. The temperature range −40°C to 125 °C was segmented into multiple sub-segments for this interpolation. By applying these measures, a new procedure for an improved incremental damage superposition approach (IDSA) was developed in this work. This new procedure was then used to superpose the vibration and temperature cycling loads to forecast the fatigue life of SAC105 solder joints for leadless chip resistors under simultaneous vibration and temperature cycling loads. Potential failure sites of the solder joint have been successfully investigated by utilizing this new procedure. Using the developed model, accelerated testing profiles are designed such that the vibration fatigue and temperature cycling fatigue damage are comparable and cause failure in approximately 250 temperature cycles.
{"title":"Improved Damage Modeling for Solder Joints under Combined Vibration and Temperature Cycling Loading","authors":"R. Höhne, K. Meier, A. Dasgupta, D. Leslie, K. Bock","doi":"10.1109/ECTC32696.2021.00218","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00218","url":null,"abstract":"In this work, fatigue damage caused to solder joints in printed wiring assemblies due to the superposition of harmonic vibration and temperature is studied along with different damage superposition approaches. In this work, a non-linear interactive damage superposition method is used, with temperature-dependent vibration damage coefficients that are interpolated from isothermal vibration experiments at selected temperatures. The temperature range −40°C to 125 °C was segmented into multiple sub-segments for this interpolation. By applying these measures, a new procedure for an improved incremental damage superposition approach (IDSA) was developed in this work. This new procedure was then used to superpose the vibration and temperature cycling loads to forecast the fatigue life of SAC105 solder joints for leadless chip resistors under simultaneous vibration and temperature cycling loads. Potential failure sites of the solder joint have been successfully investigated by utilizing this new procedure. Using the developed model, accelerated testing profiles are designed such that the vibration fatigue and temperature cycling fatigue damage are comparable and cause failure in approximately 250 temperature cycles.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129411967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Semiconductor products used in high-performance computing (HPC) and artificial intelligence (AI) applications require higher memory bandwidth, greater input/output (I/O) count, better power delivery network (PDN) performance and improved heat dissipation characteristics. To meet these requirements, a 2.5D package architecture with a Through Silicon Via (TSV)-bearing silicon (Si) interposer is mainly used in volume production. However, a redistribution layer (RDL) interposer is emerging as a cost effective and higher performance alternative. To implement an improved high-performance, multifunctional interposer, S-Connect technology has been developed that uses a multi-chip, fan-out interposer with various functionalities, such as a die-to-die (D2D) connection, where integrated passive devices (IPDs) and active devices can be integrated. If active devices are included in the interposer, S-Connect technology enables a 3D system where multiple active chips are vertically integrated. In this paper, the S-Connect design differences from the existing 2.5D package using Si interposer with TSVs and its fabrication process flow are explained. S-Connect technology provides manufacturing flexibility to apply various types of interconnects. Two different connect features will be discussed. Firstly, a Si connect will be explored having a back end of line (BEOL) and TSV approach that can provide the same die-to-die routing with smaller than $1-mu mathrm{m}$ line/space (L/S) and vertical connections as a Si interposer. The second option uses a multilayer RDL, which can be fabricated on Si, glass and even on the epoxy mold compound (EMC). The RDL can also provide vertical interconnects such as TSVs in Si. For demonstration, a test vehicle (TV) with one logic chip and two memory chips mounted on a multi-chip, fan-out interposer with an area approximately 1.5 times larger than the reticle was used. The interposer consists of two connect chips with $2-mu mathrm{m}$ L/S RDL and 6 mechanical IPDs located under the logic die. Two types of the connect chips were used - RDL on Si wafer and RDL on EMC having TMVs. The top die to interposer joints were made using $mu$-bumps with $25-mu mathrm{m}$ size on a $45-mu mathrm{m}$ pitch in the logic and $25-mu mathrm{m}$ size on a $55-mu mathrm{m}$ pitch in the memory die. Both the top and bottom sides of the fan-out interposer have a single layer of RDL. To interconnect the bottom side of the interposer and the package substrate, copper (Cu) pillar C4 bumps at $150-mu mathrm{m}$ pitch were formed. Once the top die and interposer assembly is complete, the subsequent processes are standard flip chip ball grid array (FCBGA) process flows. Moisture sensitivity and long-term reliability test results will be presented as well as warpage behavior, which is critical for the large body packages. Lastly, the advantages of the S-Connect package will be compared to other 2.5D and flip chip solutions in terms of manufacturability, ability to
{"title":"S-Connect Fan-out Interposer For Next Gen Heterogeneous Integration","authors":"JiHun Lee, Gamhan Yong, Minsu Jeong, JongHyun Jeon, Donghoon Han, MinKeon Lee, Wonchul Do, EunSook Sohn, M. Kelly, David Hiner, JinYoung Khim","doi":"10.1109/ECTC32696.2021.00027","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00027","url":null,"abstract":"Semiconductor products used in high-performance computing (HPC) and artificial intelligence (AI) applications require higher memory bandwidth, greater input/output (I/O) count, better power delivery network (PDN) performance and improved heat dissipation characteristics. To meet these requirements, a 2.5D package architecture with a Through Silicon Via (TSV)-bearing silicon (Si) interposer is mainly used in volume production. However, a redistribution layer (RDL) interposer is emerging as a cost effective and higher performance alternative. To implement an improved high-performance, multifunctional interposer, S-Connect technology has been developed that uses a multi-chip, fan-out interposer with various functionalities, such as a die-to-die (D2D) connection, where integrated passive devices (IPDs) and active devices can be integrated. If active devices are included in the interposer, S-Connect technology enables a 3D system where multiple active chips are vertically integrated. In this paper, the S-Connect design differences from the existing 2.5D package using Si interposer with TSVs and its fabrication process flow are explained. S-Connect technology provides manufacturing flexibility to apply various types of interconnects. Two different connect features will be discussed. Firstly, a Si connect will be explored having a back end of line (BEOL) and TSV approach that can provide the same die-to-die routing with smaller than $1-mu mathrm{m}$ line/space (L/S) and vertical connections as a Si interposer. The second option uses a multilayer RDL, which can be fabricated on Si, glass and even on the epoxy mold compound (EMC). The RDL can also provide vertical interconnects such as TSVs in Si. For demonstration, a test vehicle (TV) with one logic chip and two memory chips mounted on a multi-chip, fan-out interposer with an area approximately 1.5 times larger than the reticle was used. The interposer consists of two connect chips with $2-mu mathrm{m}$ L/S RDL and 6 mechanical IPDs located under the logic die. Two types of the connect chips were used - RDL on Si wafer and RDL on EMC having TMVs. The top die to interposer joints were made using $mu$-bumps with $25-mu mathrm{m}$ size on a $45-mu mathrm{m}$ pitch in the logic and $25-mu mathrm{m}$ size on a $55-mu mathrm{m}$ pitch in the memory die. Both the top and bottom sides of the fan-out interposer have a single layer of RDL. To interconnect the bottom side of the interposer and the package substrate, copper (Cu) pillar C4 bumps at $150-mu mathrm{m}$ pitch were formed. Once the top die and interposer assembly is complete, the subsequent processes are standard flip chip ball grid array (FCBGA) process flows. Moisture sensitivity and long-term reliability test results will be presented as well as warpage behavior, which is critical for the large body packages. Lastly, the advantages of the S-Connect package will be compared to other 2.5D and flip chip solutions in terms of manufacturability, ability to","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128371448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-01DOI: 10.1109/ECTC32696.2021.00107
Seokkan Ki, Jaehwan Shim, Seungtae Oh, Seunggeol Ryu, Jaechoon Kim, Y. Nam
Enhancing thermo-physical properties of thermal interface materials (TIMs) is important for efficient cooling of electronic devices. To eliminate air pockets between silicon (Si) die and copper (Cu) heat spreader/sink, TIMs can fill the voids at the interfaces and reduce the contact resistances. In recent, gallium (Ga)-based liquid metals (LMs) have drawn much attention due to their high thermal conductivity and maintained fluidity at room temperature. Previous works have tried to further increase the thermal conductivity by adding conductive fillers to Ga-based LM matrix; however, it is challenging to attain a solder-level thermal conductivity (>60 Wm−1K−1) while maintaining the fluidity. The fluidity gradually decreases due to the solid additives with high volume fraction (>10%) of fillers and significant oxidation, which is a critical issue for applying the LM TIMs to real-world application. To address the issues mentioned above, we incorporated Cu nano-fillers into the Ga-based matrix, excluding the oxidation issues. Through our suggested method, the fabricated LM composite shows over 64 Wm−1K−1 of thermal conductivity at only 4 vol% of copper nano-fillers. The fluidity can be maintained because of the low vol% of additives, which leads to wetting characteristics for the interface between Si and Cu substrate. The mechanism of thermal enhancement is demonstrated by the cluster visualization test, calculating a nanoparticle clustering model. Through the liquid-cooled test vehicle, the thermal performance of synthesized LM composites is assessed. Approximately 33% lower junction temperature is measured compared to the grease-type TIMs at high heat flux regime (>400 Wcm−2) with excellent thermal stability. In summary, this study not only provides a method for the fabrication of highperformance LM TIMs but also demonstrates the rapid enhancement in thermal conductivity for the thermal management of high-power electronics.
{"title":"Rapid Enhancement of Thermal Conductivity by Incorporating Oxide-Free Copper Nanoparticle Clusters for Highly Conductive Liquid Metal-based Thermal Interface Materials","authors":"Seokkan Ki, Jaehwan Shim, Seungtae Oh, Seunggeol Ryu, Jaechoon Kim, Y. Nam","doi":"10.1109/ECTC32696.2021.00107","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00107","url":null,"abstract":"Enhancing thermo-physical properties of thermal interface materials (TIMs) is important for efficient cooling of electronic devices. To eliminate air pockets between silicon (Si) die and copper (Cu) heat spreader/sink, TIMs can fill the voids at the interfaces and reduce the contact resistances. In recent, gallium (Ga)-based liquid metals (LMs) have drawn much attention due to their high thermal conductivity and maintained fluidity at room temperature. Previous works have tried to further increase the thermal conductivity by adding conductive fillers to Ga-based LM matrix; however, it is challenging to attain a solder-level thermal conductivity (>60 Wm−1K−1) while maintaining the fluidity. The fluidity gradually decreases due to the solid additives with high volume fraction (>10%) of fillers and significant oxidation, which is a critical issue for applying the LM TIMs to real-world application. To address the issues mentioned above, we incorporated Cu nano-fillers into the Ga-based matrix, excluding the oxidation issues. Through our suggested method, the fabricated LM composite shows over 64 Wm−1K−1 of thermal conductivity at only 4 vol% of copper nano-fillers. The fluidity can be maintained because of the low vol% of additives, which leads to wetting characteristics for the interface between Si and Cu substrate. The mechanism of thermal enhancement is demonstrated by the cluster visualization test, calculating a nanoparticle clustering model. Through the liquid-cooled test vehicle, the thermal performance of synthesized LM composites is assessed. Approximately 33% lower junction temperature is measured compared to the grease-type TIMs at high heat flux regime (>400 Wcm−2) with excellent thermal stability. In summary, this study not only provides a method for the fabrication of highperformance LM TIMs but also demonstrates the rapid enhancement in thermal conductivity for the thermal management of high-power electronics.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129472900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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