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2021 IEEE 71st Electronic Components and Technology Conference (ECTC)最新文献

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Performance Analysis of Self Heated Multilayer Vertical Graphene Nanoribbon Interconnects 自热多层垂直石墨烯纳米带互连的性能分析
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00256
B. Kumari, Rahul Kumar, Manodipan Sahoo, Rohit Sharma
In this paper, we report qualitative comparative signal integrity analysis of self-heated Ferric Chloride ($FeCl_{3}$) doped Top Contacted Multilayer Vertical Graphene Nanoribbon (TC-MLVGNR) interconnect and its comparison with copper and $FeCl_{3}$ doped Top Contacted Multilayer Horizontal Graphene Nanoribbon (TC-MLHGNR) interconnects. A coupled three-line interconnect system is utilized in this study. The dimensions of interconnects are taken as per the IRDS-2018 roadmap for 7nm technology node. In realistic scenario, roughness is present on interconnect surfaces and it plays a major role at lower technology nodes. Roughness is inevitable during the fabrication process. It helps to provide the adhesion between dielectric and interconnect. So to capture the realistic scenario, we are considering rough Multilayer Graphene Nanoribbon (MLGNR) interconnects to compare with conventional rough copper interconnects. When compared to rough copper, smooth copper and TC-MLHGNR interconnects, delay of TC-MLVGNR interconnect is reduced by 59%, 51% and 62%, respectively. Even if we consider self-heating, its performance is better than rough copper, smooth copper and TC-MLHGNR interconnects by 26%, 11% and 54%, respectively. It is worth noting that rough TC-MLHGNRs induce the highest delay especially when self-heating effect is considered. Also, this study proves that TC-MLVGNR interconnects outperform TC-MLHGNR interconnects in terms of thermal efficiency by 15% thus making it a potential interconnect candidate for ultra-scaled technology nodes.
在本文中,我们报道了自加热氯化铁($FeCl_{3}$)掺杂顶部接触多层垂直石墨烯纳米带(TC-MLVGNR)互连的定性比较信号完整性分析,并与铜和$FeCl_{3}$掺杂顶部接触多层水平石墨烯纳米带(TC-MLHGNR)互连进行了比较。本研究采用耦合三线互连系统。互连尺寸按照7纳米技术节点的IRDS-2018路线图。在现实情况下,粗糙度存在于互连表面,并且在较低的技术节点上起主要作用。在制造过程中,粗糙度是不可避免的。它有助于提供介电和互连之间的附着力。因此,为了捕捉现实场景,我们正在考虑粗糙的多层石墨烯纳米带(MLGNR)互连与传统的粗糙铜互连进行比较。与粗铜、光滑铜和TC-MLHGNR互连相比,TC-MLHGNR互连的延迟分别降低了59%、51%和62%。即使考虑自热,其性能也比粗铜、光滑铜和TC-MLHGNR互连分别好26%、11%和54%。值得注意的是,粗糙tc - mlhgnr产生的延迟最高,特别是考虑到自热效应时。此外,本研究证明TC-MLVGNR互连在热效率方面优于TC-MLHGNR互连15%,从而使其成为超大规模技术节点的潜在互连候选者。
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引用次数: 1
Case studies of accurate fault localization in advanced packages 先进封装中精确故障定位的案例研究
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00144
Sajay Bhuvanendran Nair Gourikutty, J. Alton, Desmond Yeo, Kok Keng Chua, Sharon Lim Seow Huang, S. Bhattacharya
Advanced wafer-level packaging has been successfully used in state-of-the-art FPGA ICs, smart-phone application processors, and GPU units to provide power-performance-form factor boosts that are not obtainable by conventional packaging. In addition, very fine pitch interconnects approaches such as high-density fan-out on organic substrates and fine pitch silicon interposers enable the need for heterogeneous integration and scaling demand. However, this increased the intricacy of package architecture which leads to a higher possibility of failures making it challenging to attain high yield in volume production. Therefore, high failure analysis success is required in this area and without accurate fault localization, failure analysis is difficult and often reliant on a best-guess approach which tends to be time-consuming and relatively expensive to be implemented. In this work, we demonstrated a rapid methodology for non-destructive accurate defect isolation at various levels of the advanced ICs preventing potential artifacts. First, fault isolation is verified on a 2.5D advanced package where an open fault is successfully localized after the micro-bump in the die side metal layer. Secondly, the methodology is validated by employing fine pitch interposer chip samples by isolating defects including high resistance fault in RDL metal lines.
先进的晶圆级封装已成功用于最先进的FPGA ic、智能手机应用处理器和GPU单元,以提供传统封装无法实现的功率性能提升。此外,非常细间距互连方法,如有机衬底上的高密度扇出和细间距硅中间层,可以满足异质集成和缩放需求。然而,这增加了封装架构的复杂性,导致更高的故障可能性,使其在批量生产中达到高成品率具有挑战性。因此,在这一领域需要高的故障分析成功率,如果没有准确的故障定位,故障分析是困难的,往往依赖于最佳猜测的方法,这往往是耗时和相对昂贵的实现。在这项工作中,我们展示了一种快速的方法,用于在不同级别的高级集成电路中进行非破坏性的精确缺陷隔离,以防止潜在的工件。首先,在2.5D先进封装上验证故障隔离,其中在模侧金属层的微碰撞后成功定位了开放故障。其次,采用细间距插片样品隔离RDL金属线中高阻故障等缺陷,验证了该方法的有效性。
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引用次数: 0
Flexible heterogeneously integrated low form factor wireless multi-channel surface electromyography (sEMG) device 柔性异质集成低尺寸无线多通道肌表面电图(sEMG)装置
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00245
A. Alam, M. Molter, A. Kapoor, B. Gaonkar, S. Benedict, L. Macyszyn, M. S. Joseph, S. Iyer
A elegant extremely flexible Fan-Out Wafer-Level Packaging (FOWLP) based fully integrated bipolar multi-channel (up to 12 channels) surface electromyography (sEMG) device and assembly is demonstrated for intraoperative neurological monitoring (IONM) for complex spine surgeries and post-op physiological monitoring. It includes twenty gold-capped vertically corrugated flexible dry copper electrodes, Bluetooth wireless data transfer, a multichannel sEMG data acquisition and processing dielet, rechargeable energy storage and an ergonomic reusable adhesive for ease of use. This completely biocompatible and wearable system is highly flexible, thin (1 mm), light weight (< 5 g) and can be used to monitor neuro-muscular activations for IONM as well as for general physiological monitoring.
一种基于完全集成的双极多通道(多达12通道)表面肌电图(sEMG)设备和组件,展示了用于复杂脊柱手术术中神经监测(IONM)和术后生理监测的优雅的极其灵活的扇形圆片级封装(FOWLP)。它包括20个金帽垂直波纹柔性干铜电极,蓝牙无线数据传输,多通道肌电信号数据采集和处理板,可充电能量存储和易于使用的符合人体工程学的可重复使用粘合剂。这种完全具有生物相容性和可穿戴性的系统高度灵活,薄(1毫米),重量轻(< 5克),可用于监测IONM的神经肌肉激活以及一般生理监测。
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引用次数: 0
The reliability of ENIG joint bonded by In-coated Cu sheet 涂层Cu板ENIG接头的可靠性研究
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00093
H. Nishikawa, Jianhao Wang, K. Kariya, N. Masago
To meet the increasing demand of the next-generation power conversion circuit on the high-power density, high operating temperature and miniaturization, many novel packaging methods have been investigation. Due to high remelting temperature and low cost transient liquid phase (TLP) bonding technology shows the great potential. In this paper, ENIG-finished Cu disks were bonded by In-coated Cu sheet through TLP bonding at 250°C and the shear test as well as fracture analysis during thermal aging was conducted. The bonded joint with the Cu2In, Au-In-Cu and Ni2In3IMC interface showed a strength of 19.85 MPa, although some defects could be observed. During thermal aging, the Cu2In and Ni2In3coarsened and the interface became more compact. It was very interesting that the shear strength of joint was increased by 81.21 after 1008 h thermal aging at 250°C. Although the fracture location was changed during thermal aging, the fracture surface always showed brittle characteristics.
为了满足下一代功率转换电路对高功率密度、高工作温度和小型化日益增长的要求,人们研究了许多新的封装方法。瞬态液相(TLP)键合技术由于重熔温度高、成本低而显示出巨大的发展潜力。本文采用In-coated Cu sheet在250℃下通过TLP焊接enigg -finished Cu disks,并进行了剪切试验和热时效过程中的断裂分析。与Cu2In、Au-In-Cu和Ni2In3IMC界面结合的接头强度为19.85 MPa,但存在一定缺陷。在热时效过程中,Cu2In和ni2in3晶粒变粗,界面变得更加致密。在250℃热时效1008 h后,接头的抗剪强度提高了81.21倍。在热时效过程中,虽然断口位置发生了变化,但断口表面始终呈现脆性特征。
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引用次数: 1
A Novel Photosensitive Polyimide Adhesive Material for Hybrid Bonding Processing 一种新型光敏聚酰亚胺杂化粘接材料
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00118
S. Yoneda, Kenya Adachi, K. Kobayashi, Daisaku Matsukawa, Mamoru Sasaki, T. Itabashi, Toshiaki Shirasaka, T. Shibata
Cu/insulating material hybrid bonding technology was a promising process for high performance three-dimensional integrated package. A novel polyimide (PI) and thermal compression bonding (TCB) process were proposed for chip to wafer hybrid bonding. The new PI was developed by re-designing key components of the formulation. It showed high adhesion after TCB and high reliability performance. For the PI to PI bonding process evaluation, there were not any visible voids after pre-bonding at 250-350 °C and after TCB at 300 °C. Cu/PI co-planarization process was confirmed, and the PI showed a practical removal rate even though the PI was cured at high temperature. Furthermore, the PI showed highly smooth surface after CMP.
铜/绝缘材料杂化键合技术是一种很有前途的高性能三维集成封装技术。提出了一种新的聚酰亚胺(PI)和热压缩键合(TCB)工艺用于芯片与晶圆的杂化键合。新的PI是通过重新设计配方的关键成分而开发的。TCB后附着力高,可靠性高。对于PI到PI键合过程的评价,250-350℃预键合和300℃TCB后没有任何可见的空洞。证实了Cu/PI共平面化过程,且PI在高温固化下仍具有实际的去除率。此外,CMP后的PI表面高度光滑。
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引用次数: 6
Heterogeneous Integration of Double Side SiP for IoT and 5G Application 面向物联网和5G应用的双向SiP异构集成
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00170
Mike Tsai, Ryan Chiu, Ming-fan Tsai, Eric He, Erico Yang, Tim Chang, Frank Chu, J. Chen
Double Side SiP is hot packaging solution by using double side SMT technology and dual side molding to shrink the overall module size. The calculation of package size can be reduce over 40% PCB placement area from 8 x 8mm to 6 x 6mm. Based on module level warpage and thermal dissipation performance point of view, the simulation and experiment including the molding process study with difference molding compound selection DOE to verify Double Side SiP warpage performance. The advantage of Double Side SiP, simplify PKG I/O Count (10% reduction based on PMIC of portable), to improve power supply efficiency and reduce noise emission. From electrical integration point of view, due to shorter signal transmission path to get good electrical performance (SI & PI) than other side by side flip chip base structure. From thermal performance, high thermal solution can be improved $mathrm{24}sim mathrm{38}%$. The Double Side SiP module can provide an advanced solution to address the module size, cost, performance, and time-to-market requirement for 5G and IoT marketing. The performance verification in this paper will proceed simulation and measurement. The reliability testing verification was including the TCT, HTSL and u-HAST (Temperature Cycle Test, High Temperature Storage Test, un-bias HAST) results as a verification for Double Side SiP structure. Finally, this paper have Double Side SiP structure and feasibility data for future 5G and IoT devices application.
双面SiP是采用双面SMT技术和双面成型来缩小整体模块尺寸的热封装解决方案。封装尺寸的计算可以减少40%以上的PCB放置面积从8 × 8mm到6 × 6mm。从模块级翘曲性能和散热性能的角度出发,通过仿真和实验,包括不同成型材料选择DOE的成型工艺研究,验证了双面SiP翘曲性能。双侧SiP优势,简化PKG I/O计数(在便携式PMIC基础上减少10%),提高电源效率,降低噪声排放。从电气集成的角度来看,由于信号传输路径较短,获得了较好的电气性能(SI & PI)比其他并排倒装芯片基架结构。从热学性能来看,高热溶液可以改善$ mathm {24}sim mathm{38}%$。双面SiP模块可以提供先进的解决方案,以满足5G和物联网营销对模块尺寸、成本、性能和上市时间的要求。本文的性能验证将进行仿真和测量。可靠性测试验证包括TCT、HTSL和u-HAST(温度循环测试、高温储存测试、无偏置HAST)结果作为对双面SiP结构的验证。最后,本文给出了双向SiP结构和未来5G和物联网设备应用的可行性数据。
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引用次数: 5
Monitoring of the Effect of Thermal Shock on Crack Growth in Copper Through-Glass Via Substrates 热冲击对铜玻璃通孔衬底裂纹扩展影响的监测
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00058
C. Okoro, S. Jayaraman, S. Pollard
This work aims at understanding thermo-mechanically induced cracks in through-glass via (TGV) made in Corning® HPFS® Fused Silica glass substrate, as well as to study the effect of thermal shock on the propagation of cracks. Two types of thermo-mechanically induced cracks were observed; radial cracks formed during heating and circumferential cracks that are formed during cooling. These cracks were initiated as a result of high tensile stresses in the circumferential and radial directions respectively. Thermal shock was found to lead to the growth of radial cracks. After 1000 cycles, catastrophic failures occurred due to the networking of radial cracks from adjacent vias. This suggests that TGV pitch dimension is a critical parameter that needs to be considered in order to limit catastrophic failures. On the other hand, no crack growth was observed for circumferential cracks in the in-plane direction, even after 1000 cycles of thermal shock. These results indicate that the prevention of radial and circumferential crack formation is the most critical step in mitigating risk of failure concerns, thus, the need for optimized crack-free metallized TGV solutions. Through TGV shape re-design, control of Cu metallization thickness as well as the use of lower annealing heating rate, these thermo-mechanically driven cracks were successfully mitigated in a previously reported work.
本工作旨在了解康宁®HPFS®熔融石英玻璃基板中玻璃通孔(TGV)的热机械诱导裂纹,并研究热冲击对裂纹扩展的影响。观察到两种类型的热致裂纹;加热时形成的径向裂纹和冷却时形成的周向裂纹。这些裂纹分别是由高周向和径向拉应力引起的。热冲击导致径向裂纹的扩展。经过1000次循环后,由于相邻过孔的径向裂纹联网而发生灾难性失效。这表明TGV节距尺寸是一个需要考虑的关键参数,以限制灾难性失效。另一方面,即使在1000次热冲击循环后,也没有观察到面内方向的周向裂纹扩展。这些结果表明,防止径向和周向裂纹的形成是降低失效风险的最关键步骤,因此,需要优化无裂纹金属化TGV解决方案。通过重新设计TGV形状、控制Cu金属化厚度以及采用较低的退火加热速率,这些热机械驱动的裂纹在先前的研究中得到了成功的缓解。
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引用次数: 2
Improved Damage Modeling for Solder Joints under Combined Vibration and Temperature Cycling Loading 振动和温度循环复合载荷下焊点损伤模型的改进
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00218
R. Höhne, K. Meier, A. Dasgupta, D. Leslie, K. Bock
In this work, fatigue damage caused to solder joints in printed wiring assemblies due to the superposition of harmonic vibration and temperature is studied along with different damage superposition approaches. In this work, a non-linear interactive damage superposition method is used, with temperature-dependent vibration damage coefficients that are interpolated from isothermal vibration experiments at selected temperatures. The temperature range −40°C to 125 °C was segmented into multiple sub-segments for this interpolation. By applying these measures, a new procedure for an improved incremental damage superposition approach (IDSA) was developed in this work. This new procedure was then used to superpose the vibration and temperature cycling loads to forecast the fatigue life of SAC105 solder joints for leadless chip resistors under simultaneous vibration and temperature cycling loads. Potential failure sites of the solder joint have been successfully investigated by utilizing this new procedure. Using the developed model, accelerated testing profiles are designed such that the vibration fatigue and temperature cycling fatigue damage are comparable and cause failure in approximately 250 temperature cycles.
本文采用不同的损伤叠加方法,研究了谐波振动和温度叠加对印刷线材焊点造成的疲劳损伤。在这项工作中,使用了一种非线性交互损伤叠加方法,该方法与温度相关的振动损伤系数是在选定温度下的等温振动实验中插值的。温度范围- 40°C至125°C被分割成多个子段进行插值。在此基础上,提出了一种改进的增量损伤叠加法(IDSA)。利用该方法对振动和温度循环载荷进行叠加,预测了无引线片式电阻SAC105焊点在振动和温度循环载荷作用下的疲劳寿命。利用这种新方法成功地研究了焊点的潜在失效部位。利用开发的模型,设计了加速测试剖面,使振动疲劳和温度循环疲劳损伤具有可比性,并且在大约250个温度循环中导致失效。
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引用次数: 5
S-Connect Fan-out Interposer For Next Gen Heterogeneous Integration 面向下一代异构集成的S-Connect扇出接口
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00027
JiHun Lee, Gamhan Yong, Minsu Jeong, JongHyun Jeon, Donghoon Han, MinKeon Lee, Wonchul Do, EunSook Sohn, M. Kelly, David Hiner, JinYoung Khim
Semiconductor products used in high-performance computing (HPC) and artificial intelligence (AI) applications require higher memory bandwidth, greater input/output (I/O) count, better power delivery network (PDN) performance and improved heat dissipation characteristics. To meet these requirements, a 2.5D package architecture with a Through Silicon Via (TSV)-bearing silicon (Si) interposer is mainly used in volume production. However, a redistribution layer (RDL) interposer is emerging as a cost effective and higher performance alternative. To implement an improved high-performance, multifunctional interposer, S-Connect technology has been developed that uses a multi-chip, fan-out interposer with various functionalities, such as a die-to-die (D2D) connection, where integrated passive devices (IPDs) and active devices can be integrated. If active devices are included in the interposer, S-Connect technology enables a 3D system where multiple active chips are vertically integrated. In this paper, the S-Connect design differences from the existing 2.5D package using Si interposer with TSVs and its fabrication process flow are explained. S-Connect technology provides manufacturing flexibility to apply various types of interconnects. Two different connect features will be discussed. Firstly, a Si connect will be explored having a back end of line (BEOL) and TSV approach that can provide the same die-to-die routing with smaller than $1-mu mathrm{m}$ line/space (L/S) and vertical connections as a Si interposer. The second option uses a multilayer RDL, which can be fabricated on Si, glass and even on the epoxy mold compound (EMC). The RDL can also provide vertical interconnects such as TSVs in Si. For demonstration, a test vehicle (TV) with one logic chip and two memory chips mounted on a multi-chip, fan-out interposer with an area approximately 1.5 times larger than the reticle was used. The interposer consists of two connect chips with $2-mu mathrm{m}$ L/S RDL and 6 mechanical IPDs located under the logic die. Two types of the connect chips were used - RDL on Si wafer and RDL on EMC having TMVs. The top die to interposer joints were made using $mu$-bumps with $25-mu mathrm{m}$ size on a $45-mu mathrm{m}$ pitch in the logic and $25-mu mathrm{m}$ size on a $55-mu mathrm{m}$ pitch in the memory die. Both the top and bottom sides of the fan-out interposer have a single layer of RDL. To interconnect the bottom side of the interposer and the package substrate, copper (Cu) pillar C4 bumps at $150-mu mathrm{m}$ pitch were formed. Once the top die and interposer assembly is complete, the subsequent processes are standard flip chip ball grid array (FCBGA) process flows. Moisture sensitivity and long-term reliability test results will be presented as well as warpage behavior, which is critical for the large body packages. Lastly, the advantages of the S-Connect package will be compared to other 2.5D and flip chip solutions in terms of manufacturability, ability to
用于高性能计算(HPC)和人工智能(AI)应用的半导体产品需要更高的内存带宽、更大的输入/输出(I/O)数量、更好的功率输送网络(PDN)性能和更好的散热特性。为了满足这些要求,在量产中主要采用带有通硅通孔(TSV)轴承硅(Si)中间层的2.5D封装架构。然而,重新分配层(RDL)中介器正在作为一种成本效益高、性能更高的替代方案出现。为了实现改进的高性能多功能中介器,S-Connect技术已经开发出来,该技术使用具有各种功能的多芯片扇形输出中介器,例如模对模(D2D)连接,其中集成的无源器件(ipd)和有源器件可以集成。如果在中介器中包含有源设备,则S-Connect技术可以实现多个有源芯片垂直集成的3D系统。本文阐述了S-Connect与现有采用Si介面与tsv的2.5D封装的设计差异及其制造工艺流程。S-Connect技术为应用各种类型的互连提供了制造灵活性。我们将讨论两种不同的连接特性。首先,将探索具有后端线(BEOL)和TSV方法的Si连接,该方法可以提供相同的模到模路由,其小于$1-mu mathm {m}$线/空间(L/S)和作为Si中间层的垂直连接。第二种选择使用多层RDL,可以在Si,玻璃甚至环氧模具化合物(EMC)上制造。RDL还可以提供垂直互连,如Si中的tsv。为了进行演示,使用了一辆测试车(TV),该测试车将一个逻辑芯片和两个存储芯片安装在一个多芯片上,扇形出的中间插孔面积约为十字线的1.5倍。该中间体由两个具有$2-mu mathm {m}$ L/S RDL的连接芯片和位于逻辑模下的6个机械ipd组成。采用两种类型的连接芯片:硅片上的RDL和具有tmv的EMC上的RDL。上模到中间模的连接使用$ $ mu$-凸块,其大小为$ $25-mu mathm {m}$,其大小为$45-mu mathm {m}$,其大小为$25-mu mathm {m}$,其大小为$55-mu mathm {m}$,其大小为$55-mu mathm {m}$。扇出中介器的顶部和底部都有一层RDL。为了将中间层底部与封装基板互连,形成了$150-mu mathm {m}$间距的铜(Cu)柱C4凸起。一旦上模和中间层组装完成,随后的工艺是标准的倒装芯片球网格阵列(FCBGA)工艺流程。湿气敏感性和长期可靠性测试结果,以及翘曲行为,这是大型车身包装的关键。最后,S-Connect封装的优势将在可制造性、集成多种功能的能力和成本方面与其他2.5D和倒装芯片解决方案进行比较。
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引用次数: 7
Rapid Enhancement of Thermal Conductivity by Incorporating Oxide-Free Copper Nanoparticle Clusters for Highly Conductive Liquid Metal-based Thermal Interface Materials 在高导电性液态金属基热界面材料中加入无氧化物铜纳米颗粒团簇的快速增强导热性
Pub Date : 2021-06-01 DOI: 10.1109/ECTC32696.2021.00107
Seokkan Ki, Jaehwan Shim, Seungtae Oh, Seunggeol Ryu, Jaechoon Kim, Y. Nam
Enhancing thermo-physical properties of thermal interface materials (TIMs) is important for efficient cooling of electronic devices. To eliminate air pockets between silicon (Si) die and copper (Cu) heat spreader/sink, TIMs can fill the voids at the interfaces and reduce the contact resistances. In recent, gallium (Ga)-based liquid metals (LMs) have drawn much attention due to their high thermal conductivity and maintained fluidity at room temperature. Previous works have tried to further increase the thermal conductivity by adding conductive fillers to Ga-based LM matrix; however, it is challenging to attain a solder-level thermal conductivity (>60 Wm−1K−1) while maintaining the fluidity. The fluidity gradually decreases due to the solid additives with high volume fraction (>10%) of fillers and significant oxidation, which is a critical issue for applying the LM TIMs to real-world application. To address the issues mentioned above, we incorporated Cu nano-fillers into the Ga-based matrix, excluding the oxidation issues. Through our suggested method, the fabricated LM composite shows over 64 Wm−1K−1 of thermal conductivity at only 4 vol% of copper nano-fillers. The fluidity can be maintained because of the low vol% of additives, which leads to wetting characteristics for the interface between Si and Cu substrate. The mechanism of thermal enhancement is demonstrated by the cluster visualization test, calculating a nanoparticle clustering model. Through the liquid-cooled test vehicle, the thermal performance of synthesized LM composites is assessed. Approximately 33% lower junction temperature is measured compared to the grease-type TIMs at high heat flux regime (>400 Wcm−2) with excellent thermal stability. In summary, this study not only provides a method for the fabrication of highperformance LM TIMs but also demonstrates the rapid enhancement in thermal conductivity for the thermal management of high-power electronics.
提高热界面材料(TIMs)的热物理性能对电子器件的高效冷却具有重要意义。为了消除硅(Si)芯片和铜(Cu)散热器/散热器之间的气穴,TIMs可以填充界面处的空隙并降低接触电阻。近年来,镓(Ga)基液态金属(LMs)因其高导热性和在室温下保持流动性而备受关注。以前的工作试图通过在ga基LM基体中添加导电填料来进一步提高导热性;然而,在保持流动性的同时实现焊料级导热系数(bbb60 Wm−1K−1)是具有挑战性的。由于填料体积分数高(bbb10 %)的固体添加剂和明显的氧化,流动性逐渐降低,这是将LM TIMs应用于实际应用的关键问题。为了解决上述问题,我们将Cu纳米填料加入到ga基基体中,排除了氧化问题。通过我们提出的方法,制备的LM复合材料在铜纳米填料含量仅为4 vol%时的导热系数超过64 Wm−1K−1。由于添加剂的体积百分比较低,因此可以保持流动性,这导致Si和Cu衬底之间的界面具有润湿特性。通过聚类可视化实验,计算纳米颗粒聚类模型,论证了热增强的机理。通过液冷试验车,对合成LM复合材料的热性能进行了评价。在高热流密度下(>400 Wcm−2),与润滑脂型TIMs相比,结温降低了约33%,具有优异的热稳定性。综上所述,本研究不仅为高性能LM TIMs的制造提供了一种方法,而且还展示了高功率电子产品热管理的热导率的快速提高。
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引用次数: 2
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2021 IEEE 71st Electronic Components and Technology Conference (ECTC)
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