J. Lau, C. Ko, C. Peng, Kai-Ming Yang, T. Xia, P. Lin, Jean-Jou Chen, Po-Chun Huang, Tzvy-Jang Tseng, E. Lin, Leo Chang, Curry Lin, Yan-Jun Fan, H. Liu, Winnie Lu
In this study, the reliability of the solder joints of a heterogeneous integration of one large chip (10 × 10 mm) and two smaller chips (7 × 5 mm) by a fan-out method with a redistribution layer-first substrate fabricated on a 515 × 510-mm panel is investigated. Emphasis is placed on the thermal cycling test (−55°C Δ 125°C, 50-min cycle) of the heterogeneous integration package on a printed circuit board (PCB). The thermal cycling test results are plotted into a Weibull distribution. The Weibull slope and characteristic life at median rank are presented. At 90% confidence, the true Weibull slope and the true 10% life interval are also provided. A linear acceleration factor is adopted to map the solder joint reliability at the test condition to the solder joint reliability at an operating condition. The failure location and failure mode of the PCB assembly of the heterogeneous integration package are provided and discussed. A nonlinear, time- and temperature-dependent 3-D finite element simulation is performed for the heterogeneous integration PCB assembly and correlated with the thermal cycling test results.
{"title":"Thermal Cycling Test and Simulation of Fan-Out Chip-Last Panel-Level Packaging for Heterogeneous Integration","authors":"J. Lau, C. Ko, C. Peng, Kai-Ming Yang, T. Xia, P. Lin, Jean-Jou Chen, Po-Chun Huang, Tzvy-Jang Tseng, E. Lin, Leo Chang, Curry Lin, Yan-Jun Fan, H. Liu, Winnie Lu","doi":"10.4071/imaps.1419800","DOIUrl":"https://doi.org/10.4071/imaps.1419800","url":null,"abstract":"\u0000 In this study, the reliability of the solder joints of a heterogeneous integration of one large chip (10 × 10 mm) and two smaller chips (7 × 5 mm) by a fan-out method with a redistribution layer-first substrate fabricated on a 515 × 510-mm panel is investigated. Emphasis is placed on the thermal cycling test (−55°C Δ 125°C, 50-min cycle) of the heterogeneous integration package on a printed circuit board (PCB). The thermal cycling test results are plotted into a Weibull distribution. The Weibull slope and characteristic life at median rank are presented. At 90% confidence, the true Weibull slope and the true 10% life interval are also provided. A linear acceleration factor is adopted to map the solder joint reliability at the test condition to the solder joint reliability at an operating condition. The failure location and failure mode of the PCB assembly of the heterogeneous integration package are provided and discussed. A nonlinear, time- and temperature-dependent 3-D finite element simulation is performed for the heterogeneous integration PCB assembly and correlated with the thermal cycling test results.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49002094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Lau, C. Ko, C. Peng, Tzvy-Jang Tseng, Kai-Ming Yang, T. Xia, P. Lin, E. Lin, Leo Chang, H. Liu, Curry Lin, Yan-Jun Fan, D. Cheng, Winnie Lu
In this study, the reliability of the solder joints of a six-side molded panel-level chip-scale package (PLCSP) is investigated. Emphasis is placed on the thermal cycling test (−55°C Δ 125°C, 50-min cycle) of the six-side molded PLCSP on a printed circuit board. For comparison purpose, the one without six-side molded (ordinary) PLCSP is also subjected to the same test. The thermal cycling test results are plotted into a Weibull distribution, and the true Weibull slope and true characteristic life at 90% confidence are presented. The solder joint mean life ratio of these two cases and its confidence level are also determined. Furthermore, their solder joint failure location and failure mode are provided. Finally, a nonlinear, time- and temperature-dependent 3-D finite element simulation is performed for these two cases and correlated with the thermal cycling test results.
{"title":"Thermal Cycling Test and Simulation of Six-Side Molded Panel-Level Chip-Scale Packages (PLCSPs)","authors":"J. Lau, C. Ko, C. Peng, Tzvy-Jang Tseng, Kai-Ming Yang, T. Xia, P. Lin, E. Lin, Leo Chang, H. Liu, Curry Lin, Yan-Jun Fan, D. Cheng, Winnie Lu","doi":"10.4071/imaps.1421341","DOIUrl":"https://doi.org/10.4071/imaps.1421341","url":null,"abstract":"\u0000 In this study, the reliability of the solder joints of a six-side molded panel-level chip-scale package (PLCSP) is investigated. Emphasis is placed on the thermal cycling test (−55°C Δ 125°C, 50-min cycle) of the six-side molded PLCSP on a printed circuit board. For comparison purpose, the one without six-side molded (ordinary) PLCSP is also subjected to the same test. The thermal cycling test results are plotted into a Weibull distribution, and the true Weibull slope and true characteristic life at 90% confidence are presented. The solder joint mean life ratio of these two cases and its confidence level are also determined. Furthermore, their solder joint failure location and failure mode are provided. Finally, a nonlinear, time- and temperature-dependent 3-D finite element simulation is performed for these two cases and correlated with the thermal cycling test results.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45926674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, we give an overview of the development of an asymmetric optical bus coupler (AOBC) from the theoretical basis, the optical continuous wave, and bit rate performance to the implementation in a 3-D-Opto-MID package. The coupler allows for an interruption-free and bidirectional connection between two multimode waveguides, with different coupling ratios at the same node up to an aspect ratio of 5:1 depending on the coupling direction. For the first time, data transmission up to 12.5 Gbit/s is demonstrated with the AOBC, as well as the full implementation of the coupling element into a 3-D-Opto-MID package including an electrical test circuit.
{"title":"Multimode Bus Coupler for Device Communication Integrated in 3D-Opto-MID","authors":"L. Lorenz, K. Nieweglowski, K. Bock","doi":"10.4071/imaps.1412062","DOIUrl":"https://doi.org/10.4071/imaps.1412062","url":null,"abstract":"\u0000 In this article, we give an overview of the development of an asymmetric optical bus coupler (AOBC) from the theoretical basis, the optical continuous wave, and bit rate performance to the implementation in a 3-D-Opto-MID package. The coupler allows for an interruption-free and bidirectional connection between two multimode waveguides, with different coupling ratios at the same node up to an aspect ratio of 5:1 depending on the coupling direction. For the first time, data transmission up to 12.5 Gbit/s is demonstrated with the AOBC, as well as the full implementation of the coupling element into a 3-D-Opto-MID package including an electrical test circuit.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45406079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Bernhard, S. Zarwell, R. Massey, E. Steinhäuser, S. Kempa, Frank Branduuml
The effect of the Cu target pad roughness on the growth mode of electroless Cu from two different Cu baths was investigated, with bath A having a cyanide based, and bath B, a non-cyanide-based stabilizer system. Both baths are commonly used within the PCB industry. In the case of bath B, for an average target pad roughness higher than Ra = 300 nm, two growth modes are observed. The first mode is a copying of the subjacent Cu substrate morphology, whereas the second forms spherical grains (Cu-nodules) predominantly at the exposed sites of the substrate crystals. These Cu nodules typically have a radius comparable to that of the plated electroless Cu thickness and contain a high density of nanovoids toward their base. The related void formation seems relevant to weaken the overall Cu/Cu/Cu interconnection in the blind microvia. Interestingly, the tendency to form nodules with increasing Cu base roughness is widely suppressed for the cyanide-based bath A, where the deposit is nodule free up to a target pad roughness of approximately Ra=1,000 nm. When solution delivery and exchange were investigated, it is apparent that a low exchange rate has a negative impact on the electroless Cu deposition, and results with undesirable nodules and voids, even if the surface roughness values would suggest otherwise, could be expected.
{"title":"The Effect of Cu Target Pad Roughness and Solution Flow on the Growth Mode and Void Formation in Electroless Cu Films","authors":"T. Bernhard, S. Zarwell, R. Massey, E. Steinhäuser, S. Kempa, Frank Branduuml","doi":"10.4071/imaps.1409209","DOIUrl":"https://doi.org/10.4071/imaps.1409209","url":null,"abstract":"\u0000 The effect of the Cu target pad roughness on the growth mode of electroless Cu from two different Cu baths was investigated, with bath A having a cyanide based, and bath B, a non-cyanide-based stabilizer system. Both baths are commonly used within the PCB industry. In the case of bath B, for an average target pad roughness higher than Ra = 300 nm, two growth modes are observed. The first mode is a copying of the subjacent Cu substrate morphology, whereas the second forms spherical grains (Cu-nodules) predominantly at the exposed sites of the substrate crystals. These Cu nodules typically have a radius comparable to that of the plated electroless Cu thickness and contain a high density of nanovoids toward their base. The related void formation seems relevant to weaken the overall Cu/Cu/Cu interconnection in the blind microvia. Interestingly, the tendency to form nodules with increasing Cu base roughness is widely suppressed for the cyanide-based bath A, where the deposit is nodule free up to a target pad roughness of approximately Ra=1,000 nm. When solution delivery and exchange were investigated, it is apparent that a low exchange rate has a negative impact on the electroless Cu deposition, and results with undesirable nodules and voids, even if the surface roughness values would suggest otherwise, could be expected.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42268842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the power semiconductor industry, there is continuous development toward higher maximum current capability of devices while device dimensions shrink. This leads to an increase in current density which the devices have to handle, and raises the question if electromigration (EM) is a critical issue here. Generally, an EM failure can be described by the Black’s equation with temperature and current density as the main influencing factors. Normally, the current that the power packages need to handle lies in the range of 100 A. However, it should be noted that power devices exhibit asymmetric sizes of drain and source contacts. This may lead to higher current density at the source leads (area ratio drain/source: ~9× for PQFN 5 × 6). Nevertheless, the source lead area is still much larger than that of the flip chip bumps (i.e., 28 times larger than a 100-μm microbump). This typically enhances the safety of the power device with respect to EM. However, with regard to future development toward higher maximum current capability, we intended to investigate further on the EM of power devices. In the present work, we focused on the PQFN 5 × 6 package to study the EM behavior of a power device soldered on a printed circuit board (PCB). We employed the highest current (120 A) and temperature (150°C) that the stress test system could handle to study EM in accelerated mode. First fails occurred after ~1,200 h, which was much earlier than expected from previous flip-chip investigations. In addition, we found separation gaps in the solder joint between drain contact and PCB, which experienced the lowest current density in the whole test. Contradictorily, we observed only minor solder degradation at the source interface, regardless of the higher current density there. Nevertheless, the separating metal interfaces still correlated well with the current direction. Thermal simulations revealed that due to the self-heating of the device by the high current applied, both the drain and source leads were exposed to much higher temperatures (Tmax = 168°C) than the PCB board which was kept under temperature control at 150°C. This temperature difference resulted in a thermal gradient between the device and PCB, which, in turn, triggered thermal migration (TM) in addition to EM. As TM for the drain contact occurred in the same direction as EM, it enhanced the degradation effect and therefore led to a shorter time-to-failure at the drain. In contrast to this, such an enhanced effect did not occur at the source side. As a result, we observed higher solder degradation at the drain side, which we did confirm by switching the current direction in the test. To minimize the TM effect, a special EM test vehicle, which used a Cu plate instead of the metal-oxide-semiconductor field-effect transistor chip, was designed and fabricated. Thermal simulation verified that the device operated at similar temperatures as the PCB board. Using this setup, it was possible to study EM in an acce
{"title":"Electromigration in Power Devices: A Combined Effect of Electromigration and Thermal Migration","authors":"H. Zhuang, R. Bauer, M. Dinkel","doi":"10.4071/IMAPS.1377365","DOIUrl":"https://doi.org/10.4071/IMAPS.1377365","url":null,"abstract":"In the power semiconductor industry, there is continuous development toward higher maximum current capability of devices while device dimensions shrink. This leads to an increase in current density which the devices have to handle, and raises the question if electromigration (EM) is a critical issue here. Generally, an EM failure can be described by the Black’s equation with temperature and current density as the main influencing factors. Normally, the current that the power packages need to handle lies in the range of 100 A. However, it should be noted that power devices exhibit asymmetric sizes of drain and source contacts. This may lead to higher current density at the source leads (area ratio drain/source: ~9× for PQFN 5 × 6). Nevertheless, the source lead area is still much larger than that of the flip chip bumps (i.e., 28 times larger than a 100-μm microbump). This typically enhances the safety of the power device with respect to EM. However, with regard to future development toward higher maximum current capability, we intended to investigate further on the EM of power devices. In the present work, we focused on the PQFN 5 × 6 package to study the EM behavior of a power device soldered on a printed circuit board (PCB). We employed the highest current (120 A) and temperature (150°C) that the stress test system could handle to study EM in accelerated mode. First fails occurred after ~1,200 h, which was much earlier than expected from previous flip-chip investigations. In addition, we found separation gaps in the solder joint between drain contact and PCB, which experienced the lowest current density in the whole test. Contradictorily, we observed only minor solder degradation at the source interface, regardless of the higher current density there. Nevertheless, the separating metal interfaces still correlated well with the current direction. Thermal simulations revealed that due to the self-heating of the device by the high current applied, both the drain and source leads were exposed to much higher temperatures (Tmax = 168°C) than the PCB board which was kept under temperature control at 150°C. This temperature difference resulted in a thermal gradient between the device and PCB, which, in turn, triggered thermal migration (TM) in addition to EM. As TM for the drain contact occurred in the same direction as EM, it enhanced the degradation effect and therefore led to a shorter time-to-failure at the drain. In contrast to this, such an enhanced effect did not occur at the source side. As a result, we observed higher solder degradation at the drain side, which we did confirm by switching the current direction in the test. To minimize the TM effect, a special EM test vehicle, which used a Cu plate instead of the metal-oxide-semiconductor field-effect transistor chip, was designed and fabricated. Thermal simulation verified that the device operated at similar temperatures as the PCB board. Using this setup, it was possible to study EM in an acce","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"18 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70525912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abel Misrak, Tushar Chauhan, Rabin Bhandari, A. Chowdhury, A. Lakshminarayana, F. Mirza, B. G. Bazehhour, M. Vujosevic, D. Agonafer
Computational modeling is often leveraged to design and optimize electronic packages for both performance and reliability purposes. One of the factors that affect the accuracy of computational models is the accuracy of the material properties. Microelectromechanical system sensors, in particular, are usually extremely sensitive to slightest material property changes in the package. Therefore, even small measurement variations in material characterization due to different sample preparation methods or different testing techniques can impact accuracy of computational models that are leveraged for designing or analyzing sensor performance. The challenge in material characterization is even greater for materials that require curing. Die attach polymers, for example, have strict curing profile requirements that are used during the manufacturing process. Such curing conditions are usually hard to duplicate in laboratories, and the samples used for material characterization may not necessarily be representative of the actual component in the final product. In this study, the effect of parameters such as temperature curing profile, application of pressure during curing, and sample preparation technique on temperature-dependent thermomechanical properties of two types of die attach elastomers is investigated. The mechanical properties, including the elastic modulus (E), coefficient of thermal expansion, and glass transition temperature of the die attach material, are measured using a suite of techniques such as dynamic mechanical analysis and thermomechanical analysis. The analysis is performed for a wide temperature range corresponding to typical sensor applications. It is shown that sample preparation and characterization techniques have a considerable impact on the measurements, which results in different MEMS sensor performance predictions through computational modeling.
{"title":"Impact of Die Attach Sample Preparation on Its Measured Mechanical Properties for MEMS Sensor Applications","authors":"Abel Misrak, Tushar Chauhan, Rabin Bhandari, A. Chowdhury, A. Lakshminarayana, F. Mirza, B. G. Bazehhour, M. Vujosevic, D. Agonafer","doi":"10.4071/IMAPS.1234982","DOIUrl":"https://doi.org/10.4071/IMAPS.1234982","url":null,"abstract":"Computational modeling is often leveraged to design and optimize electronic packages for both performance and reliability purposes. One of the factors that affect the accuracy of computational models is the accuracy of the material properties. Microelectromechanical system sensors, in particular, are usually extremely sensitive to slightest material property changes in the package. Therefore, even small measurement variations in material characterization due to different sample preparation methods or different testing techniques can impact accuracy of computational models that are leveraged for designing or analyzing sensor performance. The challenge in material characterization is even greater for materials that require curing. Die attach polymers, for example, have strict curing profile requirements that are used during the manufacturing process. Such curing conditions are usually hard to duplicate in laboratories, and the samples used for material characterization may not necessarily be representative of the actual component in the final product. In this study, the effect of parameters such as temperature curing profile, application of pressure during curing, and sample preparation technique on temperature-dependent thermomechanical properties of two types of die attach elastomers is investigated. The mechanical properties, including the elastic modulus (E), coefficient of thermal expansion, and glass transition temperature of the die attach material, are measured using a suite of techniques such as dynamic mechanical analysis and thermomechanical analysis. The analysis is performed for a wide temperature range corresponding to typical sensor applications. It is shown that sample preparation and characterization techniques have a considerable impact on the measurements, which results in different MEMS sensor performance predictions through computational modeling.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"65 1","pages":"21-28"},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70525677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Capuz, M. Lofrano, C. Gerets, F. Duval, P. Bex, J. Derakhshandeh, K. Vanstreels, A. Phommahaxay, E. Beyne, Andy Miller
For die-to-wafer (D2W) stacking of high-density interconnects and fine-pitch microbumps, underfill serves to fill the spaces in-between microbumps for protection and reliability. Among the different types of underfill, nonconductive film (NCF) has the advantages of fillet and volume control. However, one of the challenges is the solder joint wetting. An NCF must have good embedded-flux activation to mitigate Cu UBM pad oxidation due to the repeated TCB cycles that accelerate oxidation on neighboring dice. The flux in the NCF also helps in wetting the solder bumps. To realize efficient solder wetting, one must also understand the NCF deformation quality, which is a function of its viscosity. This parameter has direct impact on the deformation of solder bumps. High-viscosity NCF would be difficult to deform, thus preventing solder contact to pad during TCB reflow temperature. High bond force is required and could lead to reduced alignment accuracy. For a low viscous NCF, it requires low bond force. Solder joint wetting is a challenge with excessive squeezeout due to fast and instantaneous deformation. We seek to demonstrate in this article a creative methodology for NCF material characterization, considering the factors of NCF viscosity, deformation, and solder squeezeout. We use TCB tool position-tracking data to define the deformation curve of the NCF as a function of temperature and time at very fast profile of TCB. We use the NCF viscosity curve as reference in relation to the actual deformation, and predict dynamic deformation in three different configurations. Deformation test configurations were performed on chips with and without microbumps bonded with a rigid flat glass surface and with a bottom Cu UBM pad. The experiments were performed with different heating ramp rates at target above Sn reflow of ~250°C interface temperature. As validation, we applied the optimized TCB process (force, temperature, and ramp rate) on a test vehicle with 20 and 40 μm pitch daisy chains and obtained very good connectivity with good joint and IMC formation.
{"title":"A Novel Method for Characterization of Ultralow Viscosity NCF Layers Using TCB for 3D Assembly","authors":"G. Capuz, M. Lofrano, C. Gerets, F. Duval, P. Bex, J. Derakhshandeh, K. Vanstreels, A. Phommahaxay, E. Beyne, Andy Miller","doi":"10.4071/imaps.1391366","DOIUrl":"https://doi.org/10.4071/imaps.1391366","url":null,"abstract":"\u0000 For die-to-wafer (D2W) stacking of high-density interconnects and fine-pitch microbumps, underfill serves to fill the spaces in-between microbumps for protection and reliability. Among the different types of underfill, nonconductive film (NCF) has the advantages of fillet and volume control. However, one of the challenges is the solder joint wetting. An NCF must have good embedded-flux activation to mitigate Cu UBM pad oxidation due to the repeated TCB cycles that accelerate oxidation on neighboring dice. The flux in the NCF also helps in wetting the solder bumps. To realize efficient solder wetting, one must also understand the NCF deformation quality, which is a function of its viscosity. This parameter has direct impact on the deformation of solder bumps. High-viscosity NCF would be difficult to deform, thus preventing solder contact to pad during TCB reflow temperature. High bond force is required and could lead to reduced alignment accuracy. For a low viscous NCF, it requires low bond force. Solder joint wetting is a challenge with excessive squeezeout due to fast and instantaneous deformation. We seek to demonstrate in this article a creative methodology for NCF material characterization, considering the factors of NCF viscosity, deformation, and solder squeezeout. We use TCB tool position-tracking data to define the deformation curve of the NCF as a function of temperature and time at very fast profile of TCB. We use the NCF viscosity curve as reference in relation to the actual deformation, and predict dynamic deformation in three different configurations. Deformation test configurations were performed on chips with and without microbumps bonded with a rigid flat glass surface and with a bottom Cu UBM pad. The experiments were performed with different heating ramp rates at target above Sn reflow of ~250°C interface temperature. As validation, we applied the optimized TCB process (force, temperature, and ramp rate) on a test vehicle with 20 and 40 μm pitch daisy chains and obtained very good connectivity with good joint and IMC formation.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47158770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The evolution of internet-enabled mobile devices has driven innovation in the manufacturing and design of technology capable of high-frequency electronic signal transfer. Among the primary factors affecting the integrity of high-frequency signals is the surface finish applied on PCB copper pads – a need commonly met through the electroless nickel immersion gold process, ENIG. However, there are well-documented limitations of ENIG due to the presence of nickel, the properties of which result in an overall reduced performance in high-frequency data transfer rate for ENIG-applied electronics, compared to bare copper. An innovation over traditional ENIG is a nickel-less approach involving a special nano-engineered barrier designed to coat copper contacts, finished with an outermost gold layer. In this paper, assemblies involving this nickel-less novel surface finish have been subjected to extended thermal exposure, then intermetallics analyses, contact/sheet resistance comparison after every reflow cycle (up to 6 reflow cycles) to assess the prevention of copper atom diffusion into the gold layer, solder ball pull and shear tests to evaluate the aging and long-term reliability of solder joints, and insertion loss testing to gauge whether this surface finish can be used for high-frequency, high density interconnect (HDI) applications.
{"title":"Reliable Nickel-Free Surface Finish Solution for High-Frequency, HDI PCB Applications","authors":"K. Shah","doi":"10.4071/imaps.1227802","DOIUrl":"https://doi.org/10.4071/imaps.1227802","url":null,"abstract":"The evolution of internet-enabled mobile devices has driven innovation in the manufacturing and design of technology capable of high-frequency electronic signal transfer. Among the primary factors affecting the integrity of high-frequency signals is the surface finish applied on PCB copper pads – a need commonly met through the electroless nickel immersion gold process, ENIG. However, there are well-documented limitations of ENIG due to the presence of nickel, the properties of which result in an overall reduced performance in high-frequency data transfer rate for ENIG-applied electronics, compared to bare copper. An innovation over traditional ENIG is a nickel-less approach involving a special nano-engineered barrier designed to coat copper contacts, finished with an outermost gold layer. In this paper, assemblies involving this nickel-less novel surface finish have been subjected to extended thermal exposure, then intermetallics analyses, contact/sheet resistance comparison after every reflow cycle (up to 6 reflow cycles) to assess the prevention of copper atom diffusion into the gold layer, solder ball pull and shear tests to evaluate the aging and long-term reliability of solder joints, and insertion loss testing to gauge whether this surface finish can be used for high-frequency, high density interconnect (HDI) applications.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"17 1","pages":"121-127"},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43539639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Juhee Lee, Kyeong-Min Kim, Simon Kim, Kiseop Kim, Kyungsoo Lee
The importance of signal integrity is emphasized as signal speed increases, and higher frequencies are applied. The PCB manufacturer uses SI coupons that can replace the in-product circuit to measure and calculate the signal loss. In this study, we tried to minimize the discontinuous path of Delta-L coupon by using the VIPPO (Via In Pad Plated Over) technique to improve the signal integrity. We compared the VIPPO-applied design that has minimal discontinuity with the conventional Delta-L design. In order to minimize discontinuity, circuits connected to pads and via holes were removed from the outer layer, and the pads were designed directly above the via holes. First of all, we simulated the optimized design that eliminated discontinuities using Signal Integrity Software, Simbeor. Second, we measured and verified DeltaL by using Introbotix's Accu-prober program. In the future, higher measurement frequencies will further increase signal loss due to unnecessary pathways and discrete signals, therefore minimizing the effects of discontinuity will be an important issue, and using the VIPPO technique will help to improve signal integrity. Introduction In order to increase the speed of the signal, high frequency is applied, which emphasizes the importance of signal integrity. Many methods have been introduced to prevent noise and loss of signals such as low dielectric constant materials or low roughness surfaces. However, there are inherent components in the PCB structure that interfere with the signal quality, and how to remove them is also important. The Via-In-Pad Plated Over (VIPPO) structure has been adopted in many BGA footprint designs within the PCB. These VIPPO structures are preferred over the more traditional dogbone pad structure in order to shrink signal path lengths, reducing two parasitic effects, capacitance and inductance, for improved high-speed performance. The signal traces, which connect the BGA pads with the vias, act as inductors. Additionally, as high-speed designs typically have ground planes immediately below the outer layer, there is also a capacitive effect that is generated. With the VIPPO structure, the outer trace layer is eliminated, thereby cancelling both parasitic effects. In the PCB manufacturing process, a coupon for measuring signal loss is inserted outside and analyzed as one way to verify the characteristics of the signal. Coupons are methods for verifying on behalf of the actual products and it is important to make them as identical as possible to the product. Developed by Intel, the Delta-L coupon measures a long, short circuit and calculates the tow differences to extract the loss. The greatest feature of Delta-L is a simplified deembedding methodology to accurately measure stripline loss by using two test structures, long and short stripline traces, to remove unwanted effect, such as vias. The condition algorithm can eliminate the loss value variation induced by the multi-reflections between these impedance m
{"title":"Optimization of PCB SI Coupon Design That Minimizes Discontinuity Through via-in-Pad Plated over (VIPPO) Technique","authors":"Juhee Lee, Kyeong-Min Kim, Simon Kim, Kiseop Kim, Kyungsoo Lee","doi":"10.4071/imaps.1227889","DOIUrl":"https://doi.org/10.4071/imaps.1227889","url":null,"abstract":"The importance of signal integrity is emphasized as signal speed increases, and higher frequencies are applied. The PCB manufacturer uses SI coupons that can replace the in-product circuit to measure and calculate the signal loss. In this study, we tried to minimize the discontinuous path of Delta-L coupon by using the VIPPO (Via In Pad Plated Over) technique to improve the signal integrity. We compared the VIPPO-applied design that has minimal discontinuity with the conventional Delta-L design. In order to minimize discontinuity, circuits connected to pads and via holes were removed from the outer layer, and the pads were designed directly above the via holes. First of all, we simulated the optimized design that eliminated discontinuities using Signal Integrity Software, Simbeor. Second, we measured and verified DeltaL by using Introbotix's Accu-prober program. In the future, higher measurement frequencies will further increase signal loss due to unnecessary pathways and discrete signals, therefore minimizing the effects of discontinuity will be an important issue, and using the VIPPO technique will help to improve signal integrity. Introduction In order to increase the speed of the signal, high frequency is applied, which emphasizes the importance of signal integrity. Many methods have been introduced to prevent noise and loss of signals such as low dielectric constant materials or low roughness surfaces. However, there are inherent components in the PCB structure that interfere with the signal quality, and how to remove them is also important. The Via-In-Pad Plated Over (VIPPO) structure has been adopted in many BGA footprint designs within the PCB. These VIPPO structures are preferred over the more traditional dogbone pad structure in order to shrink signal path lengths, reducing two parasitic effects, capacitance and inductance, for improved high-speed performance. The signal traces, which connect the BGA pads with the vias, act as inductors. Additionally, as high-speed designs typically have ground planes immediately below the outer layer, there is also a capacitive effect that is generated. With the VIPPO structure, the outer trace layer is eliminated, thereby cancelling both parasitic effects. In the PCB manufacturing process, a coupon for measuring signal loss is inserted outside and analyzed as one way to verify the characteristics of the signal. Coupons are methods for verifying on behalf of the actual products and it is important to make them as identical as possible to the product. Developed by Intel, the Delta-L coupon measures a long, short circuit and calculates the tow differences to extract the loss. The greatest feature of Delta-L is a simplified deembedding methodology to accurately measure stripline loss by using two test structures, long and short stripline traces, to remove unwanted effect, such as vias. The condition algorithm can eliminate the loss value variation induced by the multi-reflections between these impedance m","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"17 1","pages":"128-137"},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47849267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Lau, C. Ko, Tzvy-Jang Tseng, C. Peng, Kai-Ming Yang, T. Xia, P. Lin, E. Lin, Leo Chang, H. Liu, Curry Lin, D. Cheng, Winnie Lu
In this study, the design, materials, process, assembly, and reliability of a six-side molded panel-level chip-scale package (PLCSP) are presented. Emphasis is placed on the fabrication of the redistribution layers (RDLs) of the PLCSP on a large temporary panel with multiple device wafers. Because all the printed circuited board (PCB) panels are in rectangular shape, some of the device wafers are diced into two or more pieces so the panel is fully utilized. Thus, it is very high throughput. Because all the processes/equipment are PCB processes/equipment (not semiconductor process/equipment), it is a very low-cost process. After the fabrication of RDLs, the wafers from the PCB panel were debonded. It is followed by solder ball mounting and fabricating the six-side molded PLCSP from the original device wafers with RDLs. The drop test and the results including failure analysis of the PLCSP are presented. Thermal cycling of the six-side molded PLCSP PCB assembly is performed by a nonlinear temperature- and time-dependent finite-element simulation.
{"title":"Six-Side Molded Panel-Level Chip-Scale Package with Multiple Diced Wafers","authors":"J. Lau, C. Ko, Tzvy-Jang Tseng, C. Peng, Kai-Ming Yang, T. Xia, P. Lin, E. Lin, Leo Chang, H. Liu, Curry Lin, D. Cheng, Winnie Lu","doi":"10.4071/imaps.1226533","DOIUrl":"https://doi.org/10.4071/imaps.1226533","url":null,"abstract":"\u0000 In this study, the design, materials, process, assembly, and reliability of a six-side molded panel-level chip-scale package (PLCSP) are presented. Emphasis is placed on the fabrication of the redistribution layers (RDLs) of the PLCSP on a large temporary panel with multiple device wafers. Because all the printed circuited board (PCB) panels are in rectangular shape, some of the device wafers are diced into two or more pieces so the panel is fully utilized. Thus, it is very high throughput. Because all the processes/equipment are PCB processes/equipment (not semiconductor process/equipment), it is a very low-cost process. After the fabrication of RDLs, the wafers from the PCB panel were debonded. It is followed by solder ball mounting and fabricating the six-side molded PLCSP from the original device wafers with RDLs. The drop test and the results including failure analysis of the PLCSP are presented. Thermal cycling of the six-side molded PLCSP PCB assembly is performed by a nonlinear temperature- and time-dependent finite-element simulation.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44107756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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