Pub Date : 2019-10-01DOI: 10.4071/2380-4505-2019.1.000312
Maciej Patelka, Shosuke Ikeda, K. Sasaki, Hiroki Myodo, Nortisuka Mizumura
High-power semiconductor applications require a thermal interface die attach material with high thermal conductivity to efficiently release the heat generated from these devices. Current thermal interface material solutions such as thermal grease, thermal pads, and silicones have been industry standards, however may fall short in performance for high-temperature or high-power applications. This article focuses on development of a cutting-edge die attach solution for thermal interface management, focusing on fusion-type epoxy-based Ag adhesive with an extremely low storage modulus and the thermal conductivity reaching up to 30 W/mK, and also very low-modulus, low-temperature pressureless sintering silver die attach with a thermal conductivity of 70 W/mK.
{"title":"Development of High Thermally Conductive Die Attach for TIM Applications","authors":"Maciej Patelka, Shosuke Ikeda, K. Sasaki, Hiroki Myodo, Nortisuka Mizumura","doi":"10.4071/2380-4505-2019.1.000312","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000312","url":null,"abstract":"\u0000 High-power semiconductor applications require a thermal interface die attach material with high thermal conductivity to efficiently release the heat generated from these devices. Current thermal interface material solutions such as thermal grease, thermal pads, and silicones have been industry standards, however may fall short in performance for high-temperature or high-power applications. This article focuses on development of a cutting-edge die attach solution for thermal interface management, focusing on fusion-type epoxy-based Ag adhesive with an extremely low storage modulus and the thermal conductivity reaching up to 30 W/mK, and also very low-modulus, low-temperature pressureless sintering silver die attach with a thermal conductivity of 70 W/mK.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42105162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.4071/2380-4505-2019.1.000503
W. MeinholdMitchell, Caprice Gray, Jeffery B. Delisio, Ernest Kim, Christian Wells, Daniela A. Torres, P. Lewis, David Hagerstrom
A tool has been developed that supports a novel microelectronic integration paradigm whereby interconnects between components are directly established by means of microcoax wire bonding. A near-term use case of the tool is to facilitate rapid prototyping of high-bandwidth systems. When further matured, it will be able to rapidly integrate complex systems with hundreds or thousands of interconnects with minimal design time. Automatic stripping and bonding of coax wires having overall diameters between 50 and 100 μm present an array of process challenges that pose interesting demands on the material system of the wire and the bonding tool. This study reviewed a microcoax bonding system that is currently in development at Draper which is able to strip, feed, and bond microcoax wire. The system utilizes a combination of electric flame-off and thermal reflow to strip outer metal shielding and polymer dielectric layers, respectively. It leverages a rotary wire feed mechanism to precisely control wire position so that predetermined wire lengths can be established. Progress in the design of the wires, tooling, and software control architecture is reviewed.
{"title":"A Wirebonding Instrument for Insulated and Coaxial Wires","authors":"W. MeinholdMitchell, Caprice Gray, Jeffery B. Delisio, Ernest Kim, Christian Wells, Daniela A. Torres, P. Lewis, David Hagerstrom","doi":"10.4071/2380-4505-2019.1.000503","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000503","url":null,"abstract":"A tool has been developed that supports a novel microelectronic integration paradigm whereby interconnects between components are directly established by means of microcoax wire bonding. A near-term use case of the tool is to facilitate rapid prototyping of high-bandwidth systems. When further matured, it will be able to rapidly integrate complex systems with hundreds or thousands of interconnects with minimal design time. Automatic stripping and bonding of coax wires having overall diameters between 50 and 100 μm present an array of process challenges that pose interesting demands on the material system of the wire and the bonding tool. This study reviewed a microcoax bonding system that is currently in development at Draper which is able to strip, feed, and bond microcoax wire. The system utilizes a combination of electric flame-off and thermal reflow to strip outer metal shielding and polymer dielectric layers, respectively. It leverages a rotary wire feed mechanism to precisely control wire position so that predetermined wire lengths can be established. Progress in the design of the wires, tooling, and software control architecture is reviewed.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42099764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Because of good thermal, electrical, and mechanical properties, low-temperature cofired ceramic (LTCC) has shown great potential in microelectronic applications. One of the most promising directions of LTCC technology development are integrating and packing sensors. In this article, a wireless passive capacitive pressure sensor operating in the MHz range based on cofiring of heterogeneous materials with LTCC technology is proposed, and the design, simulation, and fabrication of the sensor are demonstrated and discussed. It consists of a circular spiral inductor and a capacitor of two electrodes separated by a glass medium. Furthermore, a unique process of cofiring of heterogeneous materials was introduced to avoid deformation of the capacitive embedded cavity during lamination or sintering. The results show that the inductance of the inductor and the capacitance of the capacitor embedded in the sensor are .28 μH and 16.80 pF, respectively. The novel sensor has a sensitivity of approximately 847 Hz/MPa within the pressure range from atmospheric pressure to 100 MPa.
{"title":"A Capacitive Pressure Sensor Based on Cofirable Ceramic/Glass Materials with LTCC Technology","authors":"Yue Liu, Yuanxun Li, Yongcheng Lu, Hua Su, Zhihua Tao, Mingzhou Chen, Daming Chen","doi":"10.4071/imaps.926920","DOIUrl":"https://doi.org/10.4071/imaps.926920","url":null,"abstract":"\u0000 Because of good thermal, electrical, and mechanical properties, low-temperature cofired ceramic (LTCC) has shown great potential in microelectronic applications. One of the most promising directions of LTCC technology development are integrating and packing sensors. In this article, a wireless passive capacitive pressure sensor operating in the MHz range based on cofiring of heterogeneous materials with LTCC technology is proposed, and the design, simulation, and fabrication of the sensor are demonstrated and discussed. It consists of a circular spiral inductor and a capacitor of two electrodes separated by a glass medium. Furthermore, a unique process of cofiring of heterogeneous materials was introduced to avoid deformation of the capacitive embedded cavity during lamination or sintering. The results show that the inductance of the inductor and the capacitance of the capacitor embedded in the sensor are .28 μH and 16.80 pF, respectively. The novel sensor has a sensitivity of approximately 847 Hz/MPa within the pressure range from atmospheric pressure to 100 MPa.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47634293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shuto Matsuda, T. Fujii, N. Nakada, T. Karaki, T. Kakuda
We fabricated lead-free (K,Na,Li)NbO3 (KNLN) and BaTiO3 (BT) piezoelectric ceramics using a dispenser system. After dissolving polyvinyl butyral in ethanol, a paste for extrusion was fabricated by mixing KNLN or BT ceramic powders. After several times of paste extrusion with a dispenser system, degreasing was performed at 650°C. The KNLN moldings were sintered, at 1,100–1,170°C, and sintering of BT moldings were performed by two-step sintering at 1,320°C and 1,150°C. From the x-ray diffraction pattern, the fabricated KNLN ceramics had a perovskite structure. The density of the KNLN and BT moldings fabricated by the dispenser system was 3.94 and 5.42 g/cm3, respectively. In addition, the BT moldings had the dielectric constant εr = 1.95 × 103. The Curie temperature of the BT moldings was confirmed at about 125°C, as with the BT piezoelectric ceramics fabricated by uniaxial pressure molding. The BT moldings had the piezoelectric constant d33 = 60 pC/N. The fabrication methods studied in this work provided the potential to fabricate simple three-dimensional piezoelectric ceramic devices for applications in acoustic wave sensors.
{"title":"Fabrication of Three-Dimensional Piezoelectric Ceramics Using the Dispenser System","authors":"Shuto Matsuda, T. Fujii, N. Nakada, T. Karaki, T. Kakuda","doi":"10.4071/imaps.945561","DOIUrl":"https://doi.org/10.4071/imaps.945561","url":null,"abstract":"\u0000 We fabricated lead-free (K,Na,Li)NbO3 (KNLN) and BaTiO3 (BT) piezoelectric ceramics using a dispenser system. After dissolving polyvinyl butyral in ethanol, a paste for extrusion was fabricated by mixing KNLN or BT ceramic powders. After several times of paste extrusion with a dispenser system, degreasing was performed at 650°C. The KNLN moldings were sintered, at 1,100–1,170°C, and sintering of BT moldings were performed by two-step sintering at 1,320°C and 1,150°C. From the x-ray diffraction pattern, the fabricated KNLN ceramics had a perovskite structure. The density of the KNLN and BT moldings fabricated by the dispenser system was 3.94 and 5.42 g/cm3, respectively. In addition, the BT moldings had the dielectric constant εr = 1.95 × 103. The Curie temperature of the BT moldings was confirmed at about 125°C, as with the BT piezoelectric ceramics fabricated by uniaxial pressure molding. The BT moldings had the piezoelectric constant d33 = 60 pC/N. The fabrication methods studied in this work provided the potential to fabricate simple three-dimensional piezoelectric ceramic devices for applications in acoustic wave sensors.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46107639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A bismuth oxide–based multicomponent glass system, xH3BO3-yBi2O3-(1-x-y-δ)MO-δ· rare earth oxides (REOs) with MO = TiO2, BaO, ZnO, Fe2O3, etc., and lanthanum series–based REOs, for making downhole high-pressure and high-temperature electrical feedthrough package has been developed using high-temperature melt-quenching and sintering technologies. By properly controlling phase structures in material-manufacturing processes, the obtained sealing materials have shown moisture-resistant properties in their monoclinic and tetragonal mixed phase structures but strongly hydrophobic properties in their covalent bond tetragonal phase. Sealed electrical feedthrough packages have been evaluated under boiling water immersion and 200°C/30,000 PSI water-fluid–simulated downhole harsh environments. The post electrical insulation measurement has demonstrated to be greater than 1.0 × 1014 Ω electrical resistance. This article will show that such a high–bonding strength and high–insulation strength sealing material could be used to seal electrical feed-throughs and connectors for 300°C/30,000 PSI downhole and subsea wireline, logging while drilling, and measurement while drilling tools' signal, data, and electrical power transmissions.
{"title":"Moisture-Resistant Sealing Materials for Downhole HPHT Electrical Feedthrough Package","authors":"Hua Xia, N. Settles, David DeWire","doi":"10.4071/IMAPS.942864","DOIUrl":"https://doi.org/10.4071/IMAPS.942864","url":null,"abstract":"\u0000 A bismuth oxide–based multicomponent glass system, xH3BO3-yBi2O3-(1-x-y-δ)MO-δ· rare earth oxides (REOs) with MO = TiO2, BaO, ZnO, Fe2O3, etc., and lanthanum series–based REOs, for making downhole high-pressure and high-temperature electrical feedthrough package has been developed using high-temperature melt-quenching and sintering technologies. By properly controlling phase structures in material-manufacturing processes, the obtained sealing materials have shown moisture-resistant properties in their monoclinic and tetragonal mixed phase structures but strongly hydrophobic properties in their covalent bond tetragonal phase. Sealed electrical feedthrough packages have been evaluated under boiling water immersion and 200°C/30,000 PSI water-fluid–simulated downhole harsh environments. The post electrical insulation measurement has demonstrated to be greater than 1.0 × 1014 Ω electrical resistance. This article will show that such a high–bonding strength and high–insulation strength sealing material could be used to seal electrical feed-throughs and connectors for 300°C/30,000 PSI downhole and subsea wireline, logging while drilling, and measurement while drilling tools' signal, data, and electrical power transmissions.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48678558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abstract Cooling is one of the costly factors in data centers in terms of overall power consumption. Over the past few decades, traditional cooling approaches have maintained the facility's equipme...
{"title":"Experimental Studies of Electronics Cooling Capabilities at High Altitude","authors":"Han-Yun Jhang, M. Ho, Cho-Han Lee, Fang-Shou Lee","doi":"10.4071/IMAPS.871683","DOIUrl":"https://doi.org/10.4071/IMAPS.871683","url":null,"abstract":"Abstract Cooling is one of the costly factors in data centers in terms of overall power consumption. Over the past few decades, traditional cooling approaches have maintained the facility's equipme...","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43126897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The recent advances and trends in heterogeneous integrations are presented in this study. Emphasis is placed on: (A) the definition of heterogeneous integrations, (B) the classifications of heterogeneous integrations such as heterogeneous integrations on (a) organic substrates, (b) silicon substrates (through-silicon via interposers), (c) silicon substrates (bridges), (d) fan-out RDL (redistribution-layer) substrates, and (e) ceramic substrates, and (C) the examples of heterogeneous integrations of chip-to-chip, chip-to-wafer, memory stacks, package-on-package, light-emitting diode, CMOS image sensors, microelectro-mechanical systems, vertical-cavity surface-emitting laser, and photodetector. The trends of heterogeneous integrations are also presented.
{"title":"Recent Advances and Trends in Heterogeneous Integrations","authors":"J. Lau","doi":"10.4071/IMAPS.780287","DOIUrl":"https://doi.org/10.4071/IMAPS.780287","url":null,"abstract":"\u0000 The recent advances and trends in heterogeneous integrations are presented in this study. Emphasis is placed on: (A) the definition of heterogeneous integrations, (B) the classifications of heterogeneous integrations such as heterogeneous integrations on (a) organic substrates, (b) silicon substrates (through-silicon via interposers), (c) silicon substrates (bridges), (d) fan-out RDL (redistribution-layer) substrates, and (e) ceramic substrates, and (C) the examples of heterogeneous integrations of chip-to-chip, chip-to-wafer, memory stacks, package-on-package, light-emitting diode, CMOS image sensors, microelectro-mechanical systems, vertical-cavity surface-emitting laser, and photodetector. The trends of heterogeneous integrations are also presented.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47547481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A major obstacle in screen printing conductive low-temperature curing polymer thick-film (PTF) pastes onto common flexible PET substrate materials is the substantial spread of the pastes beyond the designed line width after printing. Industry observation and controlled testing have shown this spread can be as much as 80% over the circuit design's intended line width. This phenomenon prevents designers from increasing circuit density and/or reducing circuit real estate without incorporating other more involved and higher cost patterning methods. In many cases, flexible circuit fabricators, desiring more accurate high-definition circuit elements, may have to subcontract parts out of house to incorporate alternate patterning methods. This subcontracting, in turn, leads to a loss of control of both cost and lead time. This article will provide results of numerous in-house and field testings, comparing printed line width control, edge definition, and improved conductivity of printed polymer Ag conductors on different flexible PET substrates.
{"title":"Flexible PET Substrate for High-Definition Printing of Polymer Thick-Film Conductive Pastes","authors":"A. Dobie","doi":"10.4071/imaps.788036","DOIUrl":"https://doi.org/10.4071/imaps.788036","url":null,"abstract":"\u0000 A major obstacle in screen printing conductive low-temperature curing polymer thick-film (PTF) pastes onto common flexible PET substrate materials is the substantial spread of the pastes beyond the designed line width after printing. Industry observation and controlled testing have shown this spread can be as much as 80% over the circuit design's intended line width. This phenomenon prevents designers from increasing circuit density and/or reducing circuit real estate without incorporating other more involved and higher cost patterning methods. In many cases, flexible circuit fabricators, desiring more accurate high-definition circuit elements, may have to subcontract parts out of house to incorporate alternate patterning methods. This subcontracting, in turn, leads to a loss of control of both cost and lead time. This article will provide results of numerous in-house and field testings, comparing printed line width control, edge definition, and improved conductivity of printed polymer Ag conductors on different flexible PET substrates.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48268924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Both the number and the variants of ball grid array packages (BGAs) are tending to increase on network printed board assemblies with sizes ranging from a few millimeter die size wafer level packages with low ball count to large multidie system-in-package (SiP) BGAs with 60–70 mm side lengths and thousands of I/Os. One big challenge, especially for large BGAs, SiPs, and for thin fine-pitch BGA assemblies, is the dynamic warpage during the reflow soldering process. This warpage could lead to solder balls losing contact with the solder paste and its flux during parts of the soldering process, and this may result in solder joints with irregular shapes, indicating poor or no coalescence between the added solder and the BGA balls. This defect is called head-on-pillow (HoP) and is a failure type that is difficult to determine. In this study, x-ray inspection was used as a first step to find deliberately induced HoP defects, followed by prying off of the BGAs to verify real HoP defects and the fault detection correlation between the two methods. The result clearly shows that many of the solder joints classified as potential HoP defects in the x-ray analysis have no evidence at all of HoP after pry-off. This illustrates the difficulty of determining where to draw the line between pass and fail for HoP defects when using x-ray inspection.
{"title":"Head-on-Pillow Defect Detection: X-Ray Inspection Limitations","authors":"L. Bruno, B. Gustafson","doi":"10.4071/IMAPS.871613","DOIUrl":"https://doi.org/10.4071/IMAPS.871613","url":null,"abstract":"\u0000 Both the number and the variants of ball grid array packages (BGAs) are tending to increase on network printed board assemblies with sizes ranging from a few millimeter die size wafer level packages with low ball count to large multidie system-in-package (SiP) BGAs with 60–70 mm side lengths and thousands of I/Os. One big challenge, especially for large BGAs, SiPs, and for thin fine-pitch BGA assemblies, is the dynamic warpage during the reflow soldering process. This warpage could lead to solder balls losing contact with the solder paste and its flux during parts of the soldering process, and this may result in solder joints with irregular shapes, indicating poor or no coalescence between the added solder and the BGA balls. This defect is called head-on-pillow (HoP) and is a failure type that is difficult to determine. In this study, x-ray inspection was used as a first step to find deliberately induced HoP defects, followed by prying off of the BGAs to verify real HoP defects and the fault detection correlation between the two methods. The result clearly shows that many of the solder joints classified as potential HoP defects in the x-ray analysis have no evidence at all of HoP after pry-off. This illustrates the difficulty of determining where to draw the line between pass and fail for HoP defects when using x-ray inspection.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49048226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Carroll, Douglas La Tulipe, D. Coolbaugh, R. Geer
The demand for high-performance, high-functionality packages for integrated circuits continues to grow. Three-dimensional (3D) integration is strongly being pursued to meet this demand and has started to reach maturity and industrial adoption. As advanced 3D system designs progress, requiring higher 3D interconnect density with pitches of 10 μm and lower, traditional chip attachment through solder bump technology will likely face complex manufacturing and reliability challenges. Cu-Cu thermocompression bonding has been proposed as a key 3D-enabling technology and alternative to solder. One of the main issues challenging its commercialization in high-volume manufacturing is the sensitivity of Cu-Cu bond quality to prebond surface conditions. This is especially true for die bonding applications which have limited rework options once chips have been singulated. This article outlines further development and demonstration of a tack and collective bonding scheme for Cu-Cu thermocompression bonding. This approach mitigates many of the thermal and throughput issues of a chip-level Cu-Cu attachment process by performing the quick chip alignment at a low temperature and then subsequently completing all Cu bonding simultaneously. The specific use of an intermediate handle wafer between the tack and collective bonding steps allows chips to be reconstructed into a wafer form that facilitates the cleaning and surface preparation of the chips before bonding using standard wafer processing equipment. A chip-to-wafer test structure designed for Cu pillar-to-pad bonding was used as part of this demonstration and illustrates the feasibility of the application. Full transfer of chips to a receiving device wafer using the tack and collective bonding process is shown with electrical test results and selected bond-integrity metrology confirming substantial bond yield and strength.
{"title":"Collective Cu-Cu Thermocompression Bonding Using Pillars","authors":"R. Carroll, Douglas La Tulipe, D. Coolbaugh, R. Geer","doi":"10.4071/IMAPS.741710","DOIUrl":"https://doi.org/10.4071/IMAPS.741710","url":null,"abstract":"\u0000 The demand for high-performance, high-functionality packages for integrated circuits continues to grow. Three-dimensional (3D) integration is strongly being pursued to meet this demand and has started to reach maturity and industrial adoption. As advanced 3D system designs progress, requiring higher 3D interconnect density with pitches of 10 μm and lower, traditional chip attachment through solder bump technology will likely face complex manufacturing and reliability challenges. Cu-Cu thermocompression bonding has been proposed as a key 3D-enabling technology and alternative to solder. One of the main issues challenging its commercialization in high-volume manufacturing is the sensitivity of Cu-Cu bond quality to prebond surface conditions. This is especially true for die bonding applications which have limited rework options once chips have been singulated. This article outlines further development and demonstration of a tack and collective bonding scheme for Cu-Cu thermocompression bonding. This approach mitigates many of the thermal and throughput issues of a chip-level Cu-Cu attachment process by performing the quick chip alignment at a low temperature and then subsequently completing all Cu bonding simultaneously. The specific use of an intermediate handle wafer between the tack and collective bonding steps allows chips to be reconstructed into a wafer form that facilitates the cleaning and surface preparation of the chips before bonding using standard wafer processing equipment. A chip-to-wafer test structure designed for Cu pillar-to-pad bonding was used as part of this demonstration and illustrates the feasibility of the application. Full transfer of chips to a receiving device wafer using the tack and collective bonding process is shown with electrical test results and selected bond-integrity metrology confirming substantial bond yield and strength.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44422283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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