Pub Date : 2020-09-01DOI: 10.4071/2380-4505-2020.1.000057
J. Lau, C. Ko, Tzvy-Jang Tseng, C. Peng, Kai-Ming Yang, T. Xia, P. Lin, E. Lin, Leo Chang, H. Liu, Curry Lin, D. Cheng, Winnie Lu
In this study, the design, materials, process, assembly, and reliability of a 6-side molded panel-level chip scale package (PLCSP) are presented. Emphasis is placed on the fabrication of the RDLs (redistribution layers) of the PLCSP on a large temporary panel with multiple device wafers. Since all the printed circuited board (PCB) panels are in rectangular shape, some of the device wafers are diced into two or more pieces so the panel is fully utilized. Thus, it is very high throughput. Since all the processes/equipment are PCB process/equipment (not semiconductor process/equipment), it is a very low cost process. After the fabrication of RDLs, the wafers from the PCB panel are debonded. It is followed by solder ball mounting and fabricating the 6-side molded PLCSP from the original device wafers with RDLs. The drop test and the results including failure analysis of the PLCSP are presented. Thermal cycling of the 6-side molded PLCSP PCB assembly is performed by a nonlinear temperature- and time-dependent finite-element simulation.
{"title":"Six-Side Molded Panel-Level Chip Scale Package with Multiple Diced Wafers","authors":"J. Lau, C. Ko, Tzvy-Jang Tseng, C. Peng, Kai-Ming Yang, T. Xia, P. Lin, E. Lin, Leo Chang, H. Liu, Curry Lin, D. Cheng, Winnie Lu","doi":"10.4071/2380-4505-2020.1.000057","DOIUrl":"https://doi.org/10.4071/2380-4505-2020.1.000057","url":null,"abstract":"In this study, the design, materials, process, assembly, and reliability of a 6-side molded panel-level chip scale package (PLCSP) are presented. Emphasis is placed on the fabrication of the RDLs (redistribution layers) of the PLCSP on a large temporary panel with multiple device wafers. Since all the printed circuited board (PCB) panels are in rectangular shape, some of the device wafers are diced into two or more pieces so the panel is fully utilized. Thus, it is very high throughput. Since all the processes/equipment are PCB process/equipment (not semiconductor process/equipment), it is a very low cost process. After the fabrication of RDLs, the wafers from the PCB panel are debonded. It is followed by solder ball mounting and fabricating the 6-side molded PLCSP from the original device wafers with RDLs. The drop test and the results including failure analysis of the PLCSP are presented. Thermal cycling of the 6-side molded PLCSP PCB assembly is performed by a nonlinear temperature- and time-dependent finite-element simulation.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"2020 1","pages":"000057-000066"},"PeriodicalIF":0.0,"publicationDate":"2020-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47181590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-01DOI: 10.4071/2380-4505-2020.1.000174
Masaya Toba, Kazuyuki Mitsukura, M. Yamaguchi
Semiconductor packages for high-performance devices with printed circuit boards having multi-wiring layers such as FC-BGA have been attracting attention to realize ultrareliable and low-latency communications in 5G networking. Cu wirings for the package are usually fabricated by the semi-additive process (SAP) with the de-smear process and/or the modified semi-additive process (MSAP) by using Cu film with large surface roughness. Although a de-smear process and Cu film can obtain enough adhesion between dielectric and Cu seed layer by the anchoring effect to secure reliabilities, the interface between dielectric and Cu seed layer should be smooth to achieve low attenuation of electric signals at high frequencies. Here, instead of those processes, we applied UV modification for the surface of our developed thermosetting dielectric to realize a smooth and high-adhesive seed layer against the dielectric. We obtained .5 kN/m of peel strength between dielectric and Cu seed layer despite surface roughness (Ra) of dielectric being 265 nm by the nano-level anchoring effect at UV modified layer. Because of the smooth interface by UV modification, the normalized S21 value of micro-strip line was about 29% improved compared with that assembled through Cu film with Ra of 2,400 nm at 50 GHz.
{"title":"Electroless Plating with UV Modification for Thermosetting Dielectric and Decay Suppression of High Frequency Transmission Property","authors":"Masaya Toba, Kazuyuki Mitsukura, M. Yamaguchi","doi":"10.4071/2380-4505-2020.1.000174","DOIUrl":"https://doi.org/10.4071/2380-4505-2020.1.000174","url":null,"abstract":"\u0000 Semiconductor packages for high-performance devices with printed circuit boards having multi-wiring layers such as FC-BGA have been attracting attention to realize ultrareliable and low-latency communications in 5G networking. Cu wirings for the package are usually fabricated by the semi-additive process (SAP) with the de-smear process and/or the modified semi-additive process (MSAP) by using Cu film with large surface roughness. Although a de-smear process and Cu film can obtain enough adhesion between dielectric and Cu seed layer by the anchoring effect to secure reliabilities, the interface between dielectric and Cu seed layer should be smooth to achieve low attenuation of electric signals at high frequencies. Here, instead of those processes, we applied UV modification for the surface of our developed thermosetting dielectric to realize a smooth and high-adhesive seed layer against the dielectric. We obtained .5 kN/m of peel strength between dielectric and Cu seed layer despite surface roughness (Ra) of dielectric being 265 nm by the nano-level anchoring effect at UV modified layer. Because of the smooth interface by UV modification, the normalized S21 value of micro-strip line was about 29% improved compared with that assembled through Cu film with Ra of 2,400 nm at 50 GHz.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48758687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-01DOI: 10.4071/2380-4505-2020.1.000185
G. Capuz, M. Lofrano, C. Gerets, F. Duval, P. Bex, J. Derakhshandeh, K. Vanstreels, A. Phommahaxay, E. Beyne, Andy Miller
For die to wafer bonding of high-density interconnects and fine pitch microbumps developing and characterizing suitable underfill materials are required. In general, underfill serve to fill the spaces in-between microbumps for protection and reliability. Among the different types of underfill, Non-Conductive Film (NCF) has the advantages of fillet and volume control, and a built-in flux to aid wetting. However, challenges arise for thin dies and microbumps with fine pitches on film lamination, voiding, transparency, filler percentage, dicing compatibility and most importantly, deformation behavior and possibility to improve solder joint wetting. In a Die-to-Wafer D2W stacking with a Sn solder bump interconnect to Cu UBM, concern is high on the Cu pad oxidation due to the repeated TCB cycles that accelerate oxidation on neighboring dies. Process mitigation is needed to help reducing the oxidation. But even so, an NCF must have good embedded flux activation. Another main factor for an NCF to have efficient TCB process with good solder joint wetting, is the NCF deformation quality in which is a function of its viscosity. This parameter has direct impact on the deformation of solder bumps. High viscosity NCF would be difficult to deform, thus preventing solder contact to pad during TCB reflow temperature. High bond force is required and could lead to reduced alignment accuracy. Filler entrapment is also a subsequent concern for high filler loading, high viscosity NCF. For a low viscous NCF, careful attention in process characterization is needed in TCB with low bond force. Solder joint wetting is a problem with excessive squeeze-out due to fast and instantaneous deformation. With low viscosity, not only the bond force applied should be low, but the deformation behavior should also be understood to enable an effective NCF. We seek to demonstrate in this paper a creative methodology for Non-Conductive Film (NCF) material characterization, considering the factors of NCF viscosity, deformation, and solder squeeze-out. Characterizing NCF viscosity at fast TCB profiles is challenging considering deformation behavior of both the NCF itself and the solder bumps that shaped the solder squeeze-out and wetting. Furthermore, in this paper we use TCB tool position tracking to define the deformation curve of NCF film as a function of temperature and time at very fast profile of TCB. We use material viscosity curve as reference in relation to the actual deformation, and predict dynamic deformation based on Reynold’s equation within TCB profile duration. The experiments were performed with different heating ramp rates at target above Sn reflow of ~250C interface temperature. The deformation analysis is not limited to thin film sandwiched between parallel plates. Deformation test was performed on chips with and without microbumps and with rigid flat glass surface and its combinations. Deformation of underfill is recorded in the readout of TCB tool. As valida
{"title":"A novel method for characterization of Ultra Low Viscosity NCF layers using TCB for 3D Assembly","authors":"G. Capuz, M. Lofrano, C. Gerets, F. Duval, P. Bex, J. Derakhshandeh, K. Vanstreels, A. Phommahaxay, E. Beyne, Andy Miller","doi":"10.4071/2380-4505-2020.1.000185","DOIUrl":"https://doi.org/10.4071/2380-4505-2020.1.000185","url":null,"abstract":"\u0000 For die to wafer bonding of high-density interconnects and fine pitch microbumps developing and characterizing suitable underfill materials are required. In general, underfill serve to fill the spaces in-between microbumps for protection and reliability. Among the different types of underfill, Non-Conductive Film (NCF) has the advantages of fillet and volume control, and a built-in flux to aid wetting. However, challenges arise for thin dies and microbumps with fine pitches on film lamination, voiding, transparency, filler percentage, dicing compatibility and most importantly, deformation behavior and possibility to improve solder joint wetting.\u0000 In a Die-to-Wafer D2W stacking with a Sn solder bump interconnect to Cu UBM, concern is high on the Cu pad oxidation due to the repeated TCB cycles that accelerate oxidation on neighboring dies. Process mitigation is needed to help reducing the oxidation. But even so, an NCF must have good embedded flux activation. Another main factor for an NCF to have efficient TCB process with good solder joint wetting, is the NCF deformation quality in which is a function of its viscosity. This parameter has direct impact on the deformation of solder bumps.\u0000 High viscosity NCF would be difficult to deform, thus preventing solder contact to pad during TCB reflow temperature. High bond force is required and could lead to reduced alignment accuracy. Filler entrapment is also a subsequent concern for high filler loading, high viscosity NCF.\u0000 For a low viscous NCF, careful attention in process characterization is needed in TCB with low bond force. Solder joint wetting is a problem with excessive squeeze-out due to fast and instantaneous deformation. With low viscosity, not only the bond force applied should be low, but the deformation behavior should also be understood to enable an effective NCF.\u0000 We seek to demonstrate in this paper a creative methodology for Non-Conductive Film (NCF) material characterization, considering the factors of NCF viscosity, deformation, and solder squeeze-out. Characterizing NCF viscosity at fast TCB profiles is challenging considering deformation behavior of both the NCF itself and the solder bumps that shaped the solder squeeze-out and wetting.\u0000 Furthermore, in this paper we use TCB tool position tracking to define the deformation curve of NCF film as a function of temperature and time at very fast profile of TCB. We use material viscosity curve as reference in relation to the actual deformation, and predict dynamic deformation based on Reynold’s equation within TCB profile duration.\u0000 The experiments were performed with different heating ramp rates at target above Sn reflow of ~250C interface temperature. The deformation analysis is not limited to thin film sandwiched between parallel plates. Deformation test was performed on chips with and without microbumps and with rigid flat glass surface and its combinations. Deformation of underfill is recorded in the readout of TCB tool.\u0000 As valida","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"2020 1","pages":"000185-000191"},"PeriodicalIF":0.0,"publicationDate":"2020-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43094672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-01DOI: 10.4071/2380-4505-2020.1.000150
Ikumoto Raihei, Itakura Yuki, S. Tachibana, Hisamitsu Yamamoto
Cu plating bath for high-speed electrodeposition of Cu pillar was designed in consideration of a flat top morphology of pillar and a pillar height uniformity. An ideal polarization curve was assumed for the flat top morphology. To obtain the ideal polarization curve, an effect of organic additive concentration and solution agitation on the polarization curve were investigated. The basic bath components were optimized considering a Wagner number to improve the pillar height uniformity. To confirm the pillar top morphology and the pillar height uniformity, a 300-mm diameter wafer was plated with Cu at 20 A/dm2. As a result, improved pillar top morphology and pillar height uniformity were obtained. The optimized plating bath was applied to the plating of a large-size panel of 415 × 510 mm.
设计了高速电沉积铜柱的镀铜浴，考虑了铜柱的平顶形貌和高度均匀性。对平顶形貌假定了理想的极化曲线。为了得到理想的极化曲线，研究了有机添加剂浓度和溶液搅拌对极化曲线的影响。考虑瓦格纳数，优化了基本浴组件，提高了柱高均匀性。为了确定柱顶形貌和柱高均匀性，在直径为300 mm的晶圆上镀上20 a /dm2的Cu。改善了矿柱顶部形貌和矿柱高度均匀性。将优化后的镀液应用于415 × 510 mm大尺寸面板的电镀。
{"title":"Optimization of High-Speed Electrolytic Plating of Copper Pillar to Achieve a Flat Top Morphology and Height Uniformity","authors":"Ikumoto Raihei, Itakura Yuki, S. Tachibana, Hisamitsu Yamamoto","doi":"10.4071/2380-4505-2020.1.000150","DOIUrl":"https://doi.org/10.4071/2380-4505-2020.1.000150","url":null,"abstract":"\u0000 Cu plating bath for high-speed electrodeposition of Cu pillar was designed in consideration of a flat top morphology of pillar and a pillar height uniformity. An ideal polarization curve was assumed for the flat top morphology. To obtain the ideal polarization curve, an effect of organic additive concentration and solution agitation on the polarization curve were investigated. The basic bath components were optimized considering a Wagner number to improve the pillar height uniformity. To confirm the pillar top morphology and the pillar height uniformity, a 300-mm diameter wafer was plated with Cu at 20 A/dm2. As a result, improved pillar top morphology and pillar height uniformity were obtained. The optimized plating bath was applied to the plating of a large-size panel of 415 × 510 mm.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46609013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Cauwe, B. Vandevelde, Chinmay Nawghane, Marnix Van De Slyeke, E. Bosman, J. Verhegge, Alexia Coulon, S. Heltzel
High-density interconnect (HDI) printed circuit boards (PCBs) and associated assemblies are essential to allow space projects to benefit from the ever increasing complexity and functionality of modern integrated circuits such as field-programmable gate arrays, digital signal processors and application processors. Increasing demands for functionality translate into higher signal speeds combined with an increasing number of input/outputs (I/Os). To limit the overall package size, the contact pad pitch of the components is reduced. The combination of a high number of I/Os with a reduced pitch places additional demands onto the PCB, requiring the use of laser-drilled microvias, high-aspect ratio core vias, and small track width and spacing. Although the associated advanced manufacturing processes have been widely used in commercial, automotive, medical, and military applications, reconciling these advancements in capability with the reliability requirements for space remains a challenge. Two categories of the HDI technology are considered: two levels of staggered microvias (basic HDI) and (up to) three levels of stacked microvias (complex HDI). In this article, the qualification of the basic HDI technology in accordance with ECSS-Q-ST-70-60C is described. At 1.0-mm pitch, the technology passes all testing successfully. At .8-mm pitch, failures are encountered during interconnection stress testing and conductive anodic filament testing. These failures provide the basis for updating the design rules for HDI PCBs.
{"title":"High-Density Interconnect Technology Assessment of Printed Circuit Boards for Space Applications","authors":"M. Cauwe, B. Vandevelde, Chinmay Nawghane, Marnix Van De Slyeke, E. Bosman, J. Verhegge, Alexia Coulon, S. Heltzel","doi":"10.4071/imaps.1212898","DOIUrl":"https://doi.org/10.4071/imaps.1212898","url":null,"abstract":"High-density interconnect (HDI) printed circuit boards (PCBs) and associated assemblies are essential to allow space projects to benefit from the ever increasing complexity and functionality of modern integrated circuits such as field-programmable gate arrays, digital signal processors and application processors. Increasing demands for functionality translate into higher signal speeds combined with an increasing number of input/outputs (I/Os). To limit the overall package size, the contact pad pitch of the components is reduced. The combination of a high number of I/Os with a reduced pitch places additional demands onto the PCB, requiring the use of laser-drilled microvias, high-aspect ratio core vias, and small track width and spacing. Although the associated advanced manufacturing processes have been widely used in commercial, automotive, medical, and military applications, reconciling these advancements in capability with the reliability requirements for space remains a challenge. Two categories of the HDI technology are considered: two levels of staggered microvias (basic HDI) and (up to) three levels of stacked microvias (complex HDI). In this article, the qualification of the basic HDI technology in accordance with ECSS-Q-ST-70-60C is described. At 1.0-mm pitch, the technology passes all testing successfully. At .8-mm pitch, failures are encountered during interconnection stress testing and conductive anodic filament testing. These failures provide the basis for updating the design rules for HDI PCBs.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"17 1","pages":"79-88"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46993147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A double-layer ceramic electronic packaging technology that survives the Venusian surface temperature of 465°C was developed using a ceramic interlayer dielectric with gold conductors. A 60-μm ceramic interlayer dielectric served as the insulator between the top and bottom gold conductors on high-purity ceramic substrates. Test devices with AuPtPd metallization were attached to the top gold pads using a thick-film gold paste. Thermal aging for 115 h at 500°C and thermal cycling from room temperature to 450°C were performed. Dielectric leakage tests of the interlayer ceramic layer between the top and bottom gold conductors revealed a leakage current density of less than 50 × 10−7 A/cm2 at 600 V after thermal cycling. Gold conductor resistance increased slightly after thermal cycling. The die shear test showed a 33% decrease in die shear strength after thermal tests and its 6.16 kg-F die shear strength satisfies the Military Standard Product Testing Services (MIL-STD) method.
{"title":"High-Temperature Double-Layer Ceramic Packaging Substrates","authors":"Ardalan Nasiri, S. Ang","doi":"10.4071/imaps.1123535","DOIUrl":"https://doi.org/10.4071/imaps.1123535","url":null,"abstract":"\u0000 A double-layer ceramic electronic packaging technology that survives the Venusian surface temperature of 465°C was developed using a ceramic interlayer dielectric with gold conductors. A 60-μm ceramic interlayer dielectric served as the insulator between the top and bottom gold conductors on high-purity ceramic substrates. Test devices with AuPtPd metallization were attached to the top gold pads using a thick-film gold paste. Thermal aging for 115 h at 500°C and thermal cycling from room temperature to 450°C were performed. Dielectric leakage tests of the interlayer ceramic layer between the top and bottom gold conductors revealed a leakage current density of less than 50 × 10−7 A/cm2 at 600 V after thermal cycling. Gold conductor resistance increased slightly after thermal cycling. The die shear test showed a 33% decrease in die shear strength after thermal tests and its 6.16 kg-F die shear strength satisfies the Military Standard Product Testing Services (MIL-STD) method.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"17 1","pages":"99-105"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44657271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rakesh Kumar, F. Ke, Dustin England, Angie Summers, L. Young
The rapid growth and adoption of microelectronics around the world has resulted in an increased awareness of potential environmental issues related to their use and disposal. Halogens, which have had various uses in microelectronics over the years, are known to emit toxic and corrosive gases during the disposal of electronic waste. Many organizations have applied pressure to the electronics industry to eliminate halogens completely (e.g., fluorine, chlorine, and bromine) from their products. Among the various efforts toward environmentally friendly products, making electronics completely halogen-free has gained significant attention, particularly in Asia and Europe. This initiative even impacts conformal coatings worldwide, on which most electronics rely for their long-term protection, reliability, and high performance against water and other corrosive harsh environments. Among the various coating options, the parylene family of conformal coatings offers beneficial properties to the microelectronics, improved over many properties offered by common epoxies, acrylics, urethanes, and silicones. Although parylene N is the only commercially available parylene that does not contain any halogens, its barrier performance against moisture and other corrosive chemicals is not quite as robust as the other parylenes. To meet the industry’s current and future requirements, a new halogen-free parylene, ParyFree®, has been developed. This study introduces a new parylene type to the microelectronics industry and shares the characterization and qualification results of ParyFree® parylene conformal coating for the protection, reliability, and robust performance of microelectronics. Testing on the new coating includes IPX water resistance, corrosion resistance, and qualification per IPC-CC-830B.
{"title":"A New Halogen-Free Parylene for High Performance and Reliability of Microelectronics in Harsh Environments","authors":"Rakesh Kumar, F. Ke, Dustin England, Angie Summers, L. Young","doi":"10.4071/imaps.1120416","DOIUrl":"https://doi.org/10.4071/imaps.1120416","url":null,"abstract":"\u0000 The rapid growth and adoption of microelectronics around the world has resulted in an increased awareness of potential environmental issues related to their use and disposal. Halogens, which have had various uses in microelectronics over the years, are known to emit toxic and corrosive gases during the disposal of electronic waste. Many organizations have applied pressure to the electronics industry to eliminate halogens completely (e.g., fluorine, chlorine, and bromine) from their products. Among the various efforts toward environmentally friendly products, making electronics completely halogen-free has gained significant attention, particularly in Asia and Europe. This initiative even impacts conformal coatings worldwide, on which most electronics rely for their long-term protection, reliability, and high performance against water and other corrosive harsh environments. Among the various coating options, the parylene family of conformal coatings offers beneficial properties to the microelectronics, improved over many properties offered by common epoxies, acrylics, urethanes, and silicones. Although parylene N is the only commercially available parylene that does not contain any halogens, its barrier performance against moisture and other corrosive chemicals is not quite as robust as the other parylenes. To meet the industry’s current and future requirements, a new halogen-free parylene, ParyFree®, has been developed. This study introduces a new parylene type to the microelectronics industry and shares the characterization and qualification results of ParyFree® parylene conformal coating for the protection, reliability, and robust performance of microelectronics. Testing on the new coating includes IPX water resistance, corrosion resistance, and qualification per IPC-CC-830B.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46486905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Masaya Toba, S. Nomoto, Nobuhito Komuro, Kazuyuki Mitsukura, S. Abe, T. Masuko, Kazuhiko Kurafuchi
Abstract Semiconductor packages for high-performance devices with printed circuit boards having multiwiring layers such as flip-chip ball grid array have been attracting the attention to realize ul...
采用倒装球栅阵列等多层印刷电路板的高性能器件半导体封装技术已成为实现高性能器件封装的热点。
{"title":"Assembly of Cu Wirings with Ultrasmooth and High-Adhesive Electroless Cu Seed Layer by Using UV Modification and Low Attenuation of High-Frequency Transmission Property","authors":"Masaya Toba, S. Nomoto, Nobuhito Komuro, Kazuyuki Mitsukura, S. Abe, T. Masuko, Kazuhiko Kurafuchi","doi":"10.4071/imaps.1100914","DOIUrl":"https://doi.org/10.4071/imaps.1100914","url":null,"abstract":"Abstract Semiconductor packages for high-performance devices with printed circuit boards having multiwiring layers such as flip-chip ball grid array have been attracting the attention to realize ul...","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"17 1","pages":"45-51"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46489020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ardalan Nasiri, S. Ang, T. Cannon, E. Porter, Kaoru Porter, C. Chapin, Ruiqi Chen, D. Senesky
Abstract An electronic packaging technology that survives the simulated Venusian surface temperature of 465°C and 96 bar pressure in carbon dioxide (CO2) and nitrogen environments, without the corr...
{"title":"High-Temperature Electronics Packaging for Simulated Venus Condition","authors":"Ardalan Nasiri, S. Ang, T. Cannon, E. Porter, Kaoru Porter, C. Chapin, Ruiqi Chen, D. Senesky","doi":"10.4071/imaps.1115241","DOIUrl":"https://doi.org/10.4071/imaps.1115241","url":null,"abstract":"Abstract An electronic packaging technology that survives the simulated Venusian surface temperature of 465°C and 96 bar pressure in carbon dioxide (CO2) and nitrogen environments, without the corr...","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"17 1","pages":"59-66"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44734648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abstract In this study, low-temperature cofired ceramic (LTCC) and 3D-printed ceramic interposers are designed and fabricated for a double-sided power electronic module. The interposer acts as elec...
{"title":"Fabrication of Ceramic Interposers for Module Packaging","authors":"R. Alizadeh, Kaoru Porter, T. Cannon, S. Ang","doi":"10.4071/imaps.1114553","DOIUrl":"https://doi.org/10.4071/imaps.1114553","url":null,"abstract":"Abstract In this study, low-temperature cofired ceramic (LTCC) and 3D-printed ceramic interposers are designed and fabricated for a double-sided power electronic module. The interposer acts as elec...","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"17 1","pages":"67-72"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43802663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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