In this work, magnesium oxide was elaborated on a glass substrate at 450°C by a pneumatic spray technique. The structural, optical, and electrical properties were studied at different MgO concentrations (.05, .10, .15, and .2 mol L−1). Poly-crystalline MgO films with a cubic structure with a strong (002) preferred orientation were observed at all sprayed films, with a maximum crystallite size of 21.4 nm attained by the sprayed film at .2 mol L−1. Good transmission was found in the deposited MgO thin films with lowest molarity. The transmission of MgO thin films decreases rapidly as the wavelength increases in the range of 300–400 nm and then increases slowly at higher wavelengths. The bandgap of MgO thin films decreases as the molarity increases, and the band gap values range between 4.8 and 4.3 eV. The Urbach energy values range between 375 and 519 meV. The electrical resistance of our films is on the order of 2 × 107Ω. The prepared MgO thin films were suitable for electronic packaging; they are capable to provide very stable and high secondary electron emission combined with low bandgap energy and low electrical resistance.
{"title":"Synthesis and Characterization of Physical Properties of MgO Thin Films by Various Concentrations","authors":"N. Chaouch, S. Benramache, S. Lakel","doi":"10.4071/imaps.963453","DOIUrl":"https://doi.org/10.4071/imaps.963453","url":null,"abstract":"\u0000 In this work, magnesium oxide was elaborated on a glass substrate at 450°C by a pneumatic spray technique. The structural, optical, and electrical properties were studied at different MgO concentrations (.05, .10, .15, and .2 mol L−1). Poly-crystalline MgO films with a cubic structure with a strong (002) preferred orientation were observed at all sprayed films, with a maximum crystallite size of 21.4 nm attained by the sprayed film at .2 mol L−1. Good transmission was found in the deposited MgO thin films with lowest molarity. The transmission of MgO thin films decreases rapidly as the wavelength increases in the range of 300–400 nm and then increases slowly at higher wavelengths. The bandgap of MgO thin films decreases as the molarity increases, and the band gap values range between 4.8 and 4.3 eV. The Urbach energy values range between 375 and 519 meV. The electrical resistance of our films is on the order of 2 × 107Ω. The prepared MgO thin films were suitable for electronic packaging; they are capable to provide very stable and high secondary electron emission combined with low bandgap energy and low electrical resistance.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43643322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abstract Most circuit boards operate in environments that have the potential to be exposed to moisture, either in vapor or liquid form. Because low-cost circuit boards can readily absorb moisture, ...
大多数电路板在有可能暴露于水汽或液体形式的环境中工作。因为低成本的电路板很容易吸收水分，…
{"title":"A Technique for Detecting Moisture Absorption in Printed Circuit Boards","authors":"J. Craven, Ariel Oldag, R. Dean","doi":"10.4071/imaps.1014123","DOIUrl":"https://doi.org/10.4071/imaps.1014123","url":null,"abstract":"Abstract Most circuit boards operate in environments that have the potential to be exposed to moisture, either in vapor or liquid form. Because low-cost circuit boards can readily absorb moisture, ...","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"17 1","pages":"28-33"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70526000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Simon Schambeck, M. Hutter, J. Jaeschke, A. Deutinger, M. Schneider-Ramelow
Abstract The combination of continuous miniaturization of electronics and the demanding reliability requirements for industrial and automotive electronics is one big challenge for emerging packagin...
电子产品的不断小型化与工业和汽车电子产品对可靠性的苛刻要求相结合，是新兴封装行业面临的一大挑战。
{"title":"Sporadic Early Life Solder Ball Detachment Effects on Subsequent Microstructure Evolution and Fatigue of Solder Joints in Wafer-Level Chip-Scale Packages","authors":"Simon Schambeck, M. Hutter, J. Jaeschke, A. Deutinger, M. Schneider-Ramelow","doi":"10.4071/imaps.966816","DOIUrl":"https://doi.org/10.4071/imaps.966816","url":null,"abstract":"Abstract The combination of continuous miniaturization of electronics and the demanding reliability requirements for industrial and automotive electronics is one big challenge for emerging packagin...","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"17 1","pages":"13-22"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70531826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lei Fu, M. Bhagavat, C. Selvanayagam, Ken Leong, Ivor Barber
Power, performance, and area gains are important metrics driving the complementary metal–oxide–semiconductor (CMOS) technology from older nodes to newer ones. Over past several decades, a steady downscaling of feature sizes of CMOS technology has been a leading force enabling continual improvement in circuit speeds and cost per functionality. Increase in functionality drives larger number of inputs/outputs (I/Os), and the scaling-driven small intellectual property (IP) block sizes force these larger number of I/Os to be accommodated by reduction of I/O pitches. The result is an unrelenting pressure to reduce bump pitches from one generation of CMOS to another. In contrast to 14-nm/16-nm nodes which used 150-um bump pitch coming out of a die, for 7-nm node, the industry is targeting 130-um bump pitch for high performance devices. With this pitch reduction, conventional tin/silver (SnAg) solder bumps face limitations in terms of bridging. Cu pillar bumps are the best candidate for smaller bump pitches. However, for large die sizes prevalent in high-performance computing (HPC), the Cu pillar bumps will induce higher stress on the silicon resulting in higher risks of extremely low K (ELK) cracking. If copper pillar bumps are not properly developed, then there is a risk of marginal reliability in terms of chip package interaction. The situation becomes even more dire in large die sizes, where coefficient of thermal expansion mismatch between silicon and laminate substrate magnifies the stress. The present article discusses successful development of Cu pillar bumps for 7-nm technology. The development program included a 2-step development path. In the first step, extensive thermomechanical modeling was carried out to find optimal design of copper pillar bump for robustness of interactions with 7-nm back end of line ELK layers. In the second step, a 460-mm2 7-nm Silicon test vehicle was fabricated, and its assembly process was optimized to characterize the copper pillar bumps and prove their extended reliability on 7-nm silicon. As a result of this development, copper pillar technology has been qualified on Advanced Micro Devices (AMD) products. Today, copper pillar is a fully integral part of AMD's ever-growing 7-nm product offering in HPC.
{"title":"Cu Pillar Bump Development for 7-nm Chip Package Interaction (CPI) Technology","authors":"Lei Fu, M. Bhagavat, C. Selvanayagam, Ken Leong, Ivor Barber","doi":"10.4071/imaps.968260","DOIUrl":"https://doi.org/10.4071/imaps.968260","url":null,"abstract":"\u0000 Power, performance, and area gains are important metrics driving the complementary metal–oxide–semiconductor (CMOS) technology from older nodes to newer ones. Over past several decades, a steady downscaling of feature sizes of CMOS technology has been a leading force enabling continual improvement in circuit speeds and cost per functionality. Increase in functionality drives larger number of inputs/outputs (I/Os), and the scaling-driven small intellectual property (IP) block sizes force these larger number of I/Os to be accommodated by reduction of I/O pitches. The result is an unrelenting pressure to reduce bump pitches from one generation of CMOS to another. In contrast to 14-nm/16-nm nodes which used 150-um bump pitch coming out of a die, for 7-nm node, the industry is targeting 130-um bump pitch for high performance devices. With this pitch reduction, conventional tin/silver (SnAg) solder bumps face limitations in terms of bridging. Cu pillar bumps are the best candidate for smaller bump pitches. However, for large die sizes prevalent in high-performance computing (HPC), the Cu pillar bumps will induce higher stress on the silicon resulting in higher risks of extremely low K (ELK) cracking. If copper pillar bumps are not properly developed, then there is a risk of marginal reliability in terms of chip package interaction. The situation becomes even more dire in large die sizes, where coefficient of thermal expansion mismatch between silicon and laminate substrate magnifies the stress. The present article discusses successful development of Cu pillar bumps for 7-nm technology. The development program included a 2-step development path. In the first step, extensive thermomechanical modeling was carried out to find optimal design of copper pillar bump for robustness of interactions with 7-nm back end of line ELK layers. In the second step, a 460-mm2 7-nm Silicon test vehicle was fabricated, and its assembly process was optimized to characterize the copper pillar bumps and prove their extended reliability on 7-nm silicon. As a result of this development, copper pillar technology has been qualified on Advanced Micro Devices (AMD) products. Today, copper pillar is a fully integral part of AMD's ever-growing 7-nm product offering in HPC.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46336340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Thomas, M. Dijk, M. Dreissigacker, S. Hoffmann, H. Walter, K. Becker, M. Schneider-Ramelow
Abstract Transfer-molding process is enjoying growing interest when aiming for novel high-power density system-in-packages (power SiPs), where not only transistors and diodes but also drivers, pass...
{"title":"Ferrites in Transfer-Molded Power SiPs: Challenges in Packaging","authors":"T. Thomas, M. Dijk, M. Dreissigacker, S. Hoffmann, H. Walter, K. Becker, M. Schneider-Ramelow","doi":"10.4071/IMAPS.1064487","DOIUrl":"https://doi.org/10.4071/IMAPS.1064487","url":null,"abstract":"Abstract Transfer-molding process is enjoying growing interest when aiming for novel high-power density system-in-packages (power SiPs), where not only transistors and diodes but also drivers, pass...","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"17 1","pages":"35-44"},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45585565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hoang Linh Bach, Daniel Dirksen, Christoph Blechinger, T. Endres, C. F. Bayer, A. Schletz, M. März
This study encompasses the development of a high-voltage and high-temperature–capable package for power electronic applications based on the embedding of silicon carbide (SiC) semiconductor devices in the ceramic circuit carrier such as the direct bonded copper (DBC) substrate. By sealing semiconductor devices into DBC substrates, high temperature, high voltage, and high current capability as well as high corrosion resistance can be achieved compared with the state-of-the-art printed circuit board (PCB) embedding technology. The power devices are attached with high-temperature stable solder and sinter material and are surrounded by thermal conductive ceramic and high-temperature–capable potting materials that enable the complete package to operate at 250°C or above. Furthermore, the single embedded packages can be stacked together to multilevel DBC topologies with increased voltage blocking characteristics. Thus, current limits of the PCB and low-temperature cofired ceramic–based multilayer solutions are exceeded and will be confirmed in the course of this study. This package is designed to carry out the maximal performance of SiC and future wide bandgap devices. It is a promising solution not only for applications in harsh ambient environments such as aerospace and turbine, geothermal well logging, and downhole oil and gas wells but also for hybrid electric/electric vehicle and energy conversion.
{"title":"Stackable SiC-Embedded Ceramic Packages for High-Voltage and High-Temperature Power Electronic Applications","authors":"Hoang Linh Bach, Daniel Dirksen, Christoph Blechinger, T. Endres, C. F. Bayer, A. Schletz, M. März","doi":"10.4071/imaps.952440","DOIUrl":"https://doi.org/10.4071/imaps.952440","url":null,"abstract":"\u0000 This study encompasses the development of a high-voltage and high-temperature–capable package for power electronic applications based on the embedding of silicon carbide (SiC) semiconductor devices in the ceramic circuit carrier such as the direct bonded copper (DBC) substrate. By sealing semiconductor devices into DBC substrates, high temperature, high voltage, and high current capability as well as high corrosion resistance can be achieved compared with the state-of-the-art printed circuit board (PCB) embedding technology. The power devices are attached with high-temperature stable solder and sinter material and are surrounded by thermal conductive ceramic and high-temperature–capable potting materials that enable the complete package to operate at 250°C or above. Furthermore, the single embedded packages can be stacked together to multilevel DBC topologies with increased voltage blocking characteristics. Thus, current limits of the PCB and low-temperature cofired ceramic–based multilayer solutions are exceeded and will be confirmed in the course of this study. This package is designed to carry out the maximal performance of SiC and future wide bandgap devices. It is a promising solution not only for applications in harsh ambient environments such as aerospace and turbine, geothermal well logging, and downhole oil and gas wells but also for hybrid electric/electric vehicle and energy conversion.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48745502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Khazaka, D. Martineau, T. Youssef, Thanh-Long Le, S. Azzopardi
The rapid and localized heating techniques allow the joining of temperature-sensitive materials and components without thermal induced damage commonly encountered when high-temperature solder reflow processes are used. This is also advantageous for making assemblies with materials having a large difference in the coefficient of thermal expansion without induced bowing or cracking. The use of exothermic reactive foil sandwiched between solder preforms is a promising local and rapid soldering process because it does not require any external heat source. The reactive foil is formed from alternatively stacked nanolayers of Ni and Al until it reaches the total film thickness. Once the film is activated by using an external power source, a reaction takes place and releases such an amount of energy that is transferred to the solder preforms. If this amount of energy is high enough, solder preforms melt and insure the adhesion between the materials of the assembly. The influences of the applied pressure, the reactive film (RF) thickness as well as the solder, and the attached materials chemical composition and thickness were investigated. It was shown that the applied pressure during the process has a strong effect on the joint initial quality with voids ratio decreases from 64% to 26% for pressure values between .5 and 100 kPa, respectively. This can be explained by the improvement of the solder flow under higher pressure leading to a better surface wettability and voids elimination. Otherwise, the joint quality was found to be improved once the solder melting duration is increased. This relationship was observed when the thickness of the reactive foil is increased (additional induced energy) or the thickness of solders, Cu, and/or Si is decreased (less energy consumption). The microstructure of the AuSn joint achieved using the RFs shows very fine phase distribution compared with the one obtained using conventional solder reflow process in the oven because of high cooling rate. The mechanical properties of the joint were evaluated using shear tests performed on 350-μm-thick silicon diodes assembled on active metal brazed substrates under a pressure of 100 kPa. The RFs were 60 μm thick and sandwiched between two 25-μm-thick 96.5Sn3Ag.5Cu (SAC) preforms. The voids ratio was about 37% for the tested samples and shear strength values above 9.5 MPa were achieved which remains largely higher than MIL-STD-883H requirements. Finally, the process impact on the electrical properties of the assembled diodes was compared with a commonly used solder reflow assembly and the results show a negligible variation.
{"title":"Rapid and Localized Soldering Using Reactive Films for Electronic Applications","authors":"R. Khazaka, D. Martineau, T. Youssef, Thanh-Long Le, S. Azzopardi","doi":"10.4071/imaps.955217","DOIUrl":"https://doi.org/10.4071/imaps.955217","url":null,"abstract":"\u0000 The rapid and localized heating techniques allow the joining of temperature-sensitive materials and components without thermal induced damage commonly encountered when high-temperature solder reflow processes are used. This is also advantageous for making assemblies with materials having a large difference in the coefficient of thermal expansion without induced bowing or cracking. The use of exothermic reactive foil sandwiched between solder preforms is a promising local and rapid soldering process because it does not require any external heat source. The reactive foil is formed from alternatively stacked nanolayers of Ni and Al until it reaches the total film thickness. Once the film is activated by using an external power source, a reaction takes place and releases such an amount of energy that is transferred to the solder preforms. If this amount of energy is high enough, solder preforms melt and insure the adhesion between the materials of the assembly. The influences of the applied pressure, the reactive film (RF) thickness as well as the solder, and the attached materials chemical composition and thickness were investigated. It was shown that the applied pressure during the process has a strong effect on the joint initial quality with voids ratio decreases from 64% to 26% for pressure values between .5 and 100 kPa, respectively. This can be explained by the improvement of the solder flow under higher pressure leading to a better surface wettability and voids elimination. Otherwise, the joint quality was found to be improved once the solder melting duration is increased. This relationship was observed when the thickness of the reactive foil is increased (additional induced energy) or the thickness of solders, Cu, and/or Si is decreased (less energy consumption). The microstructure of the AuSn joint achieved using the RFs shows very fine phase distribution compared with the one obtained using conventional solder reflow process in the oven because of high cooling rate. The mechanical properties of the joint were evaluated using shear tests performed on 350-μm-thick silicon diodes assembled on active metal brazed substrates under a pressure of 100 kPa. The RFs were 60 μm thick and sandwiched between two 25-μm-thick 96.5Sn3Ag.5Cu (SAC) preforms. The voids ratio was about 37% for the tested samples and shear strength values above 9.5 MPa were achieved which remains largely higher than MIL-STD-883H requirements. Finally, the process impact on the electrical properties of the assembled diodes was compared with a commonly used solder reflow assembly and the results show a negligible variation.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47564431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hongyan Xu, Yaochun Shen, Yihua Hu, Jianqiang Li, Ju Xu
A highly reliable three-dimensional network structure joint was fabricated based on Cu/Ni/Sn powder with double-layer coatings and transient liquid phase bonding (TLPB) technology for high temperature application. The Cu/Ni/Sn joint is characterized by Cu metal particles embedded in the matrix of (Cu,Ni)6Sn5/Ni3Sn4 intermetallic compounds (IMCs), with a low void ratio, and can be reflowed at low temperatures (<260°C), but it can reliably work at a high temperature up to 415°C. Cu/Ni/Sn double-layer powders with different Sn layer and Ni layer thickness were was fabricated and compressed as preform used for TLPB joint bonding. The microstructure and phase composition evolution for Cu/Sn and Cu/Ni/Sn systems during reflow and aging were comparatively studied. Two kinds of interfacial structure designs were made, and corresponding interfacial microscopic morphology was analyzed and compared under once and twice reflow soldering processes. The results indicated that the Sn-coating layer was completely consumed to form (Cu,Ni)6Sn5/Ni3Sn4 IMCs, and the Cu/Ni/Sn joint had a lower void ratio and a higher shear strength than those of Cu/Sn. The mechanism of the Ni-coating layer inhibiting phase transformation was studied. The high reliable three-dimensional network structure joint based on Cu/Ni/Sn double-layer powder was fabricated for high temperature application.
{"title":"Fabrication of Highly Reliable Joint Based on Cu/Ni/Sn Double-Layer Powder for High Temperature Application","authors":"Hongyan Xu, Yaochun Shen, Yihua Hu, Jianqiang Li, Ju Xu","doi":"10.4071/imaps.960671","DOIUrl":"https://doi.org/10.4071/imaps.960671","url":null,"abstract":"\u0000 A highly reliable three-dimensional network structure joint was fabricated based on Cu/Ni/Sn powder with double-layer coatings and transient liquid phase bonding (TLPB) technology for high temperature application. The Cu/Ni/Sn joint is characterized by Cu metal particles embedded in the matrix of (Cu,Ni)6Sn5/Ni3Sn4 intermetallic compounds (IMCs), with a low void ratio, and can be reflowed at low temperatures (<260°C), but it can reliably work at a high temperature up to 415°C. Cu/Ni/Sn double-layer powders with different Sn layer and Ni layer thickness were was fabricated and compressed as preform used for TLPB joint bonding. The microstructure and phase composition evolution for Cu/Sn and Cu/Ni/Sn systems during reflow and aging were comparatively studied. Two kinds of interfacial structure designs were made, and corresponding interfacial microscopic morphology was analyzed and compared under once and twice reflow soldering processes. The results indicated that the Sn-coating layer was completely consumed to form (Cu,Ni)6Sn5/Ni3Sn4 IMCs, and the Cu/Ni/Sn joint had a lower void ratio and a higher shear strength than those of Cu/Sn. The mechanism of the Ni-coating layer inhibiting phase transformation was studied. The high reliable three-dimensional network structure joint based on Cu/Ni/Sn double-layer powder was fabricated for high temperature application.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42709238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The quality of molded packages heavily depends on the process parameters of the molding process and on the material characteristics of epoxy molding compounds (EMCs). When defects are introduced into the electronic packages in one of the last steps in the manufacturing process, namely, during encapsulation, it may cause high failure costs. To decrease the number of defects due to the molding process, a comprehensive understanding of the impact of process parameters and variations in the characteristics of the EMC on package quality is necessary. This study aimed at supporting a deeper understanding of the influence of process parameters and variations in the material characteristics of the EMC on package quality. A systematic approach was introduced to generate a process model describing the correlation between process parameters and package quality to obtain optimum process parameters for the transfer molding process. The influence of the alterations in material characteristics of the EMC due to prolonged storage duration and humidity on void formation and wire sweep was investigated. An online monitoring method, dielectric analysis (DEA), was implemented into the transfer molding process to monitor the variations in the cure behavior of the EMC. A second molding compound was used to analyze the similarities in the alteration behavior of the molding compounds when subjected to the same preconditioning and to generalize the characteristic information obtained from DEA.
{"title":"Process Optimization and Implementation of Online Monitoring Process in the Transfer Molding for Electronic Packaging","authors":"B. Kaya, J. Kaiser, K. Becker, T. Braun, K. Lang","doi":"10.4071/imaps.954402","DOIUrl":"https://doi.org/10.4071/imaps.954402","url":null,"abstract":"\u0000 The quality of molded packages heavily depends on the process parameters of the molding process and on the material characteristics of epoxy molding compounds (EMCs). When defects are introduced into the electronic packages in one of the last steps in the manufacturing process, namely, during encapsulation, it may cause high failure costs. To decrease the number of defects due to the molding process, a comprehensive understanding of the impact of process parameters and variations in the characteristics of the EMC on package quality is necessary. This study aimed at supporting a deeper understanding of the influence of process parameters and variations in the material characteristics of the EMC on package quality. A systematic approach was introduced to generate a process model describing the correlation between process parameters and package quality to obtain optimum process parameters for the transfer molding process. The influence of the alterations in material characteristics of the EMC due to prolonged storage duration and humidity on void formation and wire sweep was investigated. An online monitoring method, dielectric analysis (DEA), was implemented into the transfer molding process to monitor the variations in the cure behavior of the EMC. A second molding compound was used to analyze the similarities in the alteration behavior of the molding compounds when subjected to the same preconditioning and to generalize the characteristic information obtained from DEA.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46807572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.4071/2380-4505-2019.1.000360
Yuan Zhao, D. Katze, John Wood, B. Tolla, H. Yun
Over the past decade, electronic parts have become smaller, more complex, and highly functional. This is well understood for many products within the consumer and handheld markets. Miniaturization, however, is also impacting sectors such as aerospace and automotive, pushing the limits of already harsh environments. As more power is driven through active devices, the integrity of materials used to provide the electrically conductive interfaces is becoming increasingly critical. For many applications, adhesive films have been the preferred material because they offer a variety of performance and operational advantages such high electrical and thermal conductivity, uniform bondlines, superior adhesion, and low processing temperatures. Today, as miniaturization pushes power-density limits and although devices are also being exposed to high operating temperatures, even for traditionally robust adhesive films, it is challenging to cope with these conditions. In sectors such as aerospace where high reliability is essential, material capability must evolve to deliver on fail-safe performance expectations. This study compares the performance of an established and widely used electrically conductive film adhesive with that of a newly developed film designed to provide improved mechanical performance over a higher elevated temperature range.
{"title":"High Temperature and High Reliability Performance of Electrically Conductive Film Adhesives for RF Grounding Applications","authors":"Yuan Zhao, D. Katze, John Wood, B. Tolla, H. Yun","doi":"10.4071/2380-4505-2019.1.000360","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000360","url":null,"abstract":"\u0000 Over the past decade, electronic parts have become smaller, more complex, and highly functional. This is well understood for many products within the consumer and handheld markets. Miniaturization, however, is also impacting sectors such as aerospace and automotive, pushing the limits of already harsh environments. As more power is driven through active devices, the integrity of materials used to provide the electrically conductive interfaces is becoming increasingly critical. For many applications, adhesive films have been the preferred material because they offer a variety of performance and operational advantages such high electrical and thermal conductivity, uniform bondlines, superior adhesion, and low processing temperatures. Today, as miniaturization pushes power-density limits and although devices are also being exposed to high operating temperatures, even for traditionally robust adhesive films, it is challenging to cope with these conditions. In sectors such as aerospace where high reliability is essential, material capability must evolve to deliver on fail-safe performance expectations. This study compares the performance of an established and widely used electrically conductive film adhesive with that of a newly developed film designed to provide improved mechanical performance over a higher elevated temperature range.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43018317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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