Zhe Song, J. Chu, Kun-Fu Huang, L. Norén, Zhenxiao Fu, Yun Liu
Al2O3/K2O3–B2O3–SiO2 low temperature cofired ceramics (LTCC) dielectric materials doped with CaCO3 were prepared by using a solid-state reaction. The microstructure and dielectric properties of Al2O3/K–B–Si borosilicate, together with the effects of Ca doping, were investigated. A new material system candidate of Al2O3/KBSiO borosilicate doped by Ca was achieved after sintering at 880°C, which presents an optimized performance on dielectric properties with a permittivity ϵr < 8 and dielectric loss tan δ ≤ 0.002 and excellent stabilities across very broad frequency and temperature ranges. Most importantly, the initial results have also indicated that the new dielectric composite material is well compatible with the existing LTCC process, suggesting a considerable potential for practical LTCC applications.
{"title":"Low Temperature Cofiring and Dielectric Properties of Ca-Doped Al2O3/K2O3–B2O3–SiO2 Composite Ceramics for LTCC Applications","authors":"Zhe Song, J. Chu, Kun-Fu Huang, L. Norén, Zhenxiao Fu, Yun Liu","doi":"10.4071/IMAPS.606076","DOIUrl":"https://doi.org/10.4071/IMAPS.606076","url":null,"abstract":"Al2O3/K2O3–B2O3–SiO2 low temperature cofired ceramics (LTCC) dielectric materials doped with CaCO3 were prepared by using a solid-state reaction. The microstructure and dielectric properties of Al2O3/K–B–Si borosilicate, together with the effects of Ca doping, were investigated. A new material system candidate of Al2O3/KBSiO borosilicate doped by Ca was achieved after sintering at 880°C, which presents an optimized performance on dielectric properties with a permittivity ϵr < 8 and dielectric loss tan δ ≤ 0.002 and excellent stabilities across very broad frequency and temperature ranges. Most importantly, the initial results have also indicated that the new dielectric composite material is well compatible with the existing LTCC process, suggesting a considerable potential for practical LTCC applications.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"15 1","pages":"81-85"},"PeriodicalIF":0.0,"publicationDate":"2018-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42371588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This research is for developing a new light emitting diode (LED) indoor lighting module with high color rendering index greater than 95. When the LED is operated, electrical energy is generated and heat is released. The failing of heat dispersal degrades the performance and decreases the operating life. To manage the thermal problem effectively, several approaches have been tested in this research study. A heat sink is designed to absorb and transfer heat from the LED module. To analyze the heat flow and thermal stress of the designed LED products effectively, hexahedral mesh generation has been implemented. Heat transfer analysis was performed to find an optimal conductive material. The outcomes of this research study suggest the best material for LED products and show the result of thermal transfer simulation.
{"title":"Thermal Stress Analysis for High CRI LED Indoor Lighting Module","authors":"Jonghwan Lee, K. Kwon","doi":"10.4071/IMAPS.655549","DOIUrl":"https://doi.org/10.4071/IMAPS.655549","url":null,"abstract":"\u0000 This research is for developing a new light emitting diode (LED) indoor lighting module with high color rendering index greater than 95. When the LED is operated, electrical energy is generated and heat is released. The failing of heat dispersal degrades the performance and decreases the operating life. To manage the thermal problem effectively, several approaches have been tested in this research study. A heat sink is designed to absorb and transfer heat from the LED module. To analyze the heat flow and thermal stress of the designed LED products effectively, hexahedral mesh generation has been implemented. Heat transfer analysis was performed to find an optimal conductive material. The outcomes of this research study suggest the best material for LED products and show the result of thermal transfer simulation.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42761946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zihan Wu, Junki Min, M. Pulugurtha, Siddharth Ravichandran, V. Sundaram, R. Tummala
Double-side or 3-D integration of high-precision and high-performance bandpass and lowpass filters that are interconnected with through-vias were designed and demonstrated on 100-micron thin glass substrates for ultra-miniaturized diplexer components. A novel process for achieving high precision with large-area fabrication was developed to achieve much improved tolerance in electrical performance. High-precision, high quality factor, and high component densities with thin-film layers on glass were used to realize innovative topologies on glass for high out-of-band rejection and low insertion loss. Low-loss 100-μm thick glass cores and multiple layers of 15-μm thin polymer films were used to build the filters on substrates. The demonstrated diplexers have dimensions of 2.3 ×2.8 ×.2 mm. Aided by the dimensional stability of glass and process control with semiadditive patterning, the performance of the fabricated filters showed excellent correlation with the simulation. The impact of process-sensitivity analysis on diplexer performance was also analyzed. Finally, a unique and innovative process solution was demonstrated to control the process deviation and achieve good diplexer tolerance. The performance deviation was controlled by ~3.5X with the new process.
{"title":"3D Integrated High-Precision Passives on Thin Glass Substrates for Miniaturized and High-Performance RF Components","authors":"Zihan Wu, Junki Min, M. Pulugurtha, Siddharth Ravichandran, V. Sundaram, R. Tummala","doi":"10.4071/IMAPS.656641","DOIUrl":"https://doi.org/10.4071/IMAPS.656641","url":null,"abstract":"\u0000 Double-side or 3-D integration of high-precision and high-performance bandpass and lowpass filters that are interconnected with through-vias were designed and demonstrated on 100-micron thin glass substrates for ultra-miniaturized diplexer components. A novel process for achieving high precision with large-area fabrication was developed to achieve much improved tolerance in electrical performance. High-precision, high quality factor, and high component densities with thin-film layers on glass were used to realize innovative topologies on glass for high out-of-band rejection and low insertion loss. Low-loss 100-μm thick glass cores and multiple layers of 15-μm thin polymer films were used to build the filters on substrates. The demonstrated diplexers have dimensions of 2.3 ×2.8 ×.2 mm. Aided by the dimensional stability of glass and process control with semiadditive patterning, the performance of the fabricated filters showed excellent correlation with the simulation. The impact of process-sensitivity analysis on diplexer performance was also analyzed. Finally, a unique and innovative process solution was demonstrated to control the process deviation and achieve good diplexer tolerance. The performance deviation was controlled by ~3.5X with the new process.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45241126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bharath Bharadwaj, SriNithish Kandagadla, Praveen J. Nadkarni, V. Krishna, T. Seetharam, K. N. Seetharamu
The need for compactness and efficiency of processing devices has kept increasing rapidly over the past few years. This need for compactness has driven the dice to be stacked one above the other. But with this come the difficulty of heat dissipation and its characterization because there are multiple heat sources and a single effective heat-conductive path. Hence, it becomes important to know the distribution and characterization of heat and temperature to provide effective cooling systems. In this article, we discuss the temperature distribution of various power configurations on stacked dice with five dice, when the dice are in staggered arrangement. The simulations have been carried out for both free convection and forced convection conditions using the ANSYS commercial software. The linear Superposition principle (LSP) is demonstrated on these configurations and validated with the results obtained from ANSYS simulation. LSP can be applied for the quick estimation of die temperatures with negligible error.
{"title":"A Simple Method for Thermal Characterization of Stacked Die Electronic Packages in Staggered Arrangement","authors":"Bharath Bharadwaj, SriNithish Kandagadla, Praveen J. Nadkarni, V. Krishna, T. Seetharam, K. N. Seetharamu","doi":"10.4071/IMAPS.658722","DOIUrl":"https://doi.org/10.4071/IMAPS.658722","url":null,"abstract":"\u0000 The need for compactness and efficiency of processing devices has kept increasing rapidly over the past few years. This need for compactness has driven the dice to be stacked one above the other. But with this come the difficulty of heat dissipation and its characterization because there are multiple heat sources and a single effective heat-conductive path. Hence, it becomes important to know the distribution and characterization of heat and temperature to provide effective cooling systems. In this article, we discuss the temperature distribution of various power configurations on stacked dice with five dice, when the dice are in staggered arrangement. The simulations have been carried out for both free convection and forced convection conditions using the ANSYS commercial software. The linear Superposition principle (LSP) is demonstrated on these configurations and validated with the results obtained from ANSYS simulation. LSP can be applied for the quick estimation of die temperatures with negligible error.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49489611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Liangyu Chen, P. Neudeck, R. Meredith, D. Lukco, D. Spry, L. Nakley, K. Phillips, G. Beheim, G. Hunter
This article presents experimental results of a prototype high-temperature cofired ceramic (HTCC) package with Au/Pt metallization in a three-phase harsh environment test that culminated with a 60-d demonstration in a simulated Venus surface environment consisting of a 465°C corrosive atmosphere at 90 bar pressure. The prototype package is based on a previously developed and reported HTCC package successfully tested with multiple analog and digital silicon carbide high-temperature semiconductor integrated circuits in 500°C Earth air ambient for more than 10,000 hours, and short-term tested at temperatures above 800°C. The three-phase harsh environment test started with 48 h in 465°C Earth air, followed by 48 h in 465°C nitrogen at 90 bar pressure and 1,400 h in a simulated Venus surface environment of 465°C corrosive atmosphere at 90 bar. In addition to in situ electrical tests in a three-phase harsh environment and posttest electrical diagnosis, initial posttest analysis of the package materials and surfaces was performed to assess the stability of the packaging materials in the testing environments, as well as the surface conditions after the test. The test in the simulated Venus environment was implemented in the NASA Glenn Extreme Environment Rig. The results of this study suggest that an effective encapsulation of areas of surface metallization and vicinities may help improve the long-term electrical performance of an HTCC alumina packaging system in a Venus environment.
{"title":"Sixty Earth-Day Test of a Prototype Pt/HTCC Alumina Package in a Simulated Venus Environment","authors":"Liangyu Chen, P. Neudeck, R. Meredith, D. Lukco, D. Spry, L. Nakley, K. Phillips, G. Beheim, G. Hunter","doi":"10.4071/IMAPS.873073","DOIUrl":"https://doi.org/10.4071/IMAPS.873073","url":null,"abstract":"\u0000 This article presents experimental results of a prototype high-temperature cofired ceramic (HTCC) package with Au/Pt metallization in a three-phase harsh environment test that culminated with a 60-d demonstration in a simulated Venus surface environment consisting of a 465°C corrosive atmosphere at 90 bar pressure. The prototype package is based on a previously developed and reported HTCC package successfully tested with multiple analog and digital silicon carbide high-temperature semiconductor integrated circuits in 500°C Earth air ambient for more than 10,000 hours, and short-term tested at temperatures above 800°C. The three-phase harsh environment test started with 48 h in 465°C Earth air, followed by 48 h in 465°C nitrogen at 90 bar pressure and 1,400 h in a simulated Venus surface environment of 465°C corrosive atmosphere at 90 bar. In addition to in situ electrical tests in a three-phase harsh environment and posttest electrical diagnosis, initial posttest analysis of the package materials and surfaces was performed to assess the stability of the packaging materials in the testing environments, as well as the surface conditions after the test. The test in the simulated Venus environment was implemented in the NASA Glenn Extreme Environment Rig. The results of this study suggest that an effective encapsulation of areas of surface metallization and vicinities may help improve the long-term electrical performance of an HTCC alumina packaging system in a Venus environment.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42983814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The most common type of electronic packaging, the printed circuit board (PCB), is also useful for realizing low-cost environmental sensors for applications such as measuring increases in the salinity of water. Salts adhering to relocated coastal sand can leach into and contaminate freshwater bodies. When adjusted for temperature, the presence of the leached salt in freshwater can be detected by measuring the accompanying increase in electrical conductivity (EC) of the resulting aqueous solution. To estimate the increase in EC from salt leaching from a mass of sand, a technique was developed based on using a low-cost planar PCB sensor, 2 g of the sand, and 125 mL of distilled water. Using the sensor, the electrical conductance is measured in the distilled water, in the distilled water with 1 g of added sand, and in the distilled water with 2 g of added sand. After a line is fitted to a plot of the three data points, the slope of that line represents an estimate of the expected increase in electrical conduc...
{"title":"An Electronic Packaging Approach to Improving an Environmental Sensor and Sensing Technique","authors":"R. Dean, Rebecca E. Dean","doi":"10.4071/IMAPS.526068","DOIUrl":"https://doi.org/10.4071/IMAPS.526068","url":null,"abstract":"The most common type of electronic packaging, the printed circuit board (PCB), is also useful for realizing low-cost environmental sensors for applications such as measuring increases in the salinity of water. Salts adhering to relocated coastal sand can leach into and contaminate freshwater bodies. When adjusted for temperature, the presence of the leached salt in freshwater can be detected by measuring the accompanying increase in electrical conductivity (EC) of the resulting aqueous solution. To estimate the increase in EC from salt leaching from a mass of sand, a technique was developed based on using a low-cost planar PCB sensor, 2 g of the sand, and 125 mL of distilled water. Using the sensor, the electrical conductance is measured in the distilled water, in the distilled water with 1 g of added sand, and in the distilled water with 2 g of added sand. After a line is fitted to a plot of the three data points, the slope of that line represents an estimate of the expected increase in electrical conduc...","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"15 1","pages":"41-47"},"PeriodicalIF":0.0,"publicationDate":"2018-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41563397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
New technology based on mixing of standard alloy SnCu in form of solder paste with copper paste was presented. This technology allows the production of solder joints with higher standoff consisting of intermetallic compounds. Such solder joints were qualified for high temperature applications by investigation of thermal stability of overlapped solder joints. For this purpose a special test bench for the investigation of remelting temperature up to 300°C was developed.
{"title":"Thermal Stability of Intermetallic Cu–Sn Interconnections for High Temperature Applications","authors":"A. Novikov, M. Nowottnick","doi":"10.4071/IMAPS.529384","DOIUrl":"https://doi.org/10.4071/IMAPS.529384","url":null,"abstract":"New technology based on mixing of standard alloy SnCu in form of solder paste with copper paste was presented. This technology allows the production of solder joints with higher standoff consisting of intermetallic compounds. Such solder joints were qualified for high temperature applications by investigation of thermal stability of overlapped solder joints. For this purpose a special test bench for the investigation of remelting temperature up to 300°C was developed.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"15 1","pages":"35-40"},"PeriodicalIF":0.0,"publicationDate":"2018-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46177413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The objective of this work is to introduce and evaluate a new end-of-aisle cooling design which consists of three cooling configurations. The key objectives of close-coupled cooling are to enable controlled cooling of information technology (IT) equipment, flexible and modular design, and the containment of hot air exhaust from the cold air. The thermal performance of the proposed solution is evaluated using computational fluid dynamics modeling. A computational model of a small size data center room has been developed. The room is modeled to be a hot aisle containment setup, i.e., the hot air exhaust exiting for each row is contained and directed within a specific volume. The cold aisle is separated from the hot aisle by means of banks of heat exchangers (HXs) placed on either side of the containment aisle. Based on the placement of rack fans, the design is divided into three sub-designs—Case 1: passive HXs with rack fan walls; Case 2: active HXs (coupled with fans) with rack fan walls; Case 3: active HX...
{"title":"Thermal Performance Evaluation of a New Close-Coupled Cooling Solution including Cooling Failure Analysis","authors":"M. Sahini, D. Agonafer","doi":"10.4071/IMAPS.528113","DOIUrl":"https://doi.org/10.4071/IMAPS.528113","url":null,"abstract":"The objective of this work is to introduce and evaluate a new end-of-aisle cooling design which consists of three cooling configurations. The key objectives of close-coupled cooling are to enable controlled cooling of information technology (IT) equipment, flexible and modular design, and the containment of hot air exhaust from the cold air. The thermal performance of the proposed solution is evaluated using computational fluid dynamics modeling. A computational model of a small size data center room has been developed. The room is modeled to be a hot aisle containment setup, i.e., the hot air exhaust exiting for each row is contained and directed within a specific volume. The cold aisle is separated from the hot aisle by means of banks of heat exchangers (HXs) placed on either side of the containment aisle. Based on the placement of rack fans, the design is divided into three sub-designs—Case 1: passive HXs with rack fan walls; Case 2: active HXs (coupled with fans) with rack fan walls; Case 3: active HX...","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"15 1","pages":"21-34"},"PeriodicalIF":0.0,"publicationDate":"2018-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46859601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Lau, Ming Li, N. Fan, E. Kuah, Zhang Li, K. Tan, Tony Chen, Iris Xu, Margie Li, Y. Cheung, Wu Kai, J. Hao, R. Beica, Thomas Taylor, C. Ko, Henry Yang, Yao-Der Chen, S. Lim, N. Lee, Jiang Ran, Koh Sau Wee, Q. Yong, Cao Xi, Mian Tao, J. Lo, Ricky S. W. Lee
This study is for fan-out wafer-level packaging with chip-first (die face-up) formation. Chips with Cu contact-pads on the front side and a die attach film on the backside are picked and placed face-up on a temporary-glass-wafer carrier with a thin layer of light-to-heat conversion material. It is followed by compression molding with an epoxy molding compound (EMC) and a post-mold cure on the reconstituted wafer carrier and then backgrinding the molded EMC to expose the Cu contact-pads of the chips. The next step is to build up the redistribution layers (RDLs) from the Cu contact-pads and then mount the solder balls. This is followed by the debonding of the carrier with a laser and then the dicing of the whole reconstituted wafer into individual packages. A 300-mm reconstituted wafer with a package/die ratio = 1.8 and a die-top EMC cap = 100 μm has also been fabricated (a total of 325 test packages on the reconstituted wafer). This test package has three RDLs; the line width/spacing of the first RDL is 5 ...
{"title":"Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution-Layers (RDLs)","authors":"J. Lau, Ming Li, N. Fan, E. Kuah, Zhang Li, K. Tan, Tony Chen, Iris Xu, Margie Li, Y. Cheung, Wu Kai, J. Hao, R. Beica, Thomas Taylor, C. Ko, Henry Yang, Yao-Der Chen, S. Lim, N. Lee, Jiang Ran, Koh Sau Wee, Q. Yong, Cao Xi, Mian Tao, J. Lo, Ricky S. W. Lee","doi":"10.4071/IMAPS.522798","DOIUrl":"https://doi.org/10.4071/IMAPS.522798","url":null,"abstract":"This study is for fan-out wafer-level packaging with chip-first (die face-up) formation. Chips with Cu contact-pads on the front side and a die attach film on the backside are picked and placed face-up on a temporary-glass-wafer carrier with a thin layer of light-to-heat conversion material. It is followed by compression molding with an epoxy molding compound (EMC) and a post-mold cure on the reconstituted wafer carrier and then backgrinding the molded EMC to expose the Cu contact-pads of the chips. The next step is to build up the redistribution layers (RDLs) from the Cu contact-pads and then mount the solder balls. This is followed by the debonding of the carrier with a laser and then the dicing of the whole reconstituted wafer into individual packages. A 300-mm reconstituted wafer with a package/die ratio = 1.8 and a die-top EMC cap = 100 μm has also been fabricated (a total of 325 test packages on the reconstituted wafer). This test package has three RDLs; the line width/spacing of the first RDL is 5 ...","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"14 1","pages":"123-131"},"PeriodicalIF":0.0,"publicationDate":"2017-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46497329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Bultitude, J. McConnell, L. Jones, G. Miller, J. Magee, A. Templeton, A. Gurav, R. Phillips
There is a long-established market for high temperature multilayer ceramic capacitors (MLCCs) that operate at 150°C and higher in downhole oil and gas exploration, and military and aerospace applications. To maximize the capacitance density and achieve a high degree of mechanical robustness, stacks and leaded form factors have been used with high melting point–Pb-containing solders as the preferred interconnects. However, Pb-containing solders are limited to temperatures below 300°C and are banned from many commercial and automotive applications with further legislation limiting their use planned in the future. Common Pb-free solders such as SAC 305 or SnSb alloys are in widespread use, but their performance at prolonged exposures at 200°C is limited. Exposures to high reflow temperatures during assembly, especially successive reflow operations, can also compromise interconnect integrity. Higher temperature gold-containing solders are widely available, but these are cost-prohibitive and so are not viable ...
{"title":"A Comparison Between Solders & Transient Liquid Phase Sintered Interconnects in High Temperature Multilayer Ceramic Capacitors","authors":"J. Bultitude, J. McConnell, L. Jones, G. Miller, J. Magee, A. Templeton, A. Gurav, R. Phillips","doi":"10.4071/IMAPS.522150","DOIUrl":"https://doi.org/10.4071/IMAPS.522150","url":null,"abstract":"There is a long-established market for high temperature multilayer ceramic capacitors (MLCCs) that operate at 150°C and higher in downhole oil and gas exploration, and military and aerospace applications. To maximize the capacitance density and achieve a high degree of mechanical robustness, stacks and leaded form factors have been used with high melting point–Pb-containing solders as the preferred interconnects. However, Pb-containing solders are limited to temperatures below 300°C and are banned from many commercial and automotive applications with further legislation limiting their use planned in the future. Common Pb-free solders such as SAC 305 or SnSb alloys are in widespread use, but their performance at prolonged exposures at 200°C is limited. Exposures to high reflow temperatures during assembly, especially successive reflow operations, can also compromise interconnect integrity. Higher temperature gold-containing solders are widely available, but these are cost-prohibitive and so are not viable ...","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"2017 1","pages":"000075-000082"},"PeriodicalIF":0.0,"publicationDate":"2017-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45219108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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