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FCCSP IMC Growth under Reliability Stress Following Automotive Standards 遵循汽车标准的可靠性应力下FCCSP IMC增长
Q4 Engineering Pub Date : 2019-01-01 DOI: 10.4071/IMAPS.735545
Wei-Wei Liu, Berdy Weng, J. Li, C. Yeh
The Kirkendall void (KV) has been a well-known issue for long term reliability of semiconductor interconnects. KVs exist at the interfaces of Cu and Sn and the growing intermetallic compound (IMC) Cu6Sn5 at the initial stage, and a part of the IMC is converted to Cu3Sn when the environmental stress added. In this article, all the assembled packages pass the condition of unbiased long-term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000 h of high-temperature storage. A large numbers of KVs was observed after 200 cycles of temperature cycling. Various assembly structures were monitored, and various IMC thicknesses were concluded to be functions of stress test. Cu3Sn, Ni3Sn4, and Cu6Sn5 are not significantly affected by heat, but Ni3Sn4 grows steadily.
Kirkendall空隙(KV)一直是半导体互连的长期可靠性的众所周知的问题。初始阶段,在Cu和Sn以及生长的金属间化合物(IMC)Cu6Sn5的界面处存在KVs,当环境应力增加时,部分IMC转化为Cu3Sn。在本文中,所有组装的封装都通过了无偏长期可靠性测试的条件,特别是2000次温度循环测试和2000小时高温储存。在200次温度循环之后观察到大量的KV。对各种组装结构进行了监测,并得出各种IMC厚度是应力测试的函数。Cu3Sn、Ni3Sn4和Cu6Sn5不受热的显著影响,但Ni3Sn5稳定生长。
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引用次数: 3
Elevated Standoff Heights of Solder Joint Interconnections Can Result in Appreciable Stress and Warpage Relief 提高焊点互连的高度可以显著减轻应力和翘曲
Q4 Engineering Pub Date : 2019-01-01 DOI: 10.4071/IMAPS.735566
E. Suhir, S. Yi, Jennie S. Hwang, R. Ghaffarian
The “head-in-pillow” (HnP) defects in lead-free solder joint interconnections of Integrated Circuit (IC) packages with conventional (small) standoff heights of the solder joints, and particularly in packages with fine pitches, are attributed by many electronic material scientists to the three major causes: attributes of the manufacturing process, solder material properties, and design-related issues. The latter are thought to be caused primarily by elevated stresses in the solder material, as well as by the excessive warpage of the Printed Circuit Board (PCB)-package assembly and particularly by the differences in the thermally induced curvatures of the PCB and the package. In this analysis, the stress and warpage issue is addressed using an analytical predictive stress model. The model is a modification and an extension of the model developed back in 1980s by the first author. It is assumed that it is the difference in the postfabrication deflections of the PCB-package assembly that is the root cause of the solder material failures and particularly and perhaps the HnP defects. The calculated data based on the developed stress model suggest that the replacement of the conventional ball grid array (BGA) designs with designs with elevated standoff heights of the solder joints could result in significant stress and warpage relief and, hopefully, in a lower propensity of the IC package to HnP defects as well. The general concepts are illustrated by a numerical example, in which the responses to the change in temperature of a conventional design, referred to as BGA, and a design with solder joints with elevated standoff heights, referred to as column grid array (CGA), are compared. The computed data indicated that the effective stress in the solder material was relieved by about 40% and the difference between the maximum deflections of the PCB and the package was reduced by about 60%, when the BGA design was replaced by a CGA system. Although no definite proof that the use of solder joints with elevated standoff heights will lessen the package propensity to the HnP defects is provided, the authors nonetheless think that there is a reason to believe that the application of solder joints with elevated standoff heights could result in a substantial improvement in the general IC package performance, including, perhaps, its propensity to HnP defects.
许多电子材料科学家将集成电路(IC)封装的无铅焊点互连中的“头枕”(HnP)缺陷归因于三个主要原因:制造工艺的属性、焊点材料的特性和设计相关问题。后者被认为主要是由焊料中的应力升高引起的,以及印刷电路板(PCB)封装组件的过度翘曲,特别是PCB和封装的热诱导曲率的差异。在本分析中,应力和翘曲问题是使用分析预测应力模型来解决的。该模型是第一作者在20世纪80年代开发的模型的修改和扩展。假设pcb封装组件的制造后挠度的差异是焊料材料失效的根本原因,特别是可能是HnP缺陷。基于所开发的应力模型的计算数据表明,将传统的球栅阵列(BGA)设计替换为提高焊点高度的设计,可以显著缓解应力和翘曲,并有望降低IC封装产生HnP缺陷的倾向。通过一个数值例子说明了一般概念,其中比较了传统设计(称为BGA)和具有升高对峙高度的焊点设计(称为柱栅阵列(CGA))对温度变化的响应。计算结果表明,用CGA系统代替BGA设计后,焊料中的有效应力降低了约40%,PCB与封装的最大挠度之差减小了约60%。虽然没有明确的证据表明,使用高隔高的焊点会减少封装对HnP缺陷的倾向,但作者仍然认为,有理由相信,使用高隔高的焊点可能会导致总体IC封装性能的实质性改善,包括,也许,其对HnP缺陷的倾向。
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引用次数: 2
Characterization of Low-Inductance Microcoaxial Cables for Power Distribution 配电用低电感微同轴电缆的特性研究
Q4 Engineering Pub Date : 2018-10-01 DOI: 10.4071/IMAPS.729301
Daniela A. Torres, A. Kopa, S. Barron, R. McCormick, R. White, Caprice Gray
Low-impedance microcoaxial cables have been developed to supply power to microchips. These uniquely low-inductance cables are enabled by a very thin dielectric compared with a conventional 50-Ω cable. These cables will be used in a novel packaging platform in which traditional interconnects are replaced by microscale coaxial cables. This method saves time and cost for small production volumes and custom electronics, compared with high density interconnects and silicon interposer technologies. These microcoaxial cables are designed to have minimal impedance to meet the stringent power supply requirements of today's electronics. As a concrete example, we consider a Kintex 7 Field-Programmable Gate Array (FPGA). To power this chip with interconnect lengths of 25 mm and a voltage ripple less than 30 mV, a resistance of 3.20–6.40 mΩ/mm and an inductance of 12–15 pH/mm is needed. The tight voltage ripple constraint is what makes this device challenging to design power distribution for. One cable fabricated by Draper, to achieve these power requirements, is the focus of this article. The Draper cable consists of a 127-μm Copper core, 12-μm polyesterimide dielectric layer, and 55-μm gold shield. The measured resistance per unit length at DC, inductance per unit length, capacitance per unit length, and characteristic impedance of the Draper cable are 2.0 mΩ/mm, 40 pH/mm, 118 pF/mm, and 6.56 Ω, respectively.
低阻抗微轴向电缆已经被开发用于向微芯片供电。与传统的50Ω电缆相比,这些独特的低电感电缆由非常薄的电介质实现。这些电缆将用于一种新型封装平台,在该平台中,传统的互连被微型同轴电缆取代。与高密度互连和硅中介层技术相比,这种方法为小批量生产和定制电子产品节省了时间和成本。这些微轴电缆设计为具有最小阻抗,以满足当今电子产品的严格电源要求。作为一个具体的例子,我们考虑了Kintex 7现场可编程门阵列(FPGA)。为使该芯片的互连长度为25 mm,电压纹波小于30 mV,需要3.20–6.40 mΩ/mm的电阻和12–15 pH/mm的电感。严格的电压纹波限制使该设备在设计配电时具有挑战性。Draper制造的一根电缆,为了达到这些功率要求,是本文的重点。Draper电缆由127μm铜芯、12μm聚酯酰胺介电层和55μm金屏蔽组成。Draper电缆在直流条件下测得的单位长度电阻、单位长度电感、单位长度电容和特性阻抗分别为2.0 mΩ/mm、40 pH/mm、118 pF/mm和6.56Ω。
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引用次数: 2
A Numerical Study on Mitigation of Flying Dies in Compression Molding of Microelectronic Packages 微电子封装压缩成型飞模减缓的数值研究
Q4 Engineering Pub Date : 2018-10-01 DOI: 10.4071/2380-4505-2018.1.000355
M. Dreissigacker, O. Hoelck, J. Bauer, T. Braun, K. Becker, M. Schneider-Ramelow, K. Lang
Compression molding with liquid encapsulants is a crucial process in microelectronic packaging. Material properties of highly filled systems of reactive epoxy molding compounds depend on process conditions in a complex manner, such as shear-thinning behavior, which is superimposed by a time- and temperature-dependent conversion rate, both strongly affecting viscosity. The focus is set on forces exerted on individual dice during encapsulation in fan-out wafer-level packaging (FOWLP). The presented framework consists of an analytical approach to calculate the melt front velocity and simulations carried out to capture the nonlinear kinematics, chemorheology, and to extract forces exerted on individual dice. It offers separate evaluation of pressure and shear contributions for two cases, 0° and 45° between the dice' frontal area and the melt front. Process parameters, such as compression speed, thus cycle time, and process temperature, are determined to keep the forces on the dice below the critical level, where drag forces exceed adhesive forces. As a result, process parameters are determined to minimize flying dice and thereby maximize yield. The approach is easily transferable to arbitrary geometries and is therefore well suited to face the challenges that come with the current efforts toward the transition from FOWLP to larger substrates.
液体封装压缩成型是微电子封装的关键工艺。反应性环氧成型化合物的高填充体系的材料性能以复杂的方式取决于工艺条件,例如剪切变薄行为,这是由时间和温度相关的转化率叠加而成的,两者都强烈影响粘度。重点是在扇形晶圆级封装(FOWLP)封装期间施加在单个骰子上的力。提出的框架包括计算熔体前沿速度的分析方法和模拟,以捕获非线性运动学,化学流变学,并提取施加在单个骰子上的力。它提供了两种情况下的压力和剪切贡献的单独评估,骰子的锋面区域和熔体锋面之间的0°和45°。工艺参数,如压缩速度,因此循环时间和工艺温度,是确定的,以保持对骰子的力低于临界水平,其中阻力超过附着力。因此,确定工艺参数以尽量减少飞骰子,从而最大限度地提高产量。该方法很容易转移到任意几何形状,因此非常适合面对当前从FOWLP向更大基板过渡所带来的挑战。
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引用次数: 2
Year-long 500°C Operational Demonstration of Up-scaled 4H-SiC JFET Integrated Circuits 规模化4H-SiC JFET集成电路长达一年的500°C运行演示
Q4 Engineering Pub Date : 2018-10-01 DOI: 10.4071/IMAPS.729648
P. Neudeck, D. Spry, M. Krasowski, N. Prokop, G. Beheim, Liangyu Chen, Carl W. Chang
This work describes recent progress in the design, processing, and testing of significantly up-scaled complex 500°C–durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for more than 1 y at 500°C in an air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500°C–durable circuit complexity from the 24-transistor ring oscillator ICs reported at HiTEC 2016. These results advance the technology foundation for realizing long-term durable 500°C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.
这项工作描述了美国宇航局格伦研究中心正在开发的具有两级互连的大规模复杂500°c耐用4H-SiC结场效应晶体管(JFET)集成电路(IC)技术的设计、处理和测试的最新进展。首次报道了半导体集成电路在500°C的空气环境中稳定工作超过1年的情况。这些突破性的耐久性结果是在两级互连JFET演示ic上获得的,每个芯片上有175个或更多的晶体管。与2016年HiTEC报告的24晶体管环形振荡器ic相比,这相当于500°c耐用电路复杂性增加了7倍以上。这些成果为实现长期耐用的500°C集成电路奠定了技术基础,增强了内燃机传感和控制、行星勘探、深井钻井监测和其他恶劣环境应用的功能。
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引用次数: 24
Screen Printing Fine Pitch Stretchable Silver Inks onto a Flexible Substrate for Wearable Applications 丝网印刷细间距可拉伸银油墨到可穿戴应用的柔性基板上
Q4 Engineering Pub Date : 2018-10-01 DOI: 10.4071/2380-4505-2018.1.000665
Jianbiao Pan, Malcolm G. Keif, Joshua Ledgerwood, Xiaoying Rong, Xuan Wang
This article presents the development and optimization of the screen printing process for printing stretchable silver ink onto a stretchable thermoplastic polyurethane substrate. A test vehicle was designed including 50 μm/5 mm (line width/line length) to 350 μm/35 mm lines (at four biases). A two-level factorial design with three replicates was selected to investigate the effect of process parameters on the quality of prints. We proposed calculated sheet resistance based on the measured resistance value, trace width, and trace length, which can replace trace height measurements on rough profile substrates. We found that squeegee pressure and emulsion thickness have statistically significant effects on calculated sheet resistance of print traces, whereas print speed does not have statistically significant effects. In our experiment setting levels, the lower the squeegee pressure, the lower the calculated sheet resistance that is achieved. The emulsion with higher emulsion over mesh (EOM) is better than the emulsion with lower EOM because it can achieve lower sheet resistance. After optimizing the screen printing process, we were able to print 100 μm (4 mils) trace width and spacing with high consistency.
本文介绍了在可拉伸热塑性聚氨酯基材上印刷可拉伸银油墨的丝网印刷工艺的开发和优化。设计了一个测试车辆,包括50μm/5 mm(线宽/线路长度)至350μm/35 mm的线路(四个偏置)。选择三个重复的两级析因设计来研究工艺参数对印刷品质量的影响。我们提出了基于测量的电阻值、迹线宽度和迹线长度来计算薄层电阻,这可以取代粗糙轮廓衬底上的迹线高度测量。我们发现,刮板压力和乳液厚度对计算出的打印迹线的纸张阻力有统计学上的显著影响,而打印速度没有统计学上的明显影响。在我们的实验设置水平中,刮板压力越低,所获得的计算片材阻力就越低。具有较高网孔乳液(EOM)的乳液比具有较低EOM的乳液更好,因为它可以实现较低的薄层电阻。在优化丝网印刷工艺后,我们能够以高一致性印刷100μm(4密耳)的迹线宽度和间距。
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引用次数: 2
Design and Demonstration of Glass Panel Embedding for 3D System Packages for Heterogeneous Integration Applications 用于异构集成应用的3D系统包的玻璃板嵌入设计与演示
Q4 Engineering Pub Date : 2018-10-01 DOI: 10.4071/IMAPS.930748
Siddharth Ravichandran, Shuhei Yamada, T. Ogawa, Tailong Shi, Fuhan Liu, V. Smet, V. Sundaram, R. Tummala
This article demonstrates a next-generation high-performance 3D packaging technology with smaller form factor, excellent electrical performance, and reliability for heterogeneous integration. High-density logic-memory integration, today, is built predominantly using interposers which are fundamentally limited in assembly pitch and interconnect lengths, and they also are expensive as the package sizes increase. On the other hand, high-frequency applications continue to use laminates which are also limited by package size and ability to integrate many components. Wafer-level fan-out (WLFO) packaging promises better performance and form factor at lower costs, but current WLFO packages are mold-based and hence are limited to small packages. This article presents a 3D packaging technology using glass panel embedding (GPE) for high-performance with potential for large body size heterogeneous integration applications. The tailorable coefficient of thermal expansion of glass allows a reliable direct board attach of large GPE packages that not only benefits the form factor and signal speed but also provides radical benefits to power delivery. Unlike interposers and silicon bridges, GPE packages are not bump-limited and can support I/O densities comparable with backend-of-line with silicon-like redistribution wiring at much lower costs. The fundamental limitations such as die shift and poor dimensional stability of current organic WLFO packages are addressed by parametric process improvements to reduce die shift to <2 μm while also improving the RDL surface planarity for high-yielding fine-line structures and integrating through glass via (TGV) in the fan-out region for 3D packaging. This article describes the fabrication process for 3D GPE, leading to demonstration of a technology using embedding of chips with all-Cu interconnections at 40-μm I/O pitch with TGVs at 300-μm pitch, thus enabling double-side RDL and assembly of chips to achieve three levels of device integration.
本文展示了下一代高性能3D封装技术,该技术具有更小的外形尺寸、卓越的电气性能和异构集成的可靠性。目前,高密度逻辑存储器集成主要使用中间体,这些中间体在组装间距和互连长度方面受到限制,并且随着封装尺寸的增加,它们也很昂贵。另一方面,高频应用继续使用层压板,这也受到封装尺寸和集成许多组件的能力的限制。晶圆级扇出(WLFO)封装承诺以更低的成本获得更好的性能和外形尺寸,但目前的WLFO封装是基于模具的,因此仅限于小封装。本文介绍了一种使用玻璃面板嵌入(GPE)的高性能3D封装技术,具有大尺寸异构集成应用的潜力。可定制的玻璃热膨胀系数使大型GPE封装能够可靠地直接贴接在电路板上,这不仅有利于外形尺寸和信号速度,而且还为功率传输提供了根本的好处。与中间层和硅桥不同,GPE封装没有碰撞限制,并且可以以低得多的成本支持与具有类似硅的再分配布线的后端线路相当的I/O密度。通过参数化工艺改进,解决了当前有机WLFO封装的基本限制,如模移和尺寸稳定性差,以减少模移至<2 μm,同时还提高了高产量细线结构的RDL表面平面度,并在扇形区域通过玻璃通孔(TGV)集成,用于3D封装。本文介绍了3D GPE的制造工艺,并演示了一种技术,该技术使用40 μm I/O间距的全cu互连芯片嵌入300 μm间距的tgv,从而实现了双面RDL和芯片组装,从而实现了三个级别的器件集成。
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引用次数: 15
Characterization of Mechanical Properties and Creep Behavior of Woven Glass/Epoxy Substrates by Nanoindentation 纳米压痕法表征玻璃/环氧树脂基板的力学性能和蠕变行为
Q4 Engineering Pub Date : 2018-07-06 DOI: 10.4071/IMAPS.654387
Abel Misrak, L. Nguyen, S. Kummerl, D. Agonafer
Reliability is of a concern when designing new products. Extensive set of reliability tests are performed before a product is ready to be shipped for use. Drop testing, thermal cycling, power cycling, etc. are some of the tests used to assess the reliability of new electronic products. However, performing experimental study of every new design is costly and time consuming. Computational tools (such as finite element analysis software) are often employed to perform the required reliability analysis in a shorter time period and save valuable resources. One of the challenges of performing computational analysis is obtaining accurate material property data to be used for building accurate models. Extensive set of material characterization work needs to be carried out before an accurate model can be developed. For example, for a new printed circuit board (PCB), the bulk properties are often characterized by equipment such as thermomechanical analyzer and tensile testing machines to obtain the bulk properties t...
在设计新产品时,可靠性是一个需要考虑的问题。在产品准备发货使用之前,要执行大量的可靠性测试。跌落测试、热循环、功率循环等是评估新电子产品可靠性的一些测试。然而,对每一种新设计进行实验研究都是昂贵且耗时的。通常采用计算工具(如有限元分析软件)在较短的时间内完成所需的可靠性分析,节省宝贵的资源。执行计算分析的挑战之一是获得准确的材料性能数据,用于建立准确的模型。在开发准确的模型之前,需要进行大量的材料表征工作。例如,对于一个新的印刷电路板(PCB),通常通过诸如热力学分析仪和拉伸试验机等设备来表征其整体性能,以获得其整体性能。
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引用次数: 3
Equivalent Capacitance Approach to Calculate Effective Roughness Dielectric Parameters for Copper Foils on Printed Circuit Boards 计算印刷电路板上铜箔有效粗糙介电参数的等效电容法
Q4 Engineering Pub Date : 2018-07-06 DOI: 10.4071/IMAPS.654479
M. Koledintseva, T. Vincent
Effective roughness dielectric (ERD) is a homogeneous lossy dielectric layer of certain thickness with effective (averaged) dielectric parameters. The ERD layer is used to model copper foil roughness in printed circuit board interconnects by being placed on a smooth conductor surface to substitute an inhomogeneous transition layer between a conductor and laminate substrate dielectric. This work derives the ERD parameters based on the understanding that there is a gradual variation of concentration of metallic inclusions in the transition layer between the dielectric and foil. The gradual variation can be structured as thin layers that are obtained using the equivalent capacitance approach. The concentration profile is extracted from scanning electron microscopy or high-resolution optical microscopy. As the concentration of metallic particles increases along the axis normal to the laminate dielectric and foil boundary, two regions can be discerned: an insulating (prepercolation) region and a conducting (pe...
有效粗糙电介质(ERD)是一种具有一定厚度的均匀有损电介质层,具有有效(平均)电介质参数。ERD层用于模拟印刷电路板互连中的铜箔粗糙度,方法是将其放置在光滑的导体表面上,以替代导体和层压基板电介质之间的不均匀过渡层。这项工作基于对电介质和箔之间的过渡层中金属夹杂物浓度逐渐变化的理解来推导ERD参数。渐变可以被构造为使用等效电容方法获得的薄层。从扫描电子显微镜或高分辨率光学显微镜中提取浓度分布。随着金属颗粒浓度沿垂直于层压板电介质和箔边界的轴增加,可以区分两个区域:绝缘(预渗透)区域和导电(渗透)区域。。。
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引用次数: 1
Thermal Interface Materials and Cooling Technologies in Microelectronic Packaging—A Critical Review 微电子封装中的热界面材料与冷却技术综述
Q4 Engineering Pub Date : 2018-07-06 DOI: 10.4071/IMAPS.654289
D. P. Thanu, Boxiao Liu, M. Cartas
The ever increasing demand for fast computing has led to heterogeneous integration of packages as can be seen in the latest Xeon family segments in the market. Microprocessors are now adjacent to memory chips, transceivers, field-programmable gate arrays, and even other microprocessors within a single substrate. These complex designs have instigated an increase in cooling demand for microprocessors, and hence, there has been an increased focus within the semiconductor industry on developing advance thermal solutions. From the packaging level, thermal interface materials (TIMs) play a key role in thermally connecting various components within the package and helps reduce the thermal resistance between the die surfaces and integrated heat spreaders. From the system level, cooling technology is critical to attain the desired overall thermal dissipation and performance. In this review, progress made in the area of TIMs and system cooling solutions are presented. The focus is on the evolution of TIMs and cooli...
对快速计算的不断增长的需求导致了封装的异构集成,这在市场上最新的至强系列细分产品中可以看到。微处理器现在与存储芯片,收发器,现场可编程门阵列,甚至是单个衬底内的其他微处理器相邻。这些复杂的设计刺激了微处理器冷却需求的增加,因此,半导体行业越来越关注开发先进的热解决方案。从封装层面来看,热界面材料(TIMs)在热连接封装内的各种组件方面发挥着关键作用,并有助于减少模具表面和集成散热器之间的热阻。从系统层面来看,冷却技术对于实现理想的整体散热和性能至关重要。本文综述了在TIMs和系统冷却解决方案方面取得的进展。重点是TIMs和cooli的演变。
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引用次数: 0
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Journal of Microelectronics and Electronic Packaging
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