The Kirkendall void (KV) has been a well-known issue for long term reliability of semiconductor interconnects. KVs exist at the interfaces of Cu and Sn and the growing intermetallic compound (IMC) Cu6Sn5 at the initial stage, and a part of the IMC is converted to Cu3Sn when the environmental stress added. In this article, all the assembled packages pass the condition of unbiased long-term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000 h of high-temperature storage. A large numbers of KVs was observed after 200 cycles of temperature cycling. Various assembly structures were monitored, and various IMC thicknesses were concluded to be functions of stress test. Cu3Sn, Ni3Sn4, and Cu6Sn5 are not significantly affected by heat, but Ni3Sn4 grows steadily.
{"title":"FCCSP IMC Growth under Reliability Stress Following Automotive Standards","authors":"Wei-Wei Liu, Berdy Weng, J. Li, C. Yeh","doi":"10.4071/IMAPS.735545","DOIUrl":"https://doi.org/10.4071/IMAPS.735545","url":null,"abstract":"\u0000 The Kirkendall void (KV) has been a well-known issue for long term reliability of semiconductor interconnects. KVs exist at the interfaces of Cu and Sn and the growing intermetallic compound (IMC) Cu6Sn5 at the initial stage, and a part of the IMC is converted to Cu3Sn when the environmental stress added. In this article, all the assembled packages pass the condition of unbiased long-term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000 h of high-temperature storage. A large numbers of KVs was observed after 200 cycles of temperature cycling. Various assembly structures were monitored, and various IMC thicknesses were concluded to be functions of stress test. Cu3Sn, Ni3Sn4, and Cu6Sn5 are not significantly affected by heat, but Ni3Sn4 grows steadily.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44304395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The “head-in-pillow” (HnP) defects in lead-free solder joint interconnections of Integrated Circuit (IC) packages with conventional (small) standoff heights of the solder joints, and particularly in packages with fine pitches, are attributed by many electronic material scientists to the three major causes: attributes of the manufacturing process, solder material properties, and design-related issues. The latter are thought to be caused primarily by elevated stresses in the solder material, as well as by the excessive warpage of the Printed Circuit Board (PCB)-package assembly and particularly by the differences in the thermally induced curvatures of the PCB and the package. In this analysis, the stress and warpage issue is addressed using an analytical predictive stress model. The model is a modification and an extension of the model developed back in 1980s by the first author. It is assumed that it is the difference in the postfabrication deflections of the PCB-package assembly that is the root cause of the solder material failures and particularly and perhaps the HnP defects. The calculated data based on the developed stress model suggest that the replacement of the conventional ball grid array (BGA) designs with designs with elevated standoff heights of the solder joints could result in significant stress and warpage relief and, hopefully, in a lower propensity of the IC package to HnP defects as well. The general concepts are illustrated by a numerical example, in which the responses to the change in temperature of a conventional design, referred to as BGA, and a design with solder joints with elevated standoff heights, referred to as column grid array (CGA), are compared. The computed data indicated that the effective stress in the solder material was relieved by about 40% and the difference between the maximum deflections of the PCB and the package was reduced by about 60%, when the BGA design was replaced by a CGA system. Although no definite proof that the use of solder joints with elevated standoff heights will lessen the package propensity to the HnP defects is provided, the authors nonetheless think that there is a reason to believe that the application of solder joints with elevated standoff heights could result in a substantial improvement in the general IC package performance, including, perhaps, its propensity to HnP defects.
{"title":"Elevated Standoff Heights of Solder Joint Interconnections Can Result in Appreciable Stress and Warpage Relief","authors":"E. Suhir, S. Yi, Jennie S. Hwang, R. Ghaffarian","doi":"10.4071/IMAPS.735566","DOIUrl":"https://doi.org/10.4071/IMAPS.735566","url":null,"abstract":"The “head-in-pillow” (HnP) defects in lead-free solder joint interconnections of Integrated Circuit (IC) packages with conventional (small) standoff heights of the solder joints, and particularly in packages with fine pitches, are attributed by many electronic material scientists to the three major causes: attributes of the manufacturing process, solder material properties, and design-related issues. The latter are thought to be caused primarily by elevated stresses in the solder material, as well as by the excessive warpage of the Printed Circuit Board (PCB)-package assembly and particularly by the differences in the thermally induced curvatures of the PCB and the package. In this analysis, the stress and warpage issue is addressed using an analytical predictive stress model. The model is a modification and an extension of the model developed back in 1980s by the first author. It is assumed that it is the difference in the postfabrication deflections of the PCB-package assembly that is the root cause of the solder material failures and particularly and perhaps the HnP defects. The calculated data based on the developed stress model suggest that the replacement of the conventional ball grid array (BGA) designs with designs with elevated standoff heights of the solder joints could result in significant stress and warpage relief and, hopefully, in a lower propensity of the IC package to HnP defects as well. The general concepts are illustrated by a numerical example, in which the responses to the change in temperature of a conventional design, referred to as BGA, and a design with solder joints with elevated standoff heights, referred to as column grid array (CGA), are compared. The computed data indicated that the effective stress in the solder material was relieved by about 40% and the difference between the maximum deflections of the PCB and the package was reduced by about 60%, when the BGA design was replaced by a CGA system. Although no definite proof that the use of solder joints with elevated standoff heights will lessen the package propensity to the HnP defects is provided, the authors nonetheless think that there is a reason to believe that the application of solder joints with elevated standoff heights could result in a substantial improvement in the general IC package performance, including, perhaps, its propensity to HnP defects.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"49 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70531536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Daniela A. Torres, A. Kopa, S. Barron, R. McCormick, R. White, Caprice Gray
Low-impedance microcoaxial cables have been developed to supply power to microchips. These uniquely low-inductance cables are enabled by a very thin dielectric compared with a conventional 50-Ω cable. These cables will be used in a novel packaging platform in which traditional interconnects are replaced by microscale coaxial cables. This method saves time and cost for small production volumes and custom electronics, compared with high density interconnects and silicon interposer technologies. These microcoaxial cables are designed to have minimal impedance to meet the stringent power supply requirements of today's electronics. As a concrete example, we consider a Kintex 7 Field-Programmable Gate Array (FPGA). To power this chip with interconnect lengths of 25 mm and a voltage ripple less than 30 mV, a resistance of 3.20–6.40 mΩ/mm and an inductance of 12–15 pH/mm is needed. The tight voltage ripple constraint is what makes this device challenging to design power distribution for. One cable fabricated by Draper, to achieve these power requirements, is the focus of this article. The Draper cable consists of a 127-μm Copper core, 12-μm polyesterimide dielectric layer, and 55-μm gold shield. The measured resistance per unit length at DC, inductance per unit length, capacitance per unit length, and characteristic impedance of the Draper cable are 2.0 mΩ/mm, 40 pH/mm, 118 pF/mm, and 6.56 Ω, respectively.
{"title":"Characterization of Low-Inductance Microcoaxial Cables for Power Distribution","authors":"Daniela A. Torres, A. Kopa, S. Barron, R. McCormick, R. White, Caprice Gray","doi":"10.4071/IMAPS.729301","DOIUrl":"https://doi.org/10.4071/IMAPS.729301","url":null,"abstract":"Low-impedance microcoaxial cables have been developed to supply power to microchips. These uniquely low-inductance cables are enabled by a very thin dielectric compared with a conventional 50-Ω cable. These cables will be used in a novel packaging platform in which traditional interconnects are replaced by microscale coaxial cables. This method saves time and cost for small production volumes and custom electronics, compared with high density interconnects and silicon interposer technologies. These microcoaxial cables are designed to have minimal impedance to meet the stringent power supply requirements of today's electronics. As a concrete example, we consider a Kintex 7 Field-Programmable Gate Array (FPGA). To power this chip with interconnect lengths of 25 mm and a voltage ripple less than 30 mV, a resistance of 3.20–6.40 mΩ/mm and an inductance of 12–15 pH/mm is needed. The tight voltage ripple constraint is what makes this device challenging to design power distribution for. One cable fabricated by Draper, to achieve these power requirements, is the focus of this article. The Draper cable consists of a 127-μm Copper core, 12-μm polyesterimide dielectric layer, and 55-μm gold shield. The measured resistance per unit length at DC, inductance per unit length, capacitance per unit length, and characteristic impedance of the Draper cable are 2.0 mΩ/mm, 40 pH/mm, 118 pF/mm, and 6.56 Ω, respectively.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44045270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.4071/2380-4505-2018.1.000355
M. Dreissigacker, O. Hoelck, J. Bauer, T. Braun, K. Becker, M. Schneider-Ramelow, K. Lang
Compression molding with liquid encapsulants is a crucial process in microelectronic packaging. Material properties of highly filled systems of reactive epoxy molding compounds depend on process conditions in a complex manner, such as shear-thinning behavior, which is superimposed by a time- and temperature-dependent conversion rate, both strongly affecting viscosity. The focus is set on forces exerted on individual dice during encapsulation in fan-out wafer-level packaging (FOWLP). The presented framework consists of an analytical approach to calculate the melt front velocity and simulations carried out to capture the nonlinear kinematics, chemorheology, and to extract forces exerted on individual dice. It offers separate evaluation of pressure and shear contributions for two cases, 0° and 45° between the dice' frontal area and the melt front. Process parameters, such as compression speed, thus cycle time, and process temperature, are determined to keep the forces on the dice below the critical level, where drag forces exceed adhesive forces. As a result, process parameters are determined to minimize flying dice and thereby maximize yield. The approach is easily transferable to arbitrary geometries and is therefore well suited to face the challenges that come with the current efforts toward the transition from FOWLP to larger substrates.
{"title":"A Numerical Study on Mitigation of Flying Dies in Compression Molding of Microelectronic Packages","authors":"M. Dreissigacker, O. Hoelck, J. Bauer, T. Braun, K. Becker, M. Schneider-Ramelow, K. Lang","doi":"10.4071/2380-4505-2018.1.000355","DOIUrl":"https://doi.org/10.4071/2380-4505-2018.1.000355","url":null,"abstract":"\u0000 Compression molding with liquid encapsulants is a crucial process in microelectronic packaging. Material properties of highly filled systems of reactive epoxy molding compounds depend on process conditions in a complex manner, such as shear-thinning behavior, which is superimposed by a time- and temperature-dependent conversion rate, both strongly affecting viscosity. The focus is set on forces exerted on individual dice during encapsulation in fan-out wafer-level packaging (FOWLP). The presented framework consists of an analytical approach to calculate the melt front velocity and simulations carried out to capture the nonlinear kinematics, chemorheology, and to extract forces exerted on individual dice. It offers separate evaluation of pressure and shear contributions for two cases, 0° and 45° between the dice' frontal area and the melt front. Process parameters, such as compression speed, thus cycle time, and process temperature, are determined to keep the forces on the dice below the critical level, where drag forces exceed adhesive forces. As a result, process parameters are determined to minimize flying dice and thereby maximize yield. The approach is easily transferable to arbitrary geometries and is therefore well suited to face the challenges that come with the current efforts toward the transition from FOWLP to larger substrates.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42448005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Neudeck, D. Spry, M. Krasowski, N. Prokop, G. Beheim, Liangyu Chen, Carl W. Chang
This work describes recent progress in the design, processing, and testing of significantly up-scaled complex 500°C–durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for more than 1 y at 500°C in an air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500°C–durable circuit complexity from the 24-transistor ring oscillator ICs reported at HiTEC 2016. These results advance the technology foundation for realizing long-term durable 500°C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.
{"title":"Year-long 500°C Operational Demonstration of Up-scaled 4H-SiC JFET Integrated Circuits","authors":"P. Neudeck, D. Spry, M. Krasowski, N. Prokop, G. Beheim, Liangyu Chen, Carl W. Chang","doi":"10.4071/IMAPS.729648","DOIUrl":"https://doi.org/10.4071/IMAPS.729648","url":null,"abstract":"\u0000 This work describes recent progress in the design, processing, and testing of significantly up-scaled complex 500°C–durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for more than 1 y at 500°C in an air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500°C–durable circuit complexity from the 24-transistor ring oscillator ICs reported at HiTEC 2016. These results advance the technology foundation for realizing long-term durable 500°C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47704420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.4071/2380-4505-2018.1.000665
Jianbiao Pan, Malcolm G. Keif, Joshua Ledgerwood, Xiaoying Rong, Xuan Wang
This article presents the development and optimization of the screen printing process for printing stretchable silver ink onto a stretchable thermoplastic polyurethane substrate. A test vehicle was designed including 50 μm/5 mm (line width/line length) to 350 μm/35 mm lines (at four biases). A two-level factorial design with three replicates was selected to investigate the effect of process parameters on the quality of prints. We proposed calculated sheet resistance based on the measured resistance value, trace width, and trace length, which can replace trace height measurements on rough profile substrates. We found that squeegee pressure and emulsion thickness have statistically significant effects on calculated sheet resistance of print traces, whereas print speed does not have statistically significant effects. In our experiment setting levels, the lower the squeegee pressure, the lower the calculated sheet resistance that is achieved. The emulsion with higher emulsion over mesh (EOM) is better than the emulsion with lower EOM because it can achieve lower sheet resistance. After optimizing the screen printing process, we were able to print 100 μm (4 mils) trace width and spacing with high consistency.
{"title":"Screen Printing Fine Pitch Stretchable Silver Inks onto a Flexible Substrate for Wearable Applications","authors":"Jianbiao Pan, Malcolm G. Keif, Joshua Ledgerwood, Xiaoying Rong, Xuan Wang","doi":"10.4071/2380-4505-2018.1.000665","DOIUrl":"https://doi.org/10.4071/2380-4505-2018.1.000665","url":null,"abstract":"\u0000 This article presents the development and optimization of the screen printing process for printing stretchable silver ink onto a stretchable thermoplastic polyurethane substrate. A test vehicle was designed including 50 μm/5 mm (line width/line length) to 350 μm/35 mm lines (at four biases). A two-level factorial design with three replicates was selected to investigate the effect of process parameters on the quality of prints. We proposed calculated sheet resistance based on the measured resistance value, trace width, and trace length, which can replace trace height measurements on rough profile substrates. We found that squeegee pressure and emulsion thickness have statistically significant effects on calculated sheet resistance of print traces, whereas print speed does not have statistically significant effects. In our experiment setting levels, the lower the squeegee pressure, the lower the calculated sheet resistance that is achieved. The emulsion with higher emulsion over mesh (EOM) is better than the emulsion with lower EOM because it can achieve lower sheet resistance. After optimizing the screen printing process, we were able to print 100 μm (4 mils) trace width and spacing with high consistency.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48205576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Siddharth Ravichandran, Shuhei Yamada, T. Ogawa, Tailong Shi, Fuhan Liu, V. Smet, V. Sundaram, R. Tummala
This article demonstrates a next-generation high-performance 3D packaging technology with smaller form factor, excellent electrical performance, and reliability for heterogeneous integration. High-density logic-memory integration, today, is built predominantly using interposers which are fundamentally limited in assembly pitch and interconnect lengths, and they also are expensive as the package sizes increase. On the other hand, high-frequency applications continue to use laminates which are also limited by package size and ability to integrate many components. Wafer-level fan-out (WLFO) packaging promises better performance and form factor at lower costs, but current WLFO packages are mold-based and hence are limited to small packages. This article presents a 3D packaging technology using glass panel embedding (GPE) for high-performance with potential for large body size heterogeneous integration applications. The tailorable coefficient of thermal expansion of glass allows a reliable direct board attach of large GPE packages that not only benefits the form factor and signal speed but also provides radical benefits to power delivery. Unlike interposers and silicon bridges, GPE packages are not bump-limited and can support I/O densities comparable with backend-of-line with silicon-like redistribution wiring at much lower costs. The fundamental limitations such as die shift and poor dimensional stability of current organic WLFO packages are addressed by parametric process improvements to reduce die shift to <2 μm while also improving the RDL surface planarity for high-yielding fine-line structures and integrating through glass via (TGV) in the fan-out region for 3D packaging. This article describes the fabrication process for 3D GPE, leading to demonstration of a technology using embedding of chips with all-Cu interconnections at 40-μm I/O pitch with TGVs at 300-μm pitch, thus enabling double-side RDL and assembly of chips to achieve three levels of device integration.
{"title":"Design and Demonstration of Glass Panel Embedding for 3D System Packages for Heterogeneous Integration Applications","authors":"Siddharth Ravichandran, Shuhei Yamada, T. Ogawa, Tailong Shi, Fuhan Liu, V. Smet, V. Sundaram, R. Tummala","doi":"10.4071/IMAPS.930748","DOIUrl":"https://doi.org/10.4071/IMAPS.930748","url":null,"abstract":"\u0000 This article demonstrates a next-generation high-performance 3D packaging technology with smaller form factor, excellent electrical performance, and reliability for heterogeneous integration. High-density logic-memory integration, today, is built predominantly using interposers which are fundamentally limited in assembly pitch and interconnect lengths, and they also are expensive as the package sizes increase. On the other hand, high-frequency applications continue to use laminates which are also limited by package size and ability to integrate many components. Wafer-level fan-out (WLFO) packaging promises better performance and form factor at lower costs, but current WLFO packages are mold-based and hence are limited to small packages. This article presents a 3D packaging technology using glass panel embedding (GPE) for high-performance with potential for large body size heterogeneous integration applications. The tailorable coefficient of thermal expansion of glass allows a reliable direct board attach of large GPE packages that not only benefits the form factor and signal speed but also provides radical benefits to power delivery. Unlike interposers and silicon bridges, GPE packages are not bump-limited and can support I/O densities comparable with backend-of-line with silicon-like redistribution wiring at much lower costs. The fundamental limitations such as die shift and poor dimensional stability of current organic WLFO packages are addressed by parametric process improvements to reduce die shift to <2 μm while also improving the RDL surface planarity for high-yielding fine-line structures and integrating through glass via (TGV) in the fan-out region for 3D packaging. This article describes the fabrication process for 3D GPE, leading to demonstration of a technology using embedding of chips with all-Cu interconnections at 40-μm I/O pitch with TGVs at 300-μm pitch, thus enabling double-side RDL and assembly of chips to achieve three levels of device integration.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46254304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Reliability is of a concern when designing new products. Extensive set of reliability tests are performed before a product is ready to be shipped for use. Drop testing, thermal cycling, power cycling, etc. are some of the tests used to assess the reliability of new electronic products. However, performing experimental study of every new design is costly and time consuming. Computational tools (such as finite element analysis software) are often employed to perform the required reliability analysis in a shorter time period and save valuable resources. One of the challenges of performing computational analysis is obtaining accurate material property data to be used for building accurate models. Extensive set of material characterization work needs to be carried out before an accurate model can be developed. For example, for a new printed circuit board (PCB), the bulk properties are often characterized by equipment such as thermomechanical analyzer and tensile testing machines to obtain the bulk properties t...
{"title":"Characterization of Mechanical Properties and Creep Behavior of Woven Glass/Epoxy Substrates by Nanoindentation","authors":"Abel Misrak, L. Nguyen, S. Kummerl, D. Agonafer","doi":"10.4071/IMAPS.654387","DOIUrl":"https://doi.org/10.4071/IMAPS.654387","url":null,"abstract":"Reliability is of a concern when designing new products. Extensive set of reliability tests are performed before a product is ready to be shipped for use. Drop testing, thermal cycling, power cycling, etc. are some of the tests used to assess the reliability of new electronic products. However, performing experimental study of every new design is costly and time consuming. Computational tools (such as finite element analysis software) are often employed to perform the required reliability analysis in a shorter time period and save valuable resources. One of the challenges of performing computational analysis is obtaining accurate material property data to be used for building accurate models. Extensive set of material characterization work needs to be carried out before an accurate model can be developed. For example, for a new printed circuit board (PCB), the bulk properties are often characterized by equipment such as thermomechanical analyzer and tensile testing machines to obtain the bulk properties t...","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"15 1","pages":"95-100"},"PeriodicalIF":0.0,"publicationDate":"2018-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43086802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Effective roughness dielectric (ERD) is a homogeneous lossy dielectric layer of certain thickness with effective (averaged) dielectric parameters. The ERD layer is used to model copper foil roughness in printed circuit board interconnects by being placed on a smooth conductor surface to substitute an inhomogeneous transition layer between a conductor and laminate substrate dielectric. This work derives the ERD parameters based on the understanding that there is a gradual variation of concentration of metallic inclusions in the transition layer between the dielectric and foil. The gradual variation can be structured as thin layers that are obtained using the equivalent capacitance approach. The concentration profile is extracted from scanning electron microscopy or high-resolution optical microscopy. As the concentration of metallic particles increases along the axis normal to the laminate dielectric and foil boundary, two regions can be discerned: an insulating (prepercolation) region and a conducting (pe...
{"title":"Equivalent Capacitance Approach to Calculate Effective Roughness Dielectric Parameters for Copper Foils on Printed Circuit Boards","authors":"M. Koledintseva, T. Vincent","doi":"10.4071/IMAPS.654479","DOIUrl":"https://doi.org/10.4071/IMAPS.654479","url":null,"abstract":"Effective roughness dielectric (ERD) is a homogeneous lossy dielectric layer of certain thickness with effective (averaged) dielectric parameters. The ERD layer is used to model copper foil roughness in printed circuit board interconnects by being placed on a smooth conductor surface to substitute an inhomogeneous transition layer between a conductor and laminate substrate dielectric. This work derives the ERD parameters based on the understanding that there is a gradual variation of concentration of metallic inclusions in the transition layer between the dielectric and foil. The gradual variation can be structured as thin layers that are obtained using the equivalent capacitance approach. The concentration profile is extracted from scanning electron microscopy or high-resolution optical microscopy. As the concentration of metallic particles increases along the axis normal to the laminate dielectric and foil boundary, two regions can be discerned: an insulating (prepercolation) region and a conducting (pe...","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"15 1","pages":"49-62"},"PeriodicalIF":0.0,"publicationDate":"2018-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46799432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The ever increasing demand for fast computing has led to heterogeneous integration of packages as can be seen in the latest Xeon family segments in the market. Microprocessors are now adjacent to memory chips, transceivers, field-programmable gate arrays, and even other microprocessors within a single substrate. These complex designs have instigated an increase in cooling demand for microprocessors, and hence, there has been an increased focus within the semiconductor industry on developing advance thermal solutions. From the packaging level, thermal interface materials (TIMs) play a key role in thermally connecting various components within the package and helps reduce the thermal resistance between the die surfaces and integrated heat spreaders. From the system level, cooling technology is critical to attain the desired overall thermal dissipation and performance. In this review, progress made in the area of TIMs and system cooling solutions are presented. The focus is on the evolution of TIMs and cooli...
{"title":"Thermal Interface Materials and Cooling Technologies in Microelectronic Packaging—A Critical Review","authors":"D. P. Thanu, Boxiao Liu, M. Cartas","doi":"10.4071/IMAPS.654289","DOIUrl":"https://doi.org/10.4071/IMAPS.654289","url":null,"abstract":"The ever increasing demand for fast computing has led to heterogeneous integration of packages as can be seen in the latest Xeon family segments in the market. Microprocessors are now adjacent to memory chips, transceivers, field-programmable gate arrays, and even other microprocessors within a single substrate. These complex designs have instigated an increase in cooling demand for microprocessors, and hence, there has been an increased focus within the semiconductor industry on developing advance thermal solutions. From the packaging level, thermal interface materials (TIMs) play a key role in thermally connecting various components within the package and helps reduce the thermal resistance between the die surfaces and integrated heat spreaders. From the system level, cooling technology is critical to attain the desired overall thermal dissipation and performance. In this review, progress made in the area of TIMs and system cooling solutions are presented. The focus is on the evolution of TIMs and cooli...","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"15 1","pages":"63-74"},"PeriodicalIF":0.0,"publicationDate":"2018-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44644676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}