Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753560
C. Murphy
A Monte Carlo simulation model was developed for examining the cost of Known Good Die (KGD) relative to packaged parts, with a focus on identifying the dominant cost drivers. The cost of KGD and packaged devices that go through test and burn-in are studied by varying these key drivers and examining their sensitivities. The model is capable of manipulating IC fab parameters (e.g., defect density, sort coverage, etc.), as well as packaging, test, and burn-in costs. In determining relative costs, an important consideration is the package type to which KGD is being compared (plastic vs. ceramic). The key cost drivers are number of KGD carrier uses, complexity of the IC, cost of the carrier, number of burn-in hours, and KGD assembly/disassembly time.
{"title":"Known Good Die Selection Tradeoffs: A Cost Model","authors":"C. Murphy","doi":"10.1109/ICMCM.1994.753560","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753560","url":null,"abstract":"A Monte Carlo simulation model was developed for examining the cost of Known Good Die (KGD) relative to packaged parts, with a focus on identifying the dominant cost drivers. The cost of KGD and packaged devices that go through test and burn-in are studied by varying these key drivers and examining their sensitivities. The model is capable of manipulating IC fab parameters (e.g., defect density, sort coverage, etc.), as well as packaging, test, and burn-in costs. In determining relative costs, an important consideration is the package type to which KGD is being compared (plastic vs. ceramic). The key cost drivers are number of KGD carrier uses, complexity of the IC, cost of the carrier, number of burn-in hours, and KGD assembly/disassembly time.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129864033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753589
P. Clot, P. Sarbach, D. Styblo
Multi-Chip-Module on a laminated epoxy-glass substrate (MCM-L) meets the demand for a low cost miniaturized module when many functions with different technologies need to be integrated in a single standard package. The following paper presents two original MCM-L designs using Chip On Board (COB) technology. Both are made on the same kind of modified multilayer glass epoxy ; one is equiped with J lead ouput pins allowing the mounting of dice on both faces, the second is very thin with dice mounted on the top face and bumps on the bottom face allowing direct soldering on the motherboard like other Surface Mount Device (SMD) components. These two kinds of MCM modules with Jedec standard dimensions are now pushed into production. Mounting procedure as well as qualification program and test approach are described. To ensure reliability of such MCMs it becomes important to know exactly the maximal stress and deformation induced by thermal or mechanical cycles during mounting procedure. The use of the Finite Element Method (FEM) for design optimization is explained. This method allows the calculation of deformation, stress and temperature distribution in the whole module during the development phase. The results of such simulation are presented here.
{"title":"Chip on Board Technology for Low Cost Multi-Chip-Modules","authors":"P. Clot, P. Sarbach, D. Styblo","doi":"10.1109/ICMCM.1994.753589","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753589","url":null,"abstract":"Multi-Chip-Module on a laminated epoxy-glass substrate (MCM-L) meets the demand for a low cost miniaturized module when many functions with different technologies need to be integrated in a single standard package. The following paper presents two original MCM-L designs using Chip On Board (COB) technology. Both are made on the same kind of modified multilayer glass epoxy ; one is equiped with J lead ouput pins allowing the mounting of dice on both faces, the second is very thin with dice mounted on the top face and bumps on the bottom face allowing direct soldering on the motherboard like other Surface Mount Device (SMD) components. These two kinds of MCM modules with Jedec standard dimensions are now pushed into production. Mounting procedure as well as qualification program and test approach are described. To ensure reliability of such MCMs it becomes important to know exactly the maximal stress and deformation induced by thermal or mechanical cycles during mounting procedure. The use of the Finite Element Method (FEM) for design optimization is explained. This method allows the calculation of deformation, stress and temperature distribution in the whole module during the development phase. The results of such simulation are presented here.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127592692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753596
R. Kuntz, S. Williams
Interconnection of multichip modules to their next higher assembly (normally a printed wiring board) has the same set of problems the industry has always had to manage, however, some of the problems have been exacerbated in today's applications. Performance requirements are getting tighter as modules now operate at 100 megahertz and up. With an increasing size of the modules, the mismatch in the thermal coefficient of expansion (TCE) between the module and the printed wiring board induces more stress. This manifests itself in reliability problems '%" the module has soldered terminations.
{"title":"Array Module Connector Test Program at Unisys","authors":"R. Kuntz, S. Williams","doi":"10.1109/ICMCM.1994.753596","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753596","url":null,"abstract":"Interconnection of multichip modules to their next higher assembly (normally a printed wiring board) has the same set of problems the industry has always had to manage, however, some of the problems have been exacerbated in today's applications. Performance requirements are getting tighter as modules now operate at 100 megahertz and up. With an increasing size of the modules, the mismatch in the thermal coefficient of expansion (TCE) between the module and the printed wiring board induces more stress. This manifests itself in reliability problems '%\" the module has soldered terminations.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121973883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753585
H. Anderson
Conventional package design of integrated circuit packages utilizes only one side of the package substrate. The MCM-L package with it's multi-laminate PC-board structure provides a rigidity to the substrate for assembly such that assembly may be performed on both sides of the package. The dual-sided MCM-L package with active chips attached to both sides of the substrate makes more effective use of substrate surface area. The same or similar chip set (combination of ASIC and memory chips) used in a 40mm package with assembly on one side, may be placed onto a dual-sided MCM-L substrate with a 28mm package size. The tooling used is designed to allow for re- insertion of the package into the bonder work holder bond site without damage to previous assembly. The tooling for processing a rigid substrate dual-sided MCM-L package differs from that of the conventional tooling set, and accomplishes two major goals. One, it provides a relief area for previous assembly to prevent physical damage to chips and wires, and heats the package area beneath the cavity to bond temperatures for fully automatic wire bonding.
{"title":"Wire Bonding Dual-Sided Mcma Modules","authors":"H. Anderson","doi":"10.1109/ICMCM.1994.753585","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753585","url":null,"abstract":"Conventional package design of integrated circuit packages utilizes only one side of the package substrate. The MCM-L package with it's multi-laminate PC-board structure provides a rigidity to the substrate for assembly such that assembly may be performed on both sides of the package. The dual-sided MCM-L package with active chips attached to both sides of the substrate makes more effective use of substrate surface area. The same or similar chip set (combination of ASIC and memory chips) used in a 40mm package with assembly on one side, may be placed onto a dual-sided MCM-L substrate with a 28mm package size. The tooling used is designed to allow for re- insertion of the package into the bonder work holder bond site without damage to previous assembly. The tooling for processing a rigid substrate dual-sided MCM-L package differs from that of the conventional tooling set, and accomplishes two major goals. One, it provides a relief area for previous assembly to prevent physical damage to chips and wires, and heats the package area beneath the cavity to bond temperatures for fully automatic wire bonding.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122968792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753600
T. Buck, M. Motazedi, G. Messner
After the decision is made to use MCM's in an electronic system, and the specific MCM technology is selected, there still remains the problem of their termination to the next level of packaging, where advanced techniques will be required to fabricate the interconnecting mother board. This paper will describe the design of a very compact mother board interconnecting 9 MCM-C's and all the necessary I/O terminations to the rest of the system within 5" by 5.5" usable area of a standard SEM-E format. The mother board uses MiCroWire/sup TM/ interconnection technology and is less than 0.060" thick, containing 4065 gold plated pads for MCM and connector interconnections, with a density of 148 pads/ in^2. MCM terminations are formed with a body centered 0.100" Land Grid Aray pattern (LGA). For this military computer system, a Solder Free Interconnection/sup TM/ (SFI) method is used between MCM's and the mother board in order to facilitate removal and replacement of MCM's in the field with a minimum loss of time and effort.
{"title":"Construction of Mother Boards Interconnecting Mcm's","authors":"T. Buck, M. Motazedi, G. Messner","doi":"10.1109/ICMCM.1994.753600","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753600","url":null,"abstract":"After the decision is made to use MCM's in an electronic system, and the specific MCM technology is selected, there still remains the problem of their termination to the next level of packaging, where advanced techniques will be required to fabricate the interconnecting mother board. This paper will describe the design of a very compact mother board interconnecting 9 MCM-C's and all the necessary I/O terminations to the rest of the system within 5\" by 5.5\" usable area of a standard SEM-E format. The mother board uses MiCroWire/sup TM/ interconnection technology and is less than 0.060\" thick, containing 4065 gold plated pads for MCM and connector interconnections, with a density of 148 pads/ in^2. MCM terminations are formed with a body centered 0.100\" Land Grid Aray pattern (LGA). For this military computer system, a Solder Free Interconnection/sup TM/ (SFI) method is used between MCM's and the mother board in order to facilitate removal and replacement of MCM's in the field with a minimum loss of time and effort.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"37 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125734674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753533
D. Palmer, W. Worobey
Considerable manufacturing development is currently aimed at reducing high density Multichip Module (MCM) cost through the use of large panels ( >40 cm x 40 cm) to fabricate many interconnection substrates in parallel. This drive for low cost MCM manufacturing is aided by the growing base of similar panel technology for the Printed Wiring Board (PWB) and Flat Panel display industries. It is toward this experience that the infant large panel MCM efforts are looking. In particular, the MCM Consortium formed by the Electronic Industry Association (EIA) and funded under the federal TRP effort is charged with developing a line of equipment optimized for large panel, fine line manufacture. PWB line definition research into large panels of glass and smooth non-woven laminate at 2-4 mil lines and spaces reveals that present equipment and processes are extendible well beyond commercial PWB product. In contrast, the ultra-cleanliness and spin coating of the silicon integrated circuit technology prove too expensive when scaled from 150mm diameter wafers to 560mm panels. Thus low waste photoresist (and other polymer dielectrics) application methods are needed for large panel manufacture. Similarly, PWB contact photomasking is nearing limits at 2-4 mil feature size, and projection or maskless direct write processes may be needed. Even small hand-held flat panel displays are manufactured from large panels to reduce the cost per display for conductive and dielectric layer deposition and patterning. In addition, as low cost flat displays become larger and improve in resolution, the line pitch and density approach that needed in high density MCMs.
目前相当大的制造发展旨在通过使用大型面板(bbb40 cm x 40 cm)来并联制造许多互连基板，从而降低高密度多芯片模块(MCM)的成本。这种低成本MCM制造的驱动是由印刷线路板(PWB)和平板显示行业的类似面板技术的不断增长的基础所辅助的。这是面向这种经验，婴儿大面板MCM的努力正在寻找。特别是，由电子工业协会(EIA)组建并由联邦TRP资助的MCM联盟负责开发针对大型面板，细线制造优化的一系列设备。对大型玻璃板和光滑无纺布层压板在2-4米线和空间的线条定义研究表明，目前的设备和工艺远远超出了商业PWB产品的扩展范围。相比之下，当从150mm直径的晶圆扩展到560mm的面板时，硅集成电路技术的超清洁度和旋转涂层被证明过于昂贵。因此，大型面板制造需要低浪费光刻胶(和其他聚合物介电材料)的应用方法。同样，印制板接触掩模在2-4 mil特征尺寸上接近极限，可能需要投影或无掩模直接写入过程。即使是小型手持平板显示器也是由大型面板制造的，以降低每个显示器的导电和介电层沉积和图案的成本。此外，随着低成本平板显示器变得更大，分辨率提高，线间距和密度接近高密度mcm所需。
{"title":"From Display and Pwb to Mcms: Large Panel Manufacturing","authors":"D. Palmer, W. Worobey","doi":"10.1109/ICMCM.1994.753533","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753533","url":null,"abstract":"Considerable manufacturing development is currently aimed at reducing high density Multichip Module (MCM) cost through the use of large panels ( >40 cm x 40 cm) to fabricate many interconnection substrates in parallel. This drive for low cost MCM manufacturing is aided by the growing base of similar panel technology for the Printed Wiring Board (PWB) and Flat Panel display industries. It is toward this experience that the infant large panel MCM efforts are looking. In particular, the MCM Consortium formed by the Electronic Industry Association (EIA) and funded under the federal TRP effort is charged with developing a line of equipment optimized for large panel, fine line manufacture. PWB line definition research into large panels of glass and smooth non-woven laminate at 2-4 mil lines and spaces reveals that present equipment and processes are extendible well beyond commercial PWB product. In contrast, the ultra-cleanliness and spin coating of the silicon integrated circuit technology prove too expensive when scaled from 150mm diameter wafers to 560mm panels. Thus low waste photoresist (and other polymer dielectrics) application methods are needed for large panel manufacture. Similarly, PWB contact photomasking is nearing limits at 2-4 mil feature size, and projection or maskless direct write processes may be needed. Even small hand-held flat panel displays are manufactured from large panels to reduce the cost per display for conductive and dielectric layer deposition and patterning. In addition, as low cost flat displays become larger and improve in resolution, the line pitch and density approach that needed in high density MCMs.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125143441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753525
S. Lindsey, B. Williams, B. Vasquez, B. Altuna, D. Vanoverloop, S. Walker
Die-Level-Bum-In (DLBI) approaches based on temporary bare die carriers are emerging in the industry as a practical, near-term solution for the production of known-good-die requiring bum-in. The goal for carrier development for test and burn-in is a cost-effective, bare die contact and. fixturing approach for both peripheral and array contacts as well as wire bond and bumped die. We are using both an FSRAM and a DRAM die to evaluate two bare die carrier technologies. The carriers differ in the type of bump used to contact the die ("piercing" vs. "burnishing" contacts) and in the design of the fixture used to hold the die in contact with the carrier. Mechanical evaluations include measurements of critical carrier features such as bump height, die alignment guide and aluminum bond pad damage caused by the carrier contacts. Contact integrity and the impact of bare-die test and burn-in on subsequent wirebond strength is being evaluated. Functionality of both carrier designs has been demonstrated by successful memory burn-in and at-speed test for both die types.
{"title":"Comparison of Two Temporary Carriers for Test and Burn-In of Memory Die","authors":"S. Lindsey, B. Williams, B. Vasquez, B. Altuna, D. Vanoverloop, S. Walker","doi":"10.1109/ICMCM.1994.753525","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753525","url":null,"abstract":"Die-Level-Bum-In (DLBI) approaches based on temporary bare die carriers are emerging in the industry as a practical, near-term solution for the production of known-good-die requiring bum-in. The goal for carrier development for test and burn-in is a cost-effective, bare die contact and. fixturing approach for both peripheral and array contacts as well as wire bond and bumped die. We are using both an FSRAM and a DRAM die to evaluate two bare die carrier technologies. The carriers differ in the type of bump used to contact the die (\"piercing\" vs. \"burnishing\" contacts) and in the design of the fixture used to hold the die in contact with the carrier. Mechanical evaluations include measurements of critical carrier features such as bump height, die alignment guide and aluminum bond pad damage caused by the carrier contacts. Contact integrity and the impact of bare-die test and burn-in on subsequent wirebond strength is being evaluated. Functionality of both carrier designs has been demonstrated by successful memory burn-in and at-speed test for both die types.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"74 5S 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132543876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753595
R. Miracky, T. Hirsch, T. Rudwick, S. Sommerfeldt
We have successfully fabricated and assembled a MCM-D prototype of the Sun SuperSPARC ("Viking") chipset, consisting of CPU, cache controller, and eight SRAM mounted on a 1.9"x1.9" copper-polyimide substrate. What makes this accomplishment interesting is that the total elapsed period (from the day the implementation go-ahead was received until the day the prototype assembly was complete) was two weeks. The prototyping sequence which was followed during the two weeks included the following individual steps: MCM design (including die placement, interconnect net routing, and connectivity check), substrate customization, shorts/opens testing, die procurement, wafer sawing, die attach (including discrete resistors and capacitors, as well as the integrated circuits), die wirebonding, and assembly of the MCM into a perimeter-leaded ceramic package.
{"title":"Mcm-D Prototype of the Supersparc Chipset in Two Weeks","authors":"R. Miracky, T. Hirsch, T. Rudwick, S. Sommerfeldt","doi":"10.1109/ICMCM.1994.753595","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753595","url":null,"abstract":"We have successfully fabricated and assembled a MCM-D prototype of the Sun SuperSPARC (\"Viking\") chipset, consisting of CPU, cache controller, and eight SRAM mounted on a 1.9\"x1.9\" copper-polyimide substrate. What makes this accomplishment interesting is that the total elapsed period (from the day the implementation go-ahead was received until the day the prototype assembly was complete) was two weeks. The prototyping sequence which was followed during the two weeks included the following individual steps: MCM design (including die placement, interconnect net routing, and connectivity check), substrate customization, shorts/opens testing, die procurement, wafer sawing, die attach (including discrete resistors and capacitors, as well as the integrated circuits), die wirebonding, and assembly of the MCM into a perimeter-leaded ceramic package.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"522 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132689641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753606
Qiong Yu, B. Sandeep, N. Sherwani
Physical design is currently a bottleneck in widespread use of MCMs. In particular, routing of a complex MCM while satisfying several performance, electrical and manufacturing constraints is a challenging problem. A router for thick film MCMs is presented in this paper. This will router partitions the whole MCM routing space into a set of small towers and decompose the routing process into three phases, viz, routing distribution, terminal assignment, and tower routing. The router has three fundamental features. First, it maintains the 3-dimensional characteristics of the original problem while partitioning it into several smaller problems and as a result, it can achieve the best utilization of the routing space. Second, it is designed to meet the constraints of net-length, path-separation, parallel-path-length, and the number of stacked vias and thus can satisfy the design requirement of high performance MCMs. Finally, the approach is amiable to parallel processing which can be used to improve the time complexity and memory constraints in a parallel computing environment. Experimental evaluation confirms the validity of our approach.
{"title":"CD3D: A Constraint-driven 3-dimensional Router for Thick Film Mcms","authors":"Qiong Yu, B. Sandeep, N. Sherwani","doi":"10.1109/ICMCM.1994.753606","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753606","url":null,"abstract":"Physical design is currently a bottleneck in widespread use of MCMs. In particular, routing of a complex MCM while satisfying several performance, electrical and manufacturing constraints is a challenging problem. A router for thick film MCMs is presented in this paper. This will router partitions the whole MCM routing space into a set of small towers and decompose the routing process into three phases, viz, routing distribution, terminal assignment, and tower routing. The router has three fundamental features. First, it maintains the 3-dimensional characteristics of the original problem while partitioning it into several smaller problems and as a result, it can achieve the best utilization of the routing space. Second, it is designed to meet the constraints of net-length, path-separation, parallel-path-length, and the number of stacked vias and thus can satisfy the design requirement of high performance MCMs. Finally, the approach is amiable to parallel processing which can be used to improve the time complexity and memory constraints in a parallel computing environment. Experimental evaluation confirms the validity of our approach.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131668168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753540
K. Yokouchi, K. Hashimoto, K. Niwa
The glass/alumina composite ceramics makes it possible to cofire the circuit board with low-resistivity conductor metals such as copper. The fired copper wiring have high reliability that is unchanged after 1000 cycles of thermal shock test, however, the thermal expansion coefficient of copper is much higher than that of the glass/alumina [1]. The difference of thermal expansion is larger than that of alumina and molybdenum, tungsten in the conventional multilayer circuit boards. The cofired copper wiring, lines and vias, have tensile strength of about 100 MPa, half of bulk copper, and ductile fracture characteristics. The ductility and high tensile strength make the wiring able to withstand stress due to large thermal expansion mismatch at the conductor-ceramic interface. The residual stress of thermal expansion mismatch on fracture of conductors was studied.
{"title":"Stress Induced in Ceramics-Conductor of Mcm","authors":"K. Yokouchi, K. Hashimoto, K. Niwa","doi":"10.1109/ICMCM.1994.753540","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753540","url":null,"abstract":"The glass/alumina composite ceramics makes it possible to cofire the circuit board with low-resistivity conductor metals such as copper. The fired copper wiring have high reliability that is unchanged after 1000 cycles of thermal shock test, however, the thermal expansion coefficient of copper is much higher than that of the glass/alumina [1]. The difference of thermal expansion is larger than that of alumina and molybdenum, tungsten in the conventional multilayer circuit boards. The cofired copper wiring, lines and vias, have tensile strength of about 100 MPa, half of bulk copper, and ductile fracture characteristics. The ductility and high tensile strength make the wiring able to withstand stress due to large thermal expansion mismatch at the conductor-ceramic interface. The residual stress of thermal expansion mismatch on fracture of conductors was studied.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133774025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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