Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753584
D. Carey, H. Hashemi, P. Hunter
MCC has been using laminate-based multichip modules (MCM-L) and advanced printed circuit board (PCB) technologies in a number of technology development efforts. These applications have targeted a spectrum of product profiles, from few chip packages to high performance computer processor modules. Example demonstrations and findings in each of these areas will be discussed. A main focus of the paper will be to review and challenge some general myths surrounding MCMs and MCM-L/PCB. Aspects of interconnect substrate cost, electrical performance, I/O density capability, and compatibility with high chip power input/output levels will be addressed in the context of both present and future MCM-L capabilities.
{"title":"Mcm-L Technologies: Myths and Experiences in Multiple Product Scenarios","authors":"D. Carey, H. Hashemi, P. Hunter","doi":"10.1109/ICMCM.1994.753584","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753584","url":null,"abstract":"MCC has been using laminate-based multichip modules (MCM-L) and advanced printed circuit board (PCB) technologies in a number of technology development efforts. These applications have targeted a spectrum of product profiles, from few chip packages to high performance computer processor modules. Example demonstrations and findings in each of these areas will be discussed. A main focus of the paper will be to review and challenge some general myths surrounding MCMs and MCM-L/PCB. Aspects of interconnect substrate cost, electrical performance, I/O density capability, and compatibility with high chip power input/output levels will be addressed in the context of both present and future MCM-L capabilities.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"331 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116234787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753603
L. Schaper, S. Ang, Y. Low
A significant decrease in MCM substrate production cost can be achieved by reducing the number of substrate layers from the conventional four or five (power, ground, X signal, Y signal, pad) to two or three. Besides reducing direct processing steps, yield will also increase as defect producing operations are eliminated. This paper describes the Interconnected Mesh Power System (IMPS), a new interconnection topology which leverages the production technologies of fine line lithography and batch via generation to allow planar power and ground distribution, and dense signal interconnection, on only two metal layers. Several possible implementations of the topology in MOM-D and MCM-L are described. The approach to incorporating IMPS in a standard commercial MCM design system is presented. The impact of a preferential routing scheme and a standardized pad structure is described. The design of a test vehicle which characterizes both the signal transmission and power distribution properties of the IMPS topology is discussed. Preliminary results of electrical characterization are described.
{"title":"Design of the Interconnected Mesh Power System (IMPS) MCM Topology","authors":"L. Schaper, S. Ang, Y. Low","doi":"10.1109/ICMCM.1994.753603","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753603","url":null,"abstract":"A significant decrease in MCM substrate production cost can be achieved by reducing the number of substrate layers from the conventional four or five (power, ground, X signal, Y signal, pad) to two or three. Besides reducing direct processing steps, yield will also increase as defect producing operations are eliminated. This paper describes the Interconnected Mesh Power System (IMPS), a new interconnection topology which leverages the production technologies of fine line lithography and batch via generation to allow planar power and ground distribution, and dense signal interconnection, on only two metal layers. Several possible implementations of the topology in MOM-D and MCM-L are described. The approach to incorporating IMPS in a standard commercial MCM design system is presented. The impact of a preferential routing scheme and a standardized pad structure is described. The design of a test vehicle which characterizes both the signal transmission and power distribution properties of the IMPS topology is discussed. Preliminary results of electrical characterization are described.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131535154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753551
K. Posse
The importance of a thorough test and accurate diagnosis of multichip module defects cannot be overemphasized. The cost of repairing a module coupled with the cost of the die which constitute the typical MCM makes an error in the defect analysis very expensive. Given the lack of access to the internal nodes of an MCM and given that the most common faults are expected to be manufacturing defects (opens shorts, wrong die, physical damage to the die, etc.), the IEEE 1149.1 boundary-scan standard is expected to play a very important role in the accurate diagnosis of a large percentage of module problems.
{"title":"Algorithmic Diagnosis of Multichip Module Defects Using the IEEE 1149.1 Standard","authors":"K. Posse","doi":"10.1109/ICMCM.1994.753551","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753551","url":null,"abstract":"The importance of a thorough test and accurate diagnosis of multichip module defects cannot be overemphasized. The cost of repairing a module coupled with the cost of the die which constitute the typical MCM makes an error in the defect analysis very expensive. Given the lack of access to the internal nodes of an MCM and given that the most common faults are expected to be manufacturing defects (opens shorts, wrong die, physical damage to the die, etc.), the IEEE 1149.1 boundary-scan standard is expected to play a very important role in the accurate diagnosis of a large percentage of module problems.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"400 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131786173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753602
R. McBride, D.P. Zarnow, R.L. Brown
Custom MCM design kits, as exemplified by Hughes' series of Deco Designer/sup TM/ kits for MCM-C and MCM-D design, are essential facilitators to cost-effective access to MCM foundries. Design kits have special features that simplify the physical design of complex MCM's through standardization and the use of special algorithms that can optimize commercial design systems for foundry-specific MCM technologies. These design kits have reduced the design cycle times of MCM-D to four weeks and MCM C to eight weeks, and represent over fifty designs committed to fabrication with first pass success. This paper discusses the cost savings benefits and technical accomplishments realized with design kits for standardization in routing and packaging. This paper reviews the essential role of databases in rapid prototyping for driving soft-tooled manufacturing for cost and cycle time reductions. Finally, future directions for the use of the design function as an "easy access" interface between customer and foundry is discussed.
{"title":"The Essential Role of Custom Design Kits for Cost-Effective Access to the Mcm Foundry","authors":"R. McBride, D.P. Zarnow, R.L. Brown","doi":"10.1109/ICMCM.1994.753602","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753602","url":null,"abstract":"Custom MCM design kits, as exemplified by Hughes' series of Deco Designer/sup TM/ kits for MCM-C and MCM-D design, are essential facilitators to cost-effective access to MCM foundries. Design kits have special features that simplify the physical design of complex MCM's through standardization and the use of special algorithms that can optimize commercial design systems for foundry-specific MCM technologies. These design kits have reduced the design cycle times of MCM-D to four weeks and MCM C to eight weeks, and represent over fifty designs committed to fabrication with first pass success. This paper discusses the cost savings benefits and technical accomplishments realized with design kits for standardization in routing and packaging. This paper reviews the essential role of databases in rapid prototyping for driving soft-tooled manufacturing for cost and cycle time reductions. Finally, future directions for the use of the design function as an \"easy access\" interface between customer and foundry is discussed.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133379543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753557
K. Hiwada, T. Tamura
We propose the newly developed contact scheme for high performance DUT (Device Under Test) interface, so called, HiPEC (High Performance Elastic Connection). The HiPEC consists of Ni based micro- bumps with Cu line-pattern on P-PTFE (Porous Poly Tetra Fluoro Ethylene) membrane, supported by silicon rubber elastoma. The metal contact via micro-bump makes a reliable contact by scratching action, generated by shape transformation of elastoma under small force. The P-PTFE membrane is usable beyond 10 GHz high frequency signal transmission, and has excellent high isolation characteristics with less than sub-pA leakage current. The HiPEC technology is useful for high pin count DUT interface with high performance, replacing contact-pin, and also for die chip contact to enable KGD (Known- Good Die) test of mixed signals MCM (Multi Chip Module).
{"title":"High Performance Elastic Connection for Reliable Device Testing","authors":"K. Hiwada, T. Tamura","doi":"10.1109/ICMCM.1994.753557","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753557","url":null,"abstract":"We propose the newly developed contact scheme for high performance DUT (Device Under Test) interface, so called, HiPEC (High Performance Elastic Connection). The HiPEC consists of Ni based micro- bumps with Cu line-pattern on P-PTFE (Porous Poly Tetra Fluoro Ethylene) membrane, supported by silicon rubber elastoma. The metal contact via micro-bump makes a reliable contact by scratching action, generated by shape transformation of elastoma under small force. The P-PTFE membrane is usable beyond 10 GHz high frequency signal transmission, and has excellent high isolation characteristics with less than sub-pA leakage current. The HiPEC technology is useful for high pin count DUT interface with high performance, replacing contact-pin, and also for die chip contact to enable KGD (Known- Good Die) test of mixed signals MCM (Multi Chip Module).","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127411083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753564
R. Saia, R. Wojnarowski, R. Fillion, G. Forman, B. Gorowitz
To solve the interconnect and packaging problems associated with large distributed processing systems and of mass memory systems, the GE Corporate Research and Development Center has developed a 3-D stacked multichip module (MCM) technology. This technology uses, as building blocks, modules produced by the GE High Density Interconnect (HDI) embedded chip process. The fundamental features of this 2-D HDI polymer film overlay process, which are used to interconnect a number of chips within a common substrate, are extended to the interconnection of a number of multichip substrates. The 2-D HDI substrates with their essentially planar surface, and chips recessed beneath the interconnect structure, are ideally suited for direct 3-D stacking of one substrate upon another. The thermal path of the stack is directly through the substrate to the base of the stack. The substrate I/O connections are brought to the substrate edges for vertical connection within the stack. The multilayer lamination and thin film interconnect processes used to interconnect the chips, i.e. polyimide film dielectric, laser formed vias, and electroplated copper metallization, are then applied to one or more of the four edges of the stack. This paper will describe the basic 2-D HDI process and how it was extended to the 3-D interconnection of multichip substrates.
为了解决与大型分布式处理系统和海量存储系统相关的互连和封装问题，GE公司研发中心开发了一种3-D堆叠多芯片模块(MCM)技术。该技术使用GE High Density Interconnect (HDI)嵌入式芯片工艺生产的模块作为构建模块。这种二维HDI聚合物薄膜覆盖工艺的基本特征，用于在公共衬底内互连多个芯片，扩展到多个多芯片衬底的互连。二维HDI衬底具有基本的平面表面，芯片嵌入互连结构之下，非常适合将一个衬底直接堆叠在另一个衬底上。堆的热路径是直接通过基板到堆的底部。基板I/O连接被带到基板边缘，以便在堆栈内进行垂直连接。然后将用于互连芯片的多层层压和薄膜互连工艺，即聚酰亚胺薄膜介电介质，激光形成的过孔和电镀铜金属化，应用于堆栈的四个边缘中的一个或多个。本文将描述基本的二维HDI过程，以及如何将其扩展到多芯片基板的三维互连。
{"title":"3-D Stacking Using the GE High Density Multichip Module Technology","authors":"R. Saia, R. Wojnarowski, R. Fillion, G. Forman, B. Gorowitz","doi":"10.1109/ICMCM.1994.753564","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753564","url":null,"abstract":"To solve the interconnect and packaging problems associated with large distributed processing systems and of mass memory systems, the GE Corporate Research and Development Center has developed a 3-D stacked multichip module (MCM) technology. This technology uses, as building blocks, modules produced by the GE High Density Interconnect (HDI) embedded chip process. The fundamental features of this 2-D HDI polymer film overlay process, which are used to interconnect a number of chips within a common substrate, are extended to the interconnection of a number of multichip substrates. The 2-D HDI substrates with their essentially planar surface, and chips recessed beneath the interconnect structure, are ideally suited for direct 3-D stacking of one substrate upon another. The thermal path of the stack is directly through the substrate to the base of the stack. The substrate I/O connections are brought to the substrate edges for vertical connection within the stack. The multilayer lamination and thin film interconnect processes used to interconnect the chips, i.e. polyimide film dielectric, laser formed vias, and electroplated copper metallization, are then applied to one or more of the four edges of the stack. This paper will describe the basic 2-D HDI process and how it was extended to the 3-D interconnection of multichip substrates.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131010907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753550
W. Blood, A. Flint
A family of high performance, computer oriented multichip module (MCM) products is being developed to provide the building blocks for advanced, high density computer systems. Each MCM is a system level building block that interfaces to other family members through compatible processor and memory busses. By selecting and interconnecting the various MGM blocks, it is possible to configure a variety of high speed, cache coherent, multiprocessing computer designs. The use of multichip modules is necessary to meet system performance and size requirements. This paper focuses on a specific member of the MGM family, a 4M word by 40 bit Dynamic Random Access Memory (DRAM). Special attention is given to product requirements, design methodology, and test strategy. MCM testing is sufficiently complex that test must be an integral part of the complete module design process.
{"title":"Design and Test of a Complex Mcm Product","authors":"W. Blood, A. Flint","doi":"10.1109/ICMCM.1994.753550","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753550","url":null,"abstract":"A family of high performance, computer oriented multichip module (MCM) products is being developed to provide the building blocks for advanced, high density computer systems. Each MCM is a system level building block that interfaces to other family members through compatible processor and memory busses. By selecting and interconnecting the various MGM blocks, it is possible to configure a variety of high speed, cache coherent, multiprocessing computer designs. The use of multichip modules is necessary to meet system performance and size requirements. This paper focuses on a specific member of the MGM family, a 4M word by 40 bit Dynamic Random Access Memory (DRAM). Special attention is given to product requirements, design methodology, and test strategy. MCM testing is sufficiently complex that test must be an integral part of the complete module design process.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122944325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753537
C. Narayan, S. Purushothaman, F. Doany, A. Deutsch
This paper describes a unique, highly flexible and cost competitive method to fabricate microelectronic packages that require thin film interconnections. The method involves fabricating thin film metal/polymer structures multi-up on a reusable temporary glass carrier and later transferring the thin film stack onto product substrates of choice. The final product substrate can be silicon, co-fired alumina or glass-ceramic, aluminum nitride, diamond or a printed wiring board. Optionally, one can also use the released thin film decal as a flexible high wireability interconnect by itself, as an interposer, or in applications Re wafer level testing for known good die (KGD). The thin film wiring structure can be fabricated multi-up on a standardized form factor carrier (independent of the characteristics of the final product substrate) in a thin film interconnect foundry, thus significantly reducing cost both from the economy of scales and full utilization of the thin film factory for a variety of customer needs.
{"title":"Thin Film Transfer Process for Low Cost Mcm-D Fabrication","authors":"C. Narayan, S. Purushothaman, F. Doany, A. Deutsch","doi":"10.1109/ICMCM.1994.753537","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753537","url":null,"abstract":"This paper describes a unique, highly flexible and cost competitive method to fabricate microelectronic packages that require thin film interconnections. The method involves fabricating thin film metal/polymer structures multi-up on a reusable temporary glass carrier and later transferring the thin film stack onto product substrates of choice. The final product substrate can be silicon, co-fired alumina or glass-ceramic, aluminum nitride, diamond or a printed wiring board. Optionally, one can also use the released thin film decal as a flexible high wireability interconnect by itself, as an interposer, or in applications Re wafer level testing for known good die (KGD). The thin film wiring structure can be fabricated multi-up on a standardized form factor carrier (independent of the characteristics of the final product substrate) in a thin film interconnect foundry, thus significantly reducing cost both from the economy of scales and full utilization of the thin film factory for a variety of customer needs.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126410631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753567
D. Cokely, C. Strittmatter
The economics governing the decision to design and integrate MCMs into products is often limited to comparison of the associated material costs. In many cases, MCM material costs exceed that of the discretes and integrated circuits which it could potentially replace. Such narrow focus has contributed to a stifling of the MCM technology explosion. Equitable comparisons must be made through a full stream system analysis with consideration given to feature enhancement, overall yield, labor, load and warranty impacts on the end product. MicroInterconnect Technology is an extension of traditional MCMs in that integration of functions can result in space and performance improvements. However, when ICs are flipped to a silicon substrate containing active and passive devices, component count decreases significantly and the critical system performance metrics, are further improved. At AT&T-Shreveport, small business telephone systems are manufactured to compete with other "commodity" vendors in the world market. Success in this high volume environment requires aggressive cost management and achievement of reliability levels consistent with consumer expectations. The Partner/sup R/ Product Management Team will be the first to integrate flip-chip, silicon-on-silicon, MicroInterconnect MCM technology by 2Q94. Successive cost reductions will be enabled with the introduction of MicroInterconnect Technology which positively affect system cost and performance.
{"title":"Redefining the Economics of Mcm Applications","authors":"D. Cokely, C. Strittmatter","doi":"10.1109/ICMCM.1994.753567","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753567","url":null,"abstract":"The economics governing the decision to design and integrate MCMs into products is often limited to comparison of the associated material costs. In many cases, MCM material costs exceed that of the discretes and integrated circuits which it could potentially replace. Such narrow focus has contributed to a stifling of the MCM technology explosion. Equitable comparisons must be made through a full stream system analysis with consideration given to feature enhancement, overall yield, labor, load and warranty impacts on the end product. MicroInterconnect Technology is an extension of traditional MCMs in that integration of functions can result in space and performance improvements. However, when ICs are flipped to a silicon substrate containing active and passive devices, component count decreases significantly and the critical system performance metrics, are further improved. At AT&T-Shreveport, small business telephone systems are manufactured to compete with other \"commodity\" vendors in the world market. Success in this high volume environment requires aggressive cost management and achievement of reliability levels consistent with consumer expectations. The Partner/sup R/ Product Management Team will be the first to integrate flip-chip, silicon-on-silicon, MicroInterconnect MCM technology by 2Q94. Successive cost reductions will be enabled with the introduction of MicroInterconnect Technology which positively affect system cost and performance.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122229293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753586
D. Light, J. S. Kresge, C.R. Davis
IBM Microelectronics has developed a High Performance Carrier (HPC) technology to provide leading edge packaging solutions to evolving computer system demands. High Performance Carrier provides high wireability, high performance, and high I/O capability at an affordable cost per unit function and performance. High Performance Carrier is an extremely versatile interconnection technology which is suitable for a broad range of applications. HPC utilizes a Teflon (R) based insulator material to provide superior electrical and mechanical characteristics, and a unique composite layer-joining process to enhance wireability, design flexibility, and composite yield. The High Performance Carrier technology can also provide integration of carrier, flex cables and connector into a single structure: cables are essentially the continuation of 'long' cores which extend beyond the laminated carrier region. This eliminates the need for mechanical or soldered interconnections at the cable-carrier interface. This design capability can significantly reduce interconnection distances and eliminate impedance discontinuities between the cable and carrier. I/O capability is drastically increased over conventional technologies: up to 300 I/O per linear inch per cable can be packaged. Cables can extend from any or all 4 edges of the carrier, providing a whole new realm of possibilities for interconnection of system packaging components, such as SCM's, MCM's, printed wiring boards, and switching networks. Three dimensional and folding third level packaging designs are also facilitated. This paper will give an overview of the HPC technology, and will discuss design, performance, reliability, and process aspects of Integrated Flex in detail.
{"title":"Integrated Flex: Rigid-Flex Capability in a High Performance Mcm","authors":"D. Light, J. S. Kresge, C.R. Davis","doi":"10.1109/ICMCM.1994.753586","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753586","url":null,"abstract":"IBM Microelectronics has developed a High Performance Carrier (HPC) technology to provide leading edge packaging solutions to evolving computer system demands. High Performance Carrier provides high wireability, high performance, and high I/O capability at an affordable cost per unit function and performance. High Performance Carrier is an extremely versatile interconnection technology which is suitable for a broad range of applications. HPC utilizes a Teflon (R) based insulator material to provide superior electrical and mechanical characteristics, and a unique composite layer-joining process to enhance wireability, design flexibility, and composite yield. The High Performance Carrier technology can also provide integration of carrier, flex cables and connector into a single structure: cables are essentially the continuation of 'long' cores which extend beyond the laminated carrier region. This eliminates the need for mechanical or soldered interconnections at the cable-carrier interface. This design capability can significantly reduce interconnection distances and eliminate impedance discontinuities between the cable and carrier. I/O capability is drastically increased over conventional technologies: up to 300 I/O per linear inch per cable can be packaged. Cables can extend from any or all 4 edges of the carrier, providing a whole new realm of possibilities for interconnection of system packaging components, such as SCM's, MCM's, printed wiring boards, and switching networks. Three dimensional and folding third level packaging designs are also facilitated. This paper will give an overview of the HPC technology, and will discuss design, performance, reliability, and process aspects of Integrated Flex in detail.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114243473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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