Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753556
J. Eastman, W. Creighton, A. Laidler, Tak Lun Leung
The high-volume production and rework of 100 chip MCMs in a structured test environment and the rationale for defect migration (continuous quality improvement) is described. Manufacturing and rework of these MCMs requires continuous improvements in chip quality. This necessitates in- expensive diagnostics at chip, INICM and system level so that the root cause of the defects can be determined and the chip fabrication, test, and burn-in processes improved. The requirements for and implementation of structural test (to detect both stuck fault and delay defects), diagnostic automation, system level test correlation, coordination of defect tracking at the system, MCM and chip level and defect model correlation are discussed. The MCMs are designed using level-sensitive scan design (LSSD). Through the use of structural test and it's associated diagnostics, the details of the defects are sup- plied to the chip fabricator who successfully improves the chip quality levels.
{"title":"Defect Migration of Multi-chip Modules Using Structural Test","authors":"J. Eastman, W. Creighton, A. Laidler, Tak Lun Leung","doi":"10.1109/ICMCM.1994.753556","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753556","url":null,"abstract":"The high-volume production and rework of 100 chip MCMs in a structured test environment and the rationale for defect migration (continuous quality improvement) is described. Manufacturing and rework of these MCMs requires continuous improvements in chip quality. This necessitates in- expensive diagnostics at chip, INICM and system level so that the root cause of the defects can be determined and the chip fabrication, test, and burn-in processes improved. The requirements for and implementation of structural test (to detect both stuck fault and delay defects), diagnostic automation, system level test correlation, coordination of defect tracking at the system, MCM and chip level and defect model correlation are discussed. The MCMs are designed using level-sensitive scan design (LSSD). Through the use of structural test and it's associated diagnostics, the details of the defects are sup- plied to the chip fabricator who successfully improves the chip quality levels.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126202140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753604
J. Demmin
It is widely known that thermal management is critical to the success of multichip module (MCM) packaging because of the density and performance of typical MCMs, but the thermal aspects of different MCM technologies are less well understood. Simplistic analysis can be misleading when, for example, the trade-offs in size, cost, and electrical performance needed to meet thermal requirements are ignored. In addition, certain subtleties of thermal performance and analysis can invalidate the first-order evaluations that often guide design decisions. This work attempts to clarify the situation by evaluating the thermal characteristics of various MCM technologies with finite element modeling techniques. This work also addresses the problem by examining some of the less intuitive aspects of MCM thermal analysis. A summary of issues to consider when evaluating thermal performance of MCM technologies is presented.
{"title":"Choosing an Mcm Technology for Thermal Performance","authors":"J. Demmin","doi":"10.1109/ICMCM.1994.753604","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753604","url":null,"abstract":"It is widely known that thermal management is critical to the success of multichip module (MCM) packaging because of the density and performance of typical MCMs, but the thermal aspects of different MCM technologies are less well understood. Simplistic analysis can be misleading when, for example, the trade-offs in size, cost, and electrical performance needed to meet thermal requirements are ignored. In addition, certain subtleties of thermal performance and analysis can invalidate the first-order evaluations that often guide design decisions. This work attempts to clarify the situation by evaluating the thermal characteristics of various MCM technologies with finite element modeling techniques. This work also addresses the problem by examining some of the less intuitive aspects of MCM thermal analysis. A summary of issues to consider when evaluating thermal performance of MCM technologies is presented.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126352993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753555
T. Bardsley, J. Lisowski, S. Wilson, S. VanAernam
Multi-chip module burn-in has been utilized at IBM for several years. The current module burn-in tool stresses 121 chip multi-chip modules used in the IBM ES/9000 mainframes. MCM level burn-in has been performed on alumina and glass-ceramic substrates with bipolar and CMOS chip technologies resulting in various challenges to tool design and proem development. This paper will focus on the module burn-in tool, key technical challenges to implementing MCM burn-in and the experience of performing MCM level burn-in. The key technical challenges: thermal management, thermal/mechanical stress issues, electrical stimulation and module testability will be reviewed. The impact of design for test on burn-in will be discussed. A review of the defect mechanisms and experimental results will be covered. An overview of a cost model which compares MCM level burn-in against known-good-die burn-in will be reviewed to demonstrate the merits of module level burn-in. The paper will conclude with the future plans to address the rapidly expanding OEM MCM market.
{"title":"Mcm Burn-In Experience","authors":"T. Bardsley, J. Lisowski, S. Wilson, S. VanAernam","doi":"10.1109/ICMCM.1994.753555","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753555","url":null,"abstract":"Multi-chip module burn-in has been utilized at IBM for several years. The current module burn-in tool stresses 121 chip multi-chip modules used in the IBM ES/9000 mainframes. MCM level burn-in has been performed on alumina and glass-ceramic substrates with bipolar and CMOS chip technologies resulting in various challenges to tool design and proem development. This paper will focus on the module burn-in tool, key technical challenges to implementing MCM burn-in and the experience of performing MCM level burn-in. The key technical challenges: thermal management, thermal/mechanical stress issues, electrical stimulation and module testability will be reviewed. The impact of design for test on burn-in will be discussed. A review of the defect mechanisms and experimental results will be covered. An overview of a cost model which compares MCM level burn-in against known-good-die burn-in will be reviewed to demonstrate the merits of module level burn-in. The paper will conclude with the future plans to address the rapidly expanding OEM MCM market.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125039765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ICMCM.1994.753597
J. Miks
Ever since the push to eliminate through hole technology for maximized component density on printed wiring boards (PWB's), the cost for the surface mount technology (SMT) packages has escalated for high lead count devices (greater than 150 leads). The primary reason for this increase is the fact that to achieve reasonable package densities on the printed wiring boards (PWB's), fine pitch leaded devices are a necessity (less than 25 mil lead pitch). The industry is in desperate need of a cost effective SMT package design, and the Ceramic Ball Grid Array (CBGA) and/or the Ceramic Column Grid Array (CCGA) packages are the solution. This paper primarily focuses in on Ceramic Ball Grid Array (CBGA) and Ceramic Column Grid Array (CCGA) packaging, but does go into discussion of all existing packaging schemes on the market today for large die (greater than 5mm). Specifically, the advantages and disadvantages of fine pitch devices, detailed description of the 1.00mm interconnect pitch CBGA/CCGA packages, CBGA/CCGA standard package offerings (JEDEC registered), general package comparisons to each other (in the areas of thermal performance, electrical performance, size, cost, and overall component density on the PWB), solder interconnect fatigue properties of the CBGA/CCGA (i.e. predicted and measured low cycle fatigue life of the device), solder interconnect inspection of the CBGA/CCGA (should inspection be performed?), test and burn-in of the CBGA/CCGA devices, CBGA/CCGA device shipping method for pick and place and/or manual assembly, how to perform CBGA/CCGA board attach on existing PWB's (i.e. what are the manufacturing process differences for the CBGA/CCGA board attach process), and finally how to layout the PWB breakout pattern for the CBGA/CCGA to minimize the number of PWB routing layers.
{"title":"Cost effective ceramic surface mount packaging for high I/O applications","authors":"J. Miks","doi":"10.1109/ICMCM.1994.753597","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753597","url":null,"abstract":"Ever since the push to eliminate through hole technology for maximized component density on printed wiring boards (PWB's), the cost for the surface mount technology (SMT) packages has escalated for high lead count devices (greater than 150 leads). The primary reason for this increase is the fact that to achieve reasonable package densities on the printed wiring boards (PWB's), fine pitch leaded devices are a necessity (less than 25 mil lead pitch). The industry is in desperate need of a cost effective SMT package design, and the Ceramic Ball Grid Array (CBGA) and/or the Ceramic Column Grid Array (CCGA) packages are the solution. This paper primarily focuses in on Ceramic Ball Grid Array (CBGA) and Ceramic Column Grid Array (CCGA) packaging, but does go into discussion of all existing packaging schemes on the market today for large die (greater than 5mm). Specifically, the advantages and disadvantages of fine pitch devices, detailed description of the 1.00mm interconnect pitch CBGA/CCGA packages, CBGA/CCGA standard package offerings (JEDEC registered), general package comparisons to each other (in the areas of thermal performance, electrical performance, size, cost, and overall component density on the PWB), solder interconnect fatigue properties of the CBGA/CCGA (i.e. predicted and measured low cycle fatigue life of the device), solder interconnect inspection of the CBGA/CCGA (should inspection be performed?), test and burn-in of the CBGA/CCGA devices, CBGA/CCGA device shipping method for pick and place and/or manual assembly, how to perform CBGA/CCGA board attach on existing PWB's (i.e. what are the manufacturing process differences for the CBGA/CCGA board attach process), and finally how to layout the PWB breakout pattern for the CBGA/CCGA to minimize the number of PWB routing layers.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130584550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ICMCM.1994.753519
{"title":"Proceedings of the 1994 International Conference on Multichip Modules","authors":"","doi":"10.1109/ICMCM.1994.753519","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753519","url":null,"abstract":"","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125911301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ICMCM.1994.753590
A. Bet-Shliemoun, M. McGraw, B. Griswold, Chung Ho, S. Westbrook
MCM-D interconnect is most often pictured as deposited thin-film layers on one side of a supporting substrate. Overall package thickness is limited by the thickness of this supporting structure. Often the substrate is more than an order of magnitude thicker than the thin-film layers deposited on its surface. If this substrate can be removed, much thinner multichip packages are possible. A packaging technique using free-standing copper/polyimide films will be presented. This MCM-D package has devices attached to both sides of the film to achieve not only good silicon density but an overall thin package profile. This paper will discuss an implementation of this technology for an EIAJ-standard 14mm by 20mm body size with a 2.75 mm thickness. Design and assembly of the package will be highlighted.
{"title":"Thin-Profile MCM-D Packaging for Small Form Factor Applications","authors":"A. Bet-Shliemoun, M. McGraw, B. Griswold, Chung Ho, S. Westbrook","doi":"10.1109/ICMCM.1994.753590","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753590","url":null,"abstract":"MCM-D interconnect is most often pictured as deposited thin-film layers on one side of a supporting substrate. Overall package thickness is limited by the thickness of this supporting structure. Often the substrate is more than an order of magnitude thicker than the thin-film layers deposited on its surface. If this substrate can be removed, much thinner multichip packages are possible. A packaging technique using free-standing copper/polyimide films will be presented. This MCM-D package has devices attached to both sides of the film to achieve not only good silicon density but an overall thin package profile. This paper will discuss an implementation of this technology for an EIAJ-standard 14mm by 20mm body size with a 2.75 mm thickness. Design and assembly of the package will be highlighted.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"06 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127571219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ICMCM.1994.753553
D. Place
Testing multichip modules (MCM's), MMIC devices, T/R modules, hybrid circuits, bare die, and any device with x,y,z and theta variations can now be performed automatically using a newly developed Vision Probing System.
{"title":"Testing Multichip Modules and Bare Die Using Vision Probing Techniques","authors":"D. Place","doi":"10.1109/ICMCM.1994.753553","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753553","url":null,"abstract":"Testing multichip modules (MCM's), MMIC devices, T/R modules, hybrid circuits, bare die, and any device with x,y,z and theta variations can now be performed automatically using a newly developed Vision Probing System.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115099842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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