Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753562
D. Scheid
This paper describes a thin film process that was developed for fabricating a high performance Cu/PI MCM-D with embedded TiW thin film resistors using standard IC equipment, modified to handle square substrates. Several thousand MCM's have been produced with exceptional AC and DC characteristics. These MCM's were attached to a larger MCM-L substrate that functioned as a logic module tester, capable of greater than 600 MHz operation. Each MCM provided for interconnection of 4 large ECL gate arrays, 9 decoupling capacitors and 18 resistor networks. By integrating the resistors into the thin film stack better performance and cost savings could be achieved. This was a result of the reduced parasitics, increased routability and component reduction. The MCM thin film consisted of 8 metal layers (4 routing, 3 power-ground and I for resistor formation) deposited on a glass ceramic substrate. The MGM measures 4.6 cm/sup 2/ and has more than 15 meters of thin film routing available with 2,000 vias/cm/sup 2/.
{"title":"Advanced Mcm-d With Embedded Resistors","authors":"D. Scheid","doi":"10.1109/ICMCM.1994.753562","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753562","url":null,"abstract":"This paper describes a thin film process that was developed for fabricating a high performance Cu/PI MCM-D with embedded TiW thin film resistors using standard IC equipment, modified to handle square substrates. Several thousand MCM's have been produced with exceptional AC and DC characteristics. These MCM's were attached to a larger MCM-L substrate that functioned as a logic module tester, capable of greater than 600 MHz operation. Each MCM provided for interconnection of 4 large ECL gate arrays, 9 decoupling capacitors and 18 resistor networks. By integrating the resistors into the thin film stack better performance and cost savings could be achieved. This was a result of the reduced parasitics, increased routability and component reduction. The MCM thin film consisted of 8 metal layers (4 routing, 3 power-ground and I for resistor formation) deposited on a glass ceramic substrate. The MGM measures 4.6 cm/sup 2/ and has more than 15 meters of thin film routing available with 2,000 vias/cm/sup 2/.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"229 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120878923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753543
T. Kishimoto, S. Sasaki, K. Genda, K. Endo, K. Kaizu
This paper describes an innovative heat-pipe cooling technology for high-speed ATM switching MCMs operating with a throughput of 40 Gb/s. Although high-speed ATM link wires are interconnected on the top surface of the MCMs, there is no room to coot the MCM by forced air convection, because the power and the system clock signal are supplied by the connector on the back side and peripheral of the MCM. We therefore attach a cold-plate to the back of each MCM. The condenser parts of the heat pipe, which is mounted behind the power supply printed circuit board, are cooled by low-velocity forced air. Total power dissipation including the power dissipation of the termination resistors is about 30 watts per MCM. With a 2 m/s forced air flow, this sub-switching element module operates at a throughput of 80 Gb/s (including 4 MCMs) with maximum junction temperature of less than 85 /spl deg/C. Measured thermal resistance between the switch LSI junction and air is about 6 /spl deg/C/W at an air flow of 2 m/s. This heat-pipe cooling system has small system footprint, compact hardware, and good cooling capability. We, demonstrate its effectiveness in cooling high-speed ATM switching MCMS operating with a throughput of 40 Gb/s.
{"title":"Heat-Pipe Cooling Technology for High-Speed Atm Switching Mcms","authors":"T. Kishimoto, S. Sasaki, K. Genda, K. Endo, K. Kaizu","doi":"10.1109/ICMCM.1994.753543","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753543","url":null,"abstract":"This paper describes an innovative heat-pipe cooling technology for high-speed ATM switching MCMs operating with a throughput of 40 Gb/s. Although high-speed ATM link wires are interconnected on the top surface of the MCMs, there is no room to coot the MCM by forced air convection, because the power and the system clock signal are supplied by the connector on the back side and peripheral of the MCM. We therefore attach a cold-plate to the back of each MCM. The condenser parts of the heat pipe, which is mounted behind the power supply printed circuit board, are cooled by low-velocity forced air. Total power dissipation including the power dissipation of the termination resistors is about 30 watts per MCM. With a 2 m/s forced air flow, this sub-switching element module operates at a throughput of 80 Gb/s (including 4 MCMs) with maximum junction temperature of less than 85 /spl deg/C. Measured thermal resistance between the switch LSI junction and air is about 6 /spl deg/C/W at an air flow of 2 m/s. This heat-pipe cooling system has small system footprint, compact hardware, and good cooling capability. We, demonstrate its effectiveness in cooling high-speed ATM switching MCMS operating with a throughput of 40 Gb/s.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126004174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753521
B. Vasquez, S. Lindsey
The yield and reliability requirements for multichip packaging (MCP) applications have provided the major impetus for the development of known-good-die (KGD) technology solutions. KGD technology includes components of electrical contact, mechanical fixturing, IC design, test and automation. This paper will provide an overview of the KGD market and KGD technologies currently available in the industry. Die-Level-Burn-In (DLBI) approaches based on temporary bare die carriers are emerging in the industry. The goal for carrier development for test and burn-in is a cost-effective, bare die contact and fixturing approach that accommodates both peripheral and array contacts as well as wire bond and bumped die. For semiconductor manufacturers, possibility of conducting burn-in in wafer form is more attractive and holds the promise of reducing the total cost to manufacture die, regardless of the packaging destination. This paper will provide a review of KGD technology solutions which span a range of maturity from conceptual to qualified for production.
{"title":"The Promise of Known-good-die Technologies","authors":"B. Vasquez, S. Lindsey","doi":"10.1109/ICMCM.1994.753521","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753521","url":null,"abstract":"The yield and reliability requirements for multichip packaging (MCP) applications have provided the major impetus for the development of known-good-die (KGD) technology solutions. KGD technology includes components of electrical contact, mechanical fixturing, IC design, test and automation. This paper will provide an overview of the KGD market and KGD technologies currently available in the industry. Die-Level-Burn-In (DLBI) approaches based on temporary bare die carriers are emerging in the industry. The goal for carrier development for test and burn-in is a cost-effective, bare die contact and fixturing approach that accommodates both peripheral and array contacts as well as wire bond and bumped die. For semiconductor manufacturers, possibility of conducting burn-in in wafer form is more attractive and holds the promise of reducing the total cost to manufacture die, regardless of the packaging destination. This paper will provide a review of KGD technology solutions which span a range of maturity from conceptual to qualified for production.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127184765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753583
K. Kurzweil, H. Wessely
The European Economic Community is sponsoring technical projects carried out in cooperation by European Companies and academic institutions. APACHIP -Advanced Packaging for High Performance has significantly contributed to the advancement of packaging technology in Europe, covering various aspects of high performance packaging. This paper illustrates one of the specific project tasks aimed at building a complex large size water cooled MCM-L module populated with up to 100 TAB bonded complex semiconductor chips.
{"title":"Advanced Mcm-L in Apachip a European Cooperative Program","authors":"K. Kurzweil, H. Wessely","doi":"10.1109/ICMCM.1994.753583","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753583","url":null,"abstract":"The European Economic Community is sponsoring technical projects carried out in cooperation by European Companies and academic institutions. APACHIP -Advanced Packaging for High Performance has significantly contributed to the advancement of packaging technology in Europe, covering various aspects of high performance packaging. This paper illustrates one of the specific project tasks aimed at building a complex large size water cooled MCM-L module populated with up to 100 TAB bonded complex semiconductor chips.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"334 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127575197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753575
W. T. Minehan, W. Weidner, R. Jensen, R. Spielberger, W. F. Jacobsen, C. Speerschneider
A three-dimensional interconnect structure utilizing MCM-C technology is currently being developed by Honeywell Solid State Electronics Center (SSEQ and Coors Electronic Package Company. This concept involves the stacking of double sided co-fired aluminum nitride (AIN) MCMs. The double sided MCMs are stacked vertically using solder attached co-fired AIN spacer bars that have been manufactured with metallized through vias and have been designed to incorporate all electrical interconnection within the ceramic. The spacer bar acts as a thermal and electrical interconnect between substrates. Prototypes are currently being produced and evaluated for thermal, electrical, and mechanical integrity. Two technology characterization vehicles (TCVs) have been designed and constructed; the first TCV contains 6 metal layers and sites for wirebond, tape automated bonding (TAB), and flip chip mounting. A second characterization vehicle contains 15 metal planes and additional electrical characterization features. This paper will discuss the fabrication and assembly of the two TCVs. This Three-Dimensional Interconnect Structures Program is being funded by Naval Command, Control and Ocean Surveillance Center (NCCOSC).
{"title":"Fabrication, Assembly, and Characterization of Stacked Multichip Modules Using Hot Pressed, Co-Fired Aluminum Nitride","authors":"W. T. Minehan, W. Weidner, R. Jensen, R. Spielberger, W. F. Jacobsen, C. Speerschneider","doi":"10.1109/ICMCM.1994.753575","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753575","url":null,"abstract":"A three-dimensional interconnect structure utilizing MCM-C technology is currently being developed by Honeywell Solid State Electronics Center (SSEQ and Coors Electronic Package Company. This concept involves the stacking of double sided co-fired aluminum nitride (AIN) MCMs. The double sided MCMs are stacked vertically using solder attached co-fired AIN spacer bars that have been manufactured with metallized through vias and have been designed to incorporate all electrical interconnection within the ceramic. The spacer bar acts as a thermal and electrical interconnect between substrates. Prototypes are currently being produced and evaluated for thermal, electrical, and mechanical integrity. Two technology characterization vehicles (TCVs) have been designed and constructed; the first TCV contains 6 metal layers and sites for wirebond, tape automated bonding (TAB), and flip chip mounting. A second characterization vehicle contains 15 metal planes and additional electrical characterization features. This paper will discuss the fabrication and assembly of the two TCVs. This Three-Dimensional Interconnect Structures Program is being funded by Naval Command, Control and Ocean Surveillance Center (NCCOSC).","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126306802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753582
W. Radlik, K. Plehnert, M. Zellner, A. Achen, R. Heistand, D. Castillo, R. Urscheler
Taking advantage of the inherent capabilities of thin film technology, a cost competitive MCM-D has been built providing for a data communication assembly. For the dielectric layers, the novel photodefinable benzocyclobutene (BCB) has been employed. Thus, the material performance has been investigated and new processing steps have been developed to achieve a highly reliable formation of 10 /spl m/m vias at least.
{"title":"Mcm-D Technology for a Communication Application","authors":"W. Radlik, K. Plehnert, M. Zellner, A. Achen, R. Heistand, D. Castillo, R. Urscheler","doi":"10.1109/ICMCM.1994.753582","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753582","url":null,"abstract":"Taking advantage of the inherent capabilities of thin film technology, a cost competitive MCM-D has been built providing for a data communication assembly. For the dielectric layers, the novel photodefinable benzocyclobutene (BCB) has been employed. Thus, the material performance has been investigated and new processing steps have been developed to achieve a highly reliable formation of 10 /spl m/m vias at least.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114696150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753593
M. Swaminathan, A. Sarfaraz, J. Crocker, H. Bhatia
This paper details the electrical design of a multichip module ( MCM ) which represents a single node of a multiprocessor digital system. After a brief overview on the architecture, the paper discusses the key performance related ingredients of the MCM such as optimum chip placement, waveform degradation, delay and noise budgets. It is the conclusion of the paper that the physical and electrical design of an MCM be conducted in parallel so as to ensure the electrical performance of the module with minimum redesign.
{"title":"Electrical Design of an Mcm for a Multiprocessor System","authors":"M. Swaminathan, A. Sarfaraz, J. Crocker, H. Bhatia","doi":"10.1109/ICMCM.1994.753593","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753593","url":null,"abstract":"This paper details the electrical design of a multichip module ( MCM ) which represents a single node of a multiprocessor digital system. After a brief overview on the architecture, the paper discusses the key performance related ingredients of the MCM such as optimum chip placement, waveform degradation, delay and noise budgets. It is the conclusion of the paper that the physical and electrical design of an MCM be conducted in parallel so as to ensure the electrical performance of the module with minimum redesign.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133978784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753594
D. Salzman, T. Knight
This paper introduces a radically new method for interconnecting electronic packages electrically and mechanically. It applies to Levels 0-3 inclusive, including die-to-die (Level 0 - Level 0), die-to- substrate (0-1), substrate-to-substrate (1-1), module-to- module (2-2), and substrate to cable or backplane (1-3). Pulse signals are used to signal among semiconductor wafers, dies, modules, or other ensembles of components Capacitive coupling makes possible extremely dense, low-cost, high-performance interconnections. Uniform electrical interfaces make an integrated package possible, collapsing the traditional packaging hierarchy into a single uniform level. Inherently much lower cost is entailed in the design, test, assembly, and rework of capacitively coupled multichip modules than for conductive modules. Savings accrue from eliminating mechanical connectors, backplane structures, processing equipment & steps, materials, and failure modes of all of these. The requisite equipment already exists in foundries, not just in dedicated MCM houses. Substrates may be thin or thick film, so long as smoothness and planarity match the density and decoupling requirements. For these reasons, any system comprising two or more die where pulse drivers and receivers can be designed in may be a candidate for capacitive coupling.
{"title":"Capacitively Coupled Multichip Modules","authors":"D. Salzman, T. Knight","doi":"10.1109/ICMCM.1994.753594","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753594","url":null,"abstract":"This paper introduces a radically new method for interconnecting electronic packages electrically and mechanically. It applies to Levels 0-3 inclusive, including die-to-die (Level 0 - Level 0), die-to- substrate (0-1), substrate-to-substrate (1-1), module-to- module (2-2), and substrate to cable or backplane (1-3). Pulse signals are used to signal among semiconductor wafers, dies, modules, or other ensembles of components Capacitive coupling makes possible extremely dense, low-cost, high-performance interconnections. Uniform electrical interfaces make an integrated package possible, collapsing the traditional packaging hierarchy into a single uniform level. Inherently much lower cost is entailed in the design, test, assembly, and rework of capacitively coupled multichip modules than for conductive modules. Savings accrue from eliminating mechanical connectors, backplane structures, processing equipment & steps, materials, and failure modes of all of these. The requisite equipment already exists in foundries, not just in dedicated MCM houses. Substrates may be thin or thick film, so long as smoothness and planarity match the density and decoupling requirements. For these reasons, any system comprising two or more die where pulse drivers and receivers can be designed in may be a candidate for capacitive coupling.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132568059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753576
C. N. Lazaridis, D. K. Flattery, W. J. Lautenberger, Y. Yamamoto, K. Imai
The excellent film properties given by BPDA/PPD make it a prime candidate for the dielectric material in MCM-D fabrications, and photodefinable versions offer the additional advantages of reduced labor and material costs. However, less than adequate adhesion to the preferred copper metallurgy coupled with prolonged development times may limit widespread adoption of this chemistry. Modifications to the BPDA/PPD backbone were made in a series of photodefinable polyimides prepared as the ionic salt precursors, and key performance and processing parameters were determined. Significant adhesion of the highly rigid BPDA/PPD backbone to copper metal was only achieved after substantial incorporation of either more flexible co-monomers, especially those containing fluorine substituents, or by incorporation of an assumed surface reactive, hydroxyl-substituted co-monomer. These modifications generally also resulted in reduced development times. Self-adhesion of polyimide to polyimide layers was optimized by using a partial cure process for the bottom polyimide layer, and appropriate cure temperatures were determined for each structure to prevent solvent-induced cracking of the bottom layer upon application of the top layer while retaining self-adhesion. Operable processing windows were found for several candidates which maximized adhesion and minimized cracking.
{"title":"Evaluation of Ionic Salt Photodefinable Polyimides As Mcm-D Dielectrics with Copper Metallization","authors":"C. N. Lazaridis, D. K. Flattery, W. J. Lautenberger, Y. Yamamoto, K. Imai","doi":"10.1109/ICMCM.1994.753576","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753576","url":null,"abstract":"The excellent film properties given by BPDA/PPD make it a prime candidate for the dielectric material in MCM-D fabrications, and photodefinable versions offer the additional advantages of reduced labor and material costs. However, less than adequate adhesion to the preferred copper metallurgy coupled with prolonged development times may limit widespread adoption of this chemistry. Modifications to the BPDA/PPD backbone were made in a series of photodefinable polyimides prepared as the ionic salt precursors, and key performance and processing parameters were determined. Significant adhesion of the highly rigid BPDA/PPD backbone to copper metal was only achieved after substantial incorporation of either more flexible co-monomers, especially those containing fluorine substituents, or by incorporation of an assumed surface reactive, hydroxyl-substituted co-monomer. These modifications generally also resulted in reduced development times. Self-adhesion of polyimide to polyimide layers was optimized by using a partial cure process for the bottom polyimide layer, and appropriate cure temperatures were determined for each structure to prevent solvent-induced cracking of the bottom layer upon application of the top layer while retaining self-adhesion. Operable processing windows were found for several candidates which maximized adhesion and minimized cracking.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114123246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753546
T. Houston, H. Heck, J. Knight
As the electronics packaging industry turns toward MCM-L technology to provide higher performance, lower cost packaging solutions the demands on laminate technology increase. Increasing chip I/O places more challenging requirements on the laminate wiring density. The design considerations that drive circuit density are I/O escape and global interconnect. This paper discusses IBM Endicott's approach to addressing the escape requirements using a set of hi density laminate technologies. IBM's laminate carriers were designed to target a spectrum of chip I/O requirements. Of particular interest is the ability to escape multiple rows of flip chip I/O. Access to multiple wiring layers is necessary when the I/O are arranged in an array or perimeter array configuration. The key to accessing internal laminate layers is the capability to provide fine pitch vias with small capture lands. This paper discusses the approaches that IBM Microelectronics takes to provide the appropriate laminate solution for a given chip I/O configuration. Specific examples are presented to show how chip I/O density affects the physical characteristics of the laminate technology. Additional factors that must be carefully weighed include material properties, processing requirements, electrical and thermal performance, and connection to the next level of packaging. IBM's laminate carriers were designed to target a spectrum of chip I/O requirements. Of particular interest is the ability to escape multiple rows of flip chip I/O. Access to multiple wiring layers is necessary when the I/O are arranged in an array or perimeter array configuration. The key to accessing internal laminate layers is the capability to provide fine pitch vias with small capture lands. This paper discusses the approaches that IBM Microelectronics takes to provide the appropriate laminate solution for a given chip I/O configuration. Specific examples are presented to show how chip I/O density affects the physical characteristics of the laminate technology. Additional factors that must be carefully weighed include material properties, processing requirements, electrical and thermal performance, and connection to the next level of packaging.
{"title":"An Application Strategy for Scm-L and Mcm-L Using High Density Laminate Technologies","authors":"T. Houston, H. Heck, J. Knight","doi":"10.1109/ICMCM.1994.753546","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753546","url":null,"abstract":"As the electronics packaging industry turns toward MCM-L technology to provide higher performance, lower cost packaging solutions the demands on laminate technology increase. Increasing chip I/O places more challenging requirements on the laminate wiring density. The design considerations that drive circuit density are I/O escape and global interconnect. This paper discusses IBM Endicott's approach to addressing the escape requirements using a set of hi density laminate technologies. IBM's laminate carriers were designed to target a spectrum of chip I/O requirements. Of particular interest is the ability to escape multiple rows of flip chip I/O. Access to multiple wiring layers is necessary when the I/O are arranged in an array or perimeter array configuration. The key to accessing internal laminate layers is the capability to provide fine pitch vias with small capture lands. This paper discusses the approaches that IBM Microelectronics takes to provide the appropriate laminate solution for a given chip I/O configuration. Specific examples are presented to show how chip I/O density affects the physical characteristics of the laminate technology. Additional factors that must be carefully weighed include material properties, processing requirements, electrical and thermal performance, and connection to the next level of packaging. IBM's laminate carriers were designed to target a spectrum of chip I/O requirements. Of particular interest is the ability to escape multiple rows of flip chip I/O. Access to multiple wiring layers is necessary when the I/O are arranged in an array or perimeter array configuration. The key to accessing internal laminate layers is the capability to provide fine pitch vias with small capture lands. This paper discusses the approaches that IBM Microelectronics takes to provide the appropriate laminate solution for a given chip I/O configuration. Specific examples are presented to show how chip I/O density affects the physical characteristics of the laminate technology. Additional factors that must be carefully weighed include material properties, processing requirements, electrical and thermal performance, and connection to the next level of packaging.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114172080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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