Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753527
G. Adema, C. Berry, N. Koopman, G. Rinne, E. Yung, I. Turlik
Flip chip interconnections provide the highest interconnection density possible which makes this technology very attractive for use with multichip modules. However, several factors have hindered the use of this technology. These factors include the availability of bumped wafers and the inability to test and bum-in bumped chips before they are assembled onto a multichip module. MCNC has addressed both of these concerns by establishing a wafer bumping facility and by developing a method for the test and burn-in of bare die. The solder bump formation is based upon an electroplating process. The test and burn-in of bumped chips is accomplished using a unique process which utilizes a temporary metallurgical attachment to a test substrate. These processes are described in detail in the following sections.
{"title":"Flip Chip Technology: A Method for Providing Known Good Die with High Density Interconnections","authors":"G. Adema, C. Berry, N. Koopman, G. Rinne, E. Yung, I. Turlik","doi":"10.1109/ICMCM.1994.753527","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753527","url":null,"abstract":"Flip chip interconnections provide the highest interconnection density possible which makes this technology very attractive for use with multichip modules. However, several factors have hindered the use of this technology. These factors include the availability of bumped wafers and the inability to test and bum-in bumped chips before they are assembled onto a multichip module. MCNC has addressed both of these concerns by establishing a wafer bumping facility and by developing a method for the test and burn-in of bare die. The solder bump formation is based upon an electroplating process. The test and burn-in of bumped chips is accomplished using a unique process which utilizes a temporary metallurgical attachment to a test substrate. These processes are described in detail in the following sections.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123238558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753535
P. Trask, V. A. Pillai
GM Hughes Electronics Company has been researching approaches to low cost manufacturing of Multichip Modules (MCM) for several years. Hughes engineers believe that the acceptance of MCM-D technology, and the advantages in performance and density it affords, will be accelerated once the cost is lowered below a level which will make it competitive with other MCM technologies. The performance benefits of MCM-D are well known, but as yet do not fully offset the perceived cost disadvantage which prevents its use in commercial products. Military customers need the volume generated by commercial applications to take advantage of the Cost Function Curve. The analysis of substrate cost as a function of production volume and the correlation to numbers of substrates per manufacturing unit, or panel, size will be discussed and the effects of defect density control emphasized Hughes has an IR&D project underway to define the technology, equipment, and process breakthroughs needed to commercialize MCM-D, and to demonstrate the cost effectiveness of fabricating HDMI/sup TM/ (High Density Multichip Interconnect) substrates on large panels. Hughes is currently building production quantites of 1.8-by-3.8 inch, densely routed substrate designs for military systems on alumina, silicon, and aluminum nitride ISO mm wafers. Hughes personnel believe that the published ARPA (Advanced Research Projects Agency) goals of a factor of ten reduction in substrate cost and a factor of 10 increase in substrate capacity are achievable using the large panel format. The progress to date in this effort will be discussed, and the plans and problems discussed
{"title":"Large Format Mcm-D Processing Adaptation of the Hughes Hdmi/sup TM/ Process to Large Format Mcm-D: Options, Problems, Results to Date","authors":"P. Trask, V. A. Pillai","doi":"10.1109/ICMCM.1994.753535","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753535","url":null,"abstract":"GM Hughes Electronics Company has been researching approaches to low cost manufacturing of Multichip Modules (MCM) for several years. Hughes engineers believe that the acceptance of MCM-D technology, and the advantages in performance and density it affords, will be accelerated once the cost is lowered below a level which will make it competitive with other MCM technologies. The performance benefits of MCM-D are well known, but as yet do not fully offset the perceived cost disadvantage which prevents its use in commercial products. Military customers need the volume generated by commercial applications to take advantage of the Cost Function Curve. The analysis of substrate cost as a function of production volume and the correlation to numbers of substrates per manufacturing unit, or panel, size will be discussed and the effects of defect density control emphasized Hughes has an IR&D project underway to define the technology, equipment, and process breakthroughs needed to commercialize MCM-D, and to demonstrate the cost effectiveness of fabricating HDMI/sup TM/ (High Density Multichip Interconnect) substrates on large panels. Hughes is currently building production quantites of 1.8-by-3.8 inch, densely routed substrate designs for military systems on alumina, silicon, and aluminum nitride ISO mm wafers. Hughes personnel believe that the published ARPA (Advanced Research Projects Agency) goals of a factor of ten reduction in substrate cost and a factor of 10 increase in substrate capacity are achievable using the large panel format. The progress to date in this effort will be discussed, and the plans and problems discussed","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131722845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753571
M. Begay, R. Cantwell
Since the recent advent of the MultiChip Module (MCM) technology options, many potential MCM customers are grappling on how to partition a new or existing system design to utilize the benefits of MCMs. In addition to the design issues, customers are having to look beyond the traditional board design cost models to justify the higher costs of MCMs over the single chip package options. These factors greatly influence the decision whether to design or redesign a system with an MCM. Unless the customer can readily determine whether cost savings or parity can be achieved with a MCM, the decision to use an MCM is either postponed or dropped as an alternative. This paper will outline the design and cost methods that were used in a telecommunication switching equipment application. This application substituted a multi-layer, four chip, 160 lead MCM-L PQFP (plastic quad flat pack) package in place of four single chip packages. The methods used in this case study delves beyond the traditional single chip versus multichip package comparisons to justify the use of a MCM-L package as a cost effective alternative to single chip semiconductor devices.
{"title":"MCM-L Cost Model & Application Case Study","authors":"M. Begay, R. Cantwell","doi":"10.1109/ICMCM.1994.753571","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753571","url":null,"abstract":"Since the recent advent of the MultiChip Module (MCM) technology options, many potential MCM customers are grappling on how to partition a new or existing system design to utilize the benefits of MCMs. In addition to the design issues, customers are having to look beyond the traditional board design cost models to justify the higher costs of MCMs over the single chip package options. These factors greatly influence the decision whether to design or redesign a system with an MCM. Unless the customer can readily determine whether cost savings or parity can be achieved with a MCM, the decision to use an MCM is either postponed or dropped as an alternative. This paper will outline the design and cost methods that were used in a telecommunication switching equipment application. This application substituted a multi-layer, four chip, 160 lead MCM-L PQFP (plastic quad flat pack) package in place of four single chip packages. The methods used in this case study delves beyond the traditional single chip versus multichip package comparisons to justify the use of a MCM-L package as a cost effective alternative to single chip semiconductor devices.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132609191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753587
L. Gates, B.E. Steckler
This report presents the results of environmental testing of sealed chip-on-board (SCOB) memory circuits. Samples consisted of four SRAM chips mounted on fine line PWBs (MCM-L technology). A complete design of experiments (DOE) matrix included two PWB sources, three die attachment adhesives, one moisture passivation coating (plasma enhanced, chemical vapor deposited silicon nitride), and two encapsulants (a silicone gel and an epoxy glob-top material). DOE was also employed to set up the environmental test scheme using tests selected from MIL-STD-883, and HAST. A set of conventional thin film hybrid circuit samples packaged in hermetic ceramic packages was included in the environmental test scheme as a control. Failure analyses of test samples and conclusions on performance of adhesives and protective coatings are presented.
{"title":"Environmental Performance of Sealed Chip-On-Board (scob) Memory Circuits","authors":"L. Gates, B.E. Steckler","doi":"10.1109/ICMCM.1994.753587","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753587","url":null,"abstract":"This report presents the results of environmental testing of sealed chip-on-board (SCOB) memory circuits. Samples consisted of four SRAM chips mounted on fine line PWBs (MCM-L technology). A complete design of experiments (DOE) matrix included two PWB sources, three die attachment adhesives, one moisture passivation coating (plasma enhanced, chemical vapor deposited silicon nitride), and two encapsulants (a silicone gel and an epoxy glob-top material). DOE was also employed to set up the environmental test scheme using tests selected from MIL-STD-883, and HAST. A set of conventional thin film hybrid circuit samples packaged in hermetic ceramic packages was included in the environmental test scheme as a control. Failure analyses of test samples and conclusions on performance of adhesives and protective coatings are presented.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132850691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753579
J.P. Droguet
Description of the process, based on copper conductors and polyimid as a dielectric* (1) Description of the industrial pilot (2) Process characterization (3) Let us briefly remind, as described by fig. 1 hereunder, that the technology allows the realization of a multilayer stack, with up to five levels of conductors for power, ground, two signal layers and a top layer, for components attach and interconnect.
{"title":"An Mcm-D Foundry from Copper/polyimid Tfml Bare Substrate to Multichif Modules","authors":"J.P. Droguet","doi":"10.1109/ICMCM.1994.753579","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753579","url":null,"abstract":"Description of the process, based on copper conductors and polyimid as a dielectric* (1) Description of the industrial pilot (2) Process characterization (3) Let us briefly remind, as described by fig. 1 hereunder, that the technology allows the realization of a multilayer stack, with up to five levels of conductors for power, ground, two signal layers and a top layer, for components attach and interconnect.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133272309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753616
D. R. Schroeder, L.J. Rexing
The design guidelines currently being incorporated in the design and fabrication of LTCC MCM's will be reviewed and compared to MCM-L and MCM-D design guidelines. Several examples of complex MCM's will be presented ranging in size up to 3" x 3" incorporating wire bonding as well as tab bonding. LTCC MCM technology has been established as a flexible cost effective advanced packaging concept for harsh environments.
{"title":"Ltcc Mcm Technology for Military Environments","authors":"D. R. Schroeder, L.J. Rexing","doi":"10.1109/ICMCM.1994.753616","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753616","url":null,"abstract":"The design guidelines currently being incorporated in the design and fabrication of LTCC MCM's will be reviewed and compared to MCM-L and MCM-D design guidelines. Several examples of complex MCM's will be presented ranging in size up to 3\" x 3\" incorporating wire bonding as well as tab bonding. LTCC MCM technology has been established as a flexible cost effective advanced packaging concept for harsh environments.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124658833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753534
G. White, E. Perfecto, T. Demercurio, D. Mcherron, T. Redmond, M. Norcott
The IBM Microelectronics Division at East Fishkill has recently demonstrated the fabrication of thin films for MCM-D on large area panels, 300 mm x 300 mm in size. Fabrication of the thin films was accomplished on IBM's 300 mm development Line using immersion development of photosensitive polyimide for via formation and electrolytic plating to define wiring and terminal metal Levels. One plane pair of thin films was constructed on Corning glass 7059 panels for 35 micron Lines on 85 micron pitch. In addition, two metal - dielectric Levels with 13 um lines on 25 um pitch has also been demonstrated. The 25 um pitch represents the most aggressive groundrule practiced in electronic packaging today. The successful production of electrically good substrates at a high yield from a 300 mm panel provides a gateway to significant cost reductions of future MCM-D products from IBM. In this paper we will discuss the processes and equipment used to fabricate two different test vehicles, as welt as some of cost and yield considerations associated with Large area panel processing for MCM-D packages.
位于East Fishkill的IBM微电子部门最近展示了在300 mm x 300 mm尺寸的大面积面板上制造MCM-D薄膜。薄膜的制造是在IBM的300mm显影线上完成的，使用光敏聚酰亚胺的浸没显影，用于通孔形成和电解电镀，以定义布线和终端金属水平。在康宁7059玻璃面板上构建了一对平面薄膜，用于85微米间距的35微米线。此外，还证明了在25um间距上具有13um线的两个金属介电电平。25微米的间距代表了当今电子封装中最具侵略性的接地规则。从300毫米面板上成功生产出高成品率的良好电基板，为IBM未来MCM-D产品的显着降低成本提供了一个途径。在本文中，我们将讨论用于制造两种不同测试车辆的工艺和设备，以及与MCM-D封装的大面积面板加工相关的一些成本和良率考虑因素。
{"title":"Large Format Fabrication a Practical Approach to Low Cost MCM-D","authors":"G. White, E. Perfecto, T. Demercurio, D. Mcherron, T. Redmond, M. Norcott","doi":"10.1109/ICMCM.1994.753534","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753534","url":null,"abstract":"The IBM Microelectronics Division at East Fishkill has recently demonstrated the fabrication of thin films for MCM-D on large area panels, 300 mm x 300 mm in size. Fabrication of the thin films was accomplished on IBM's 300 mm development Line using immersion development of photosensitive polyimide for via formation and electrolytic plating to define wiring and terminal metal Levels. One plane pair of thin films was constructed on Corning glass 7059 panels for 35 micron Lines on 85 micron pitch. In addition, two metal - dielectric Levels with 13 um lines on 25 um pitch has also been demonstrated. The 25 um pitch represents the most aggressive groundrule practiced in electronic packaging today. The successful production of electrically good substrates at a high yield from a 300 mm panel provides a gateway to significant cost reductions of future MCM-D products from IBM. In this paper we will discuss the processes and equipment used to fabricate two different test vehicles, as welt as some of cost and yield considerations associated with Large area panel processing for MCM-D packages.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126493818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753599
T. Ju, Y.C. Lee
The effects of manufacturing variations on the reliability of solder joints between a ceramic ball grid array (BGA) package and a printed wiring board (PWB) are investigated. Three manufacturing parameters tinder consideration are 1) solder volume, 2) solder height, and 3) solder pad size. To study the manufacturing effects, a solder joint profile model is derived. Then the maximum strain is calculated, and the fatigue life of the solder joint is predicted. The accuracy of the solder profile model is verified by comparing its predicted profiles with experimental results. The fatigue life of a solder joint is estimated by the Coffin-Manson's relation. The calculations show that the manufacturing variations change the joint profile, and subsequently affect the fatigue life. The solder joints formed may have convex, cylindrical and concave profiles. The concave solder joints are preferred, which have long fatigue lives and are less sensitive to the manufacturing variations. For the convex solder joints, their fatigue lives are strongly affected by the joint height variation and by the combined effects of solder volume and pad size.
{"title":"Effects of Ceramic Ball-Grid-Array Package's Manufacturing Variations on Solder Joint Reliability","authors":"T. Ju, Y.C. Lee","doi":"10.1109/ICMCM.1994.753599","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753599","url":null,"abstract":"The effects of manufacturing variations on the reliability of solder joints between a ceramic ball grid array (BGA) package and a printed wiring board (PWB) are investigated. Three manufacturing parameters tinder consideration are 1) solder volume, 2) solder height, and 3) solder pad size. To study the manufacturing effects, a solder joint profile model is derived. Then the maximum strain is calculated, and the fatigue life of the solder joint is predicted. The accuracy of the solder profile model is verified by comparing its predicted profiles with experimental results. The fatigue life of a solder joint is estimated by the Coffin-Manson's relation. The calculations show that the manufacturing variations change the joint profile, and subsequently affect the fatigue life. The solder joints formed may have convex, cylindrical and concave profiles. The concave solder joints are preferred, which have long fatigue lives and are less sensitive to the manufacturing variations. For the convex solder joints, their fatigue lives are strongly affected by the joint height variation and by the combined effects of solder volume and pad size.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"12 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115942082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753580
R. Aschenbrenner, A. Ostmann, U. Beutler, J. Simon, H. Reichl
An electroless bumping method was developed both for Rip-Chip and TAB applications. Electroless Ni/Cu plating is a maskless low cost approach to bumping directly on aluminum bondpads. An immersion tin layer for coating and soldering is plated on the copper. Due to the high alkalinity (pH>12) of electroless Cu baths, a thick Ni layer of about 7 P/spl mu/m is required on the aluminum for sealing. A shear strength of 180 cN and a contact resistance of less than 2 m/spl omega/ for the bumps were obtained. Because of the high hardness of nickel, conventional gang bonding techniques are not applicable. The hardness of electroless copper is about 200 mHV25 and after annealing in the range of 130-150 mHV25. Thermocompression gang bonding of Au plated tape to the Ni/Cu/Sn metallization was carded out. The average pull strength was 50 cN. Further investigations of the deposited copper are the influence of the size and electroless solder plating.
{"title":"Electroless Nickel/Copper Plating as a New Bump Metallization","authors":"R. Aschenbrenner, A. Ostmann, U. Beutler, J. Simon, H. Reichl","doi":"10.1109/ICMCM.1994.753580","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753580","url":null,"abstract":"An electroless bumping method was developed both for Rip-Chip and TAB applications. Electroless Ni/Cu plating is a maskless low cost approach to bumping directly on aluminum bondpads. An immersion tin layer for coating and soldering is plated on the copper. Due to the high alkalinity (pH>12) of electroless Cu baths, a thick Ni layer of about 7 P/spl mu/m is required on the aluminum for sealing. A shear strength of 180 cN and a contact resistance of less than 2 m/spl omega/ for the bumps were obtained. Because of the high hardness of nickel, conventional gang bonding techniques are not applicable. The hardness of electroless copper is about 200 mHV25 and after annealing in the range of 130-150 mHV25. Thermocompression gang bonding of Au plated tape to the Ni/Cu/Sn metallization was carded out. The average pull strength was 50 cN. Further investigations of the deposited copper are the influence of the size and electroless solder plating.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"20 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131133827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753601
D. R. Banks, T.E. Bunette, R. Gerke, E. Mammo, S. Mattay
Surface-mountable ceramic ball grid array (CBGA) packages have proven to be attractive in a variety of applications as designers seek to maximize electrical performance, reduce card real estate, and improve manufacturing process yields. In support of the PowerPC/sup TM/ family of microprocessors, 21mm CBGA packages (256 leads) were used to evaluate two different ball metalturgies--90/10 Pb/Sn and 62/36/2 Sn/Pb/Ag. Test modules were assembled to printed circuit cards and cycled at 0 to 100/spl deg/C and -40 to 125/spl deg/C. Ball attach techniques and module-to-card assembly processes are described, including screening, placement, and reflow. Failure mechanisms and reliability are discussed for both metallurgies.
{"title":"Reliability Comparison of Two Metallurgies for Ceramic Ball Grid Array","authors":"D. R. Banks, T.E. Bunette, R. Gerke, E. Mammo, S. Mattay","doi":"10.1109/ICMCM.1994.753601","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753601","url":null,"abstract":"Surface-mountable ceramic ball grid array (CBGA) packages have proven to be attractive in a variety of applications as designers seek to maximize electrical performance, reduce card real estate, and improve manufacturing process yields. In support of the PowerPC/sup TM/ family of microprocessors, 21mm CBGA packages (256 leads) were used to evaluate two different ball metalturgies--90/10 Pb/Sn and 62/36/2 Sn/Pb/Ag. Test modules were assembled to printed circuit cards and cycled at 0 to 100/spl deg/C and -40 to 125/spl deg/C. Ball attach techniques and module-to-card assembly processes are described, including screening, placement, and reflow. Failure mechanisms and reliability are discussed for both metallurgies.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115322561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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