Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753549
C. V. Reynolds, L. Schaper
High volume applications of complex MCMs are slow to enter commercial production. There are two major interrelated technological barriers, namely the availability of reliable and cost and performance effective known good interconnection substrates and the commercial availability of known good die (KGD). This paper reports on an application of the, Interconnected Mesh Power System (IMPS) *[1] interconnect topology in an MCM-L based design to achieve the same interconnect and electrical functionality as that accomplished with four layers. This was accomplished using the two layer topology with a third layer dedicated to mounting the caps.
{"title":"Interconnected Mesh Power System, (IMPS) A Packaging and Interconnection Application","authors":"C. V. Reynolds, L. Schaper","doi":"10.1109/ICMCM.1994.753549","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753549","url":null,"abstract":"High volume applications of complex MCMs are slow to enter commercial production. There are two major interrelated technological barriers, namely the availability of reliable and cost and performance effective known good interconnection substrates and the commercial availability of known good die (KGD). This paper reports on an application of the, Interconnected Mesh Power System (IMPS) *[1] interconnect topology in an MCM-L based design to achieve the same interconnect and electrical functionality as that accomplished with four layers. This was accomplished using the two layer topology with a third layer dedicated to mounting the caps.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117301816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753539
M. Yamada, Y. Otsuki, T. Kikuchi, H. Shibuya
Multichip module (MCM) technology has been expected for high speed and high density packaging. Authors have developed an 8 x 8 ATM switching module with clock speed of 622 Mb/s and power consumption of 60 watts by using MCM-C technology with low temperature co-fired ceramic (LTCC) substrate. This paper will discuss MCM packaging technologies for an ATM switching module.
{"title":"An ATM Switching Module using MCM-C Technology","authors":"M. Yamada, Y. Otsuki, T. Kikuchi, H. Shibuya","doi":"10.1109/ICMCM.1994.753539","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753539","url":null,"abstract":"Multichip module (MCM) technology has been expected for high speed and high density packaging. Authors have developed an 8 x 8 ATM switching module with clock speed of 622 Mb/s and power consumption of 60 watts by using MCM-C technology with low temperature co-fired ceramic (LTCC) substrate. This paper will discuss MCM packaging technologies for an ATM switching module.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122050062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753605
R. Goyal
For useful signal integrity analysis, availability of timely and accurate silicon models is extremely important. Nonlinear voltage controlled current sources (vccs), current controlled voltage sources (ccvs), voltage controlled voltage sources (vcvs) and current controlled current sources (cccs), available in Spice can be used in describing these device models. With this approach, one can represent the macro- models of driver, receiver, load and termination using basic controlled sources as Spice primitives, without revealing process related proprietary information.
{"title":"Accurate I/O Models for High Speed Digital Design Using Spice Controlled Sources","authors":"R. Goyal","doi":"10.1109/ICMCM.1994.753605","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753605","url":null,"abstract":"For useful signal integrity analysis, availability of timely and accurate silicon models is extremely important. Nonlinear voltage controlled current sources (vccs), current controlled voltage sources (ccvs), voltage controlled voltage sources (vcvs) and current controlled current sources (cccs), available in Spice can be used in describing these device models. With this approach, one can represent the macro- models of driver, receiver, load and termination using basic controlled sources as Spice primitives, without revealing process related proprietary information.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125172739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753618
D. Peterson, J. Sweet, D.D. Andaleon, R. F. Renzi, D. Johnson
A single substrate intended for a 3-dimensional (3D) edge-cooled multichip module (MCM) has been built and thermally tested. The substrate, with dimensions 1.9 in. by 2 in., is mounted in a fluid cooled block at one end. To test this cooling architecture and verify the accuracy of thermal models, we constructed thermal test modules using alumina (Al/sub 2/O/sub 3/), aluminum nitride (AIN), and CVD diamond substrate materials. Each module was populated with an array of 16 Sandia ATC03 test chips with resistive heaters and temperature sensing diode thermometers. Comparative measurements of the 3 substrates were made in which the top row of 4 die were heated at 5 W each for a total of 20 W. The maximum temperature differences between the heated die and the interface with the cold chuck, /spl Delta/T/sub JS/, were 24, 126, and 265/spl deg/C for diamond, AIN and Al/sub 2/O/sub 3/, respectively. Measurements on the diamond thermal test module, uniformly heated at a total power of 45 W, gave a measured substrate-to-sink temperature of /spl Delta/T /spl AP/ 20/spl deg/C. An extrapolation of our experimental data indicates that the diamond edge-cooled substrate could dissipate a total power /spl AP/ 192 W for a maximum junction-to-ambient temperature of /spl Delta/T/sub JA/ /spl AP/ 124/spl deg/C. If multiple substrates were 3 mounted in the fluid cooled block, spaced 0.075 in. apart, the volumetric power density would be about 850 W/in/sup 3/.
{"title":"Demonstration of a High Heat Removal Cvd Diamond Substrate Edge-Cooled Multichip Module","authors":"D. Peterson, J. Sweet, D.D. Andaleon, R. F. Renzi, D. Johnson","doi":"10.1109/ICMCM.1994.753618","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753618","url":null,"abstract":"A single substrate intended for a 3-dimensional (3D) edge-cooled multichip module (MCM) has been built and thermally tested. The substrate, with dimensions 1.9 in. by 2 in., is mounted in a fluid cooled block at one end. To test this cooling architecture and verify the accuracy of thermal models, we constructed thermal test modules using alumina (Al/sub 2/O/sub 3/), aluminum nitride (AIN), and CVD diamond substrate materials. Each module was populated with an array of 16 Sandia ATC03 test chips with resistive heaters and temperature sensing diode thermometers. Comparative measurements of the 3 substrates were made in which the top row of 4 die were heated at 5 W each for a total of 20 W. The maximum temperature differences between the heated die and the interface with the cold chuck, /spl Delta/T/sub JS/, were 24, 126, and 265/spl deg/C for diamond, AIN and Al/sub 2/O/sub 3/, respectively. Measurements on the diamond thermal test module, uniformly heated at a total power of 45 W, gave a measured substrate-to-sink temperature of /spl Delta/T /spl AP/ 20/spl deg/C. An extrapolation of our experimental data indicates that the diamond edge-cooled substrate could dissipate a total power /spl AP/ 192 W for a maximum junction-to-ambient temperature of /spl Delta/T/sub JA/ /spl AP/ 124/spl deg/C. If multiple substrates were 3 mounted in the fluid cooled block, spaced 0.075 in. apart, the volumetric power density would be about 850 W/in/sup 3/.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129613060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753526
D. Tuckerman, B. Jarvis, Chang-Ming Lin, P. Patel, M. Hunt
A new wafer-level bum-in method is presented. The method incorporates a silicon "bum-in substrate" fabricated using MCM-D substrate technology, and includes integral isolation resistors. The novel, Si wafer-to Si wafer pressure contact technology is based on deformable solder bumps and is functional in a high temperature burn-in environment, immune to thermal expansion mismatch problems, reusable, and does not damage or contaminate bond pads. The method is suitable for high-volume production and can reduce bum-in costs, even for chips that are ultimately destined for single-chip packages.
{"title":"A Cost-Effective Wafer-Level Burn-In Technology","authors":"D. Tuckerman, B. Jarvis, Chang-Ming Lin, P. Patel, M. Hunt","doi":"10.1109/ICMCM.1994.753526","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753526","url":null,"abstract":"A new wafer-level bum-in method is presented. The method incorporates a silicon \"bum-in substrate\" fabricated using MCM-D substrate technology, and includes integral isolation resistors. The novel, Si wafer-to Si wafer pressure contact technology is based on deformable solder bumps and is functional in a high temperature burn-in environment, immune to thermal expansion mismatch problems, reusable, and does not damage or contaminate bond pads. The method is suitable for high-volume production and can reduce bum-in costs, even for chips that are ultimately destined for single-chip packages.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128279059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753577
J. Morrison, T. Tessier, B. Gu
Recently, a Transverse Excited Atmospheric (TEA) CO/sub 2/ laser technology has been developed-for the micro-machining of Was in non-reinforced glass laminates. This system has been designed to accommodate the large panel sizes associated with PW8 processing. The salient features of this modified CO/sub 2/ laser technology are summarized. A joint Lumonics / Motorola study was carried out to assess the applicability of this laser processing technology for use in higher density PWB and MCM-L substrate processing and its compatibility with currently available classes of dielectrics currently used in high density interconnect applications. A lox improvement in cycle time / throughput over our existing raster scanning laser ablation process has been demonstrated.
{"title":"A Large Format Modified TEA CO/sub 2/ Laser Based Process for Cost Effective Small Via Generation","authors":"J. Morrison, T. Tessier, B. Gu","doi":"10.1109/ICMCM.1994.753577","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753577","url":null,"abstract":"Recently, a Transverse Excited Atmospheric (TEA) CO/sub 2/ laser technology has been developed-for the micro-machining of Was in non-reinforced glass laminates. This system has been designed to accommodate the large panel sizes associated with PW8 processing. The salient features of this modified CO/sub 2/ laser technology are summarized. A joint Lumonics / Motorola study was carried out to assess the applicability of this laser processing technology for use in higher density PWB and MCM-L substrate processing and its compatibility with currently available classes of dielectrics currently used in high density interconnect applications. A lox improvement in cycle time / throughput over our existing raster scanning laser ablation process has been demonstrated.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128479823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753615
L. Arndt
Military applications for MCMs often require non-standard form factors tailored to fit the unique configurations of military systems. Size and weight requirements may further restrict the use of standard packaging and interconnect methods such as the typical SMT packages mounted on PWBs and backplanes. Cost and design cycle time considerations however argue in favor of standard configurations which can be used in multiple applications without incurring significant NRE costs or risks for each new application. An MCM approach will be presented which uses polymer thin film HDI deposited onto an LTCC substrate to provide a flexible form factor and a very high functional density, while maintaining the advantages of a standard, proven architecture and a fixed HDI layout. The HDI provides all internal chip-to-chip interconnect, while the LTCC acts as the package floor, redistributes primary I/O, and provides physical conformance to each target system. Hermetic sealing of the chips and HDI is accomplished by routinely brazing a Kovar seal ring onto the LTCC and subsequently seam welding a Kovar lid into place. This configuration also provides an I/O pad array interface which tends itself well to direct 3-D stacking of multiple MCMs in a "building block" fashion using only connectors but no PWB or backplane. MCMs have been successfully fabricated at two different HDI foundries, using Alumina substrates, while LTCC / HDI materials and processing techniques were matured. Testing of these MCMs has been successful with demonstrated performance superior to the PWB version of the circuit.
{"title":"A Large Area, 3-D Stackable, Mcm-D on C Signal Processor","authors":"L. Arndt","doi":"10.1109/ICMCM.1994.753615","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753615","url":null,"abstract":"Military applications for MCMs often require non-standard form factors tailored to fit the unique configurations of military systems. Size and weight requirements may further restrict the use of standard packaging and interconnect methods such as the typical SMT packages mounted on PWBs and backplanes. Cost and design cycle time considerations however argue in favor of standard configurations which can be used in multiple applications without incurring significant NRE costs or risks for each new application. An MCM approach will be presented which uses polymer thin film HDI deposited onto an LTCC substrate to provide a flexible form factor and a very high functional density, while maintaining the advantages of a standard, proven architecture and a fixed HDI layout. The HDI provides all internal chip-to-chip interconnect, while the LTCC acts as the package floor, redistributes primary I/O, and provides physical conformance to each target system. Hermetic sealing of the chips and HDI is accomplished by routinely brazing a Kovar seal ring onto the LTCC and subsequently seam welding a Kovar lid into place. This configuration also provides an I/O pad array interface which tends itself well to direct 3-D stacking of multiple MCMs in a \"building block\" fashion using only connectors but no PWB or backplane. MCMs have been successfully fabricated at two different HDI foundries, using Alumina substrates, while LTCC / HDI materials and processing techniques were matured. Testing of these MCMs has been successful with demonstrated performance superior to the PWB version of the circuit.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129912653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753598
P. Danner
With the advent of greater density assembly, increased i/o connections and higher power dissipation requirements, a new method of producing cost effective high pin count packages is being demonstrated. Ball grid array packages have been around for several years, both in ceramic and laminate technologies and are now being accepted as a viable packaging alternative. This discussion will describe a low cost method to combine ceramic multichip module technology with ball grid array assembly. The methods are unique in the placement of the solder spheres, the almost spherical dimensions of the connections and the extreme ruggedness of the resulting package. The improved thermal characteristics, ease of assembly and low cost will make this packaging technique a practical solution for todays demands.
{"title":"Ball Grid Array Ceramic Packages","authors":"P. Danner","doi":"10.1109/ICMCM.1994.753598","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753598","url":null,"abstract":"With the advent of greater density assembly, increased i/o connections and higher power dissipation requirements, a new method of producing cost effective high pin count packages is being demonstrated. Ball grid array packages have been around for several years, both in ceramic and laminate technologies and are now being accepted as a viable packaging alternative. This discussion will describe a low cost method to combine ceramic multichip module technology with ball grid array assembly. The methods are unique in the placement of the solder spheres, the almost spherical dimensions of the connections and the extreme ruggedness of the resulting package. The improved thermal characteristics, ease of assembly and low cost will make this packaging technique a practical solution for todays demands.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127332904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753524
L. Prokopchak, J. Wrenn
Multichip modules(MCMs) are a major growth market in the IC industry. However, a problem hindering the widespread use of MCM technology is the inability of the MCM manufacturer to obtain bare die with the same level of reliability as those die in packaged devices. If the MCM is determined to be faulty after burn-in and test, it is difficult and expensive to repair. In fact, it can be difficult to isolate the individual chips during bum-in at the module level, making the task of determining the failing chip more laborious. One contributing factor to these failures is the lack of burn-in of the die before the MCM is assembled. If every chip on an 8-chip module has a 4% probability of failing(common for state-of-the-art devices), the module has a 28% chance of failing. This calculation is derived from the equation Pp = (l-P(f))" where; P = probability, p = passing, f = failing, and n = number of die per module. The goal is to deliver to the user known-good-die (KGD) with the same level of electrical test and burn-in reliability as currently available at the package level.
{"title":"Development of a Burn-in and Test Process for Producing Known-Good-Die","authors":"L. Prokopchak, J. Wrenn","doi":"10.1109/ICMCM.1994.753524","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753524","url":null,"abstract":"Multichip modules(MCMs) are a major growth market in the IC industry. However, a problem hindering the widespread use of MCM technology is the inability of the MCM manufacturer to obtain bare die with the same level of reliability as those die in packaged devices. If the MCM is determined to be faulty after burn-in and test, it is difficult and expensive to repair. In fact, it can be difficult to isolate the individual chips during bum-in at the module level, making the task of determining the failing chip more laborious. One contributing factor to these failures is the lack of burn-in of the die before the MCM is assembled. If every chip on an 8-chip module has a 4% probability of failing(common for state-of-the-art devices), the module has a 28% chance of failing. This calculation is derived from the equation Pp = (l-P(f))\" where; P = probability, p = passing, f = failing, and n = number of die per module. The goal is to deliver to the user known-good-die (KGD) with the same level of electrical test and burn-in reliability as currently available at the package level.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131874717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753522
W. Kim, S. Lee, I. Hyun, K. Lee, J.M. Park
Known good die is an enabling technology for the application on the wide range of electronic industry especially for multichip module application. Wafer level burn-in is an ideal methodology to produce KGD's, but there needs a considerable amount of time until it emerges to a viable process which should be practical and economical. In the mean time, die level burn-in becomes a common method to produce KGD for its practical application as several different types of burn-in carriers are commercially available. In this paper, a new cost effective process to produce KGD is proposed. Conventional wire bonding method was applied for electrical interconnection from chip to printed circuit board, designed for testing several chip together with a multichip holder. A proprietary tool was applied to cut gold wire from bond pad. Mass production of KGD was possible with the new process. Engineering samples, I Meg slow static RAM, produced by the new process showed excellent reliability and provided a significant amount of engineering data. It is believed that the new process can produce known good bare die most economically among existing die level burn-in methods. Because it used well established wire bonding technology rather than burn-in carrier to provide temporary contact between chip to test equipment which quite often proved unreliable in terms of contact resistance and can be used only limited number of times.
{"title":"A New Approach to Produce Cost-effective Known Good Die","authors":"W. Kim, S. Lee, I. Hyun, K. Lee, J.M. Park","doi":"10.1109/ICMCM.1994.753522","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753522","url":null,"abstract":"Known good die is an enabling technology for the application on the wide range of electronic industry especially for multichip module application. Wafer level burn-in is an ideal methodology to produce KGD's, but there needs a considerable amount of time until it emerges to a viable process which should be practical and economical. In the mean time, die level burn-in becomes a common method to produce KGD for its practical application as several different types of burn-in carriers are commercially available. In this paper, a new cost effective process to produce KGD is proposed. Conventional wire bonding method was applied for electrical interconnection from chip to printed circuit board, designed for testing several chip together with a multichip holder. A proprietary tool was applied to cut gold wire from bond pad. Mass production of KGD was possible with the new process. Engineering samples, I Meg slow static RAM, produced by the new process showed excellent reliability and provided a significant amount of engineering data. It is believed that the new process can produce known good bare die most economically among existing die level burn-in methods. Because it used well established wire bonding technology rather than burn-in carrier to provide temporary contact between chip to test equipment which quite often proved unreliable in terms of contact resistance and can be used only limited number of times.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127931931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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