Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292139
Han Gao, Shan-xiang Hu
The design implements a P-band broadband digital array module, mainly composed of eight independent analog transceiver channels, integrated digital transceiver channel, distributed power supply, clock dividers and photoelectric converter, etc. The design adopts the structure of double-sided layout. The front and back sides are arranged with the same functional modules. The whole structure uses air cooling to dissipate heat. With the three-dimensional layout, the structure can effectively save space and reduce the size and weight of DAM. The module is characterized by high integration, high reliability and easy maintenance and so on.
{"title":"Design of a P-Band Broadband Digital Array Module","authors":"Han Gao, Shan-xiang Hu","doi":"10.1109/ICICM50929.2020.9292139","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292139","url":null,"abstract":"The design implements a P-band broadband digital array module, mainly composed of eight independent analog transceiver channels, integrated digital transceiver channel, distributed power supply, clock dividers and photoelectric converter, etc. The design adopts the structure of double-sided layout. The front and back sides are arranged with the same functional modules. The whole structure uses air cooling to dissipate heat. With the three-dimensional layout, the structure can effectively save space and reduce the size and weight of DAM. The module is characterized by high integration, high reliability and easy maintenance and so on.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125111374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292239
Shiwei Xing, Chenjian Wu
A multi-input neuron circuit with high-precision Sigmoid activation function (AF) is presented in this paper. The proposed circuit composed of input signal weighting circuit, current-voltage conversion circuit, and Sigmoid AF fitting circuit. Designed circuit can fit Sigmoid function based on the current-voltage relationship of differential pairs. The circuit is simulated in TSMC 0.18 um CMOS technology. The post-simulation shows that the error between the output of Sigmoid AF fitting circuit and the ideal Sigmoid function is 1.76%. The area of the layout is $375 mu m times 238 mu m$. The maximum error caused by noise in the output of the circuit is $80 pA/sqrt{Hz}$.
提出了一种具有高精度Sigmoid激活函数的多输入神经元电路。该电路由输入信号加权电路、电流-电压转换电路和Sigmoid AF拟合电路组成。设计的电路可以根据差分对的电流-电压关系拟合Sigmoid函数。采用台积电0.18 um CMOS技术对电路进行了仿真。后置仿真表明，Sigmoid AF拟合电路输出与理想Sigmoid函数的误差为1.76%. The area of the layout is $375 mu m times 238 mu m$. The maximum error caused by noise in the output of the circuit is $80 pA/sqrt{Hz}$.
{"title":"Implementation of A Neuron Using Sigmoid Activation Function with CMOS","authors":"Shiwei Xing, Chenjian Wu","doi":"10.1109/ICICM50929.2020.9292239","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292239","url":null,"abstract":"A multi-input neuron circuit with high-precision Sigmoid activation function (AF) is presented in this paper. The proposed circuit composed of input signal weighting circuit, current-voltage conversion circuit, and Sigmoid AF fitting circuit. Designed circuit can fit Sigmoid function based on the current-voltage relationship of differential pairs. The circuit is simulated in TSMC 0.18 um CMOS technology. The post-simulation shows that the error between the output of Sigmoid AF fitting circuit and the ideal Sigmoid function is 1.76%. The area of the layout is $375 mu m times 238 mu m$. The maximum error caused by noise in the output of the circuit is $80 pA/sqrt{Hz}$.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"319 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125774478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292185
Z. Shiling, Y. Hua
The internal overheating of the high-voltage switchgear is mainly caused by the internal transient current. The existing literature focuses on the decomposition of SF6 gas in the insulation medium after the internal overheating of the switch-gear, but the causes of the internal overheating fault are less introduced. In view of this, this paper attempts to analyze the typical analytical formula in the process of breaking the internal circuit breaker of high-voltage combined electrical apparatus from the theoretical angle. On this basis, the experimental platform is built to carry out the field simulation experiment of the circuit breaker fault opening and the closing process. In this process, the typical voltage and current waveform are obtained, which can be compared with simulation results of the theoretical formula mutual confirmation. Furthermore, the decomposition experiments of SF6 gas under the condition of transient current overheating are carried out on the simulation experimental platform, and basic decomposition products and their variation rules are determined under condition. The research results of this paper have good guiding value and practical engineering significance for understanding the transient over-voltage and current in high voltage switch-gear, and the local overheating phenomenon caused by it, and the overheating decomposition phenomenon of SF6 insulation gas.
{"title":"Theoretical Analysis and Experimental Verification of Switching Current Transient Process of High Voltage Switch-gear Circuit Breaker","authors":"Z. Shiling, Y. Hua","doi":"10.1109/ICICM50929.2020.9292185","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292185","url":null,"abstract":"The internal overheating of the high-voltage switchgear is mainly caused by the internal transient current. The existing literature focuses on the decomposition of SF6 gas in the insulation medium after the internal overheating of the switch-gear, but the causes of the internal overheating fault are less introduced. In view of this, this paper attempts to analyze the typical analytical formula in the process of breaking the internal circuit breaker of high-voltage combined electrical apparatus from the theoretical angle. On this basis, the experimental platform is built to carry out the field simulation experiment of the circuit breaker fault opening and the closing process. In this process, the typical voltage and current waveform are obtained, which can be compared with simulation results of the theoretical formula mutual confirmation. Furthermore, the decomposition experiments of SF6 gas under the condition of transient current overheating are carried out on the simulation experimental platform, and basic decomposition products and their variation rules are determined under condition. The research results of this paper have good guiding value and practical engineering significance for understanding the transient over-voltage and current in high voltage switch-gear, and the local overheating phenomenon caused by it, and the overheating decomposition phenomenon of SF6 insulation gas.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116812322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292241
Canran Yuan, Youming Zhang, Xusheng Tang, Zennan Wei, F. Huang, N. Jiang
In order to address the imbalance analysis for the passive device, this paper promotes an effective method by analyzing the current pathways in all the branches of the equivalent circuit of passive device. Since the current pathways are relative to the impedance characteristic of the corresponding ports, we can easily get an intuitive understanding of the causes of the impedance imbalance problem. The method's procedure in addition to an instance description is presented in detail.
{"title":"A Method of Impedance Imbalance Analysis for Passive Device","authors":"Canran Yuan, Youming Zhang, Xusheng Tang, Zennan Wei, F. Huang, N. Jiang","doi":"10.1109/ICICM50929.2020.9292241","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292241","url":null,"abstract":"In order to address the imbalance analysis for the passive device, this paper promotes an effective method by analyzing the current pathways in all the branches of the equivalent circuit of passive device. Since the current pathways are relative to the impedance characteristic of the corresponding ports, we can easily get an intuitive understanding of the causes of the impedance imbalance problem. The method's procedure in addition to an instance description is presented in detail.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114333025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292226
Yaqi Ma, Lijun Zhang, Jinchen Liu
With the development of semiconductor process, CMOS circuit size continues to shrink and the bulk silicon process has been difficult to meet the performance and power requirements of devices and circuits. At the same time, FINFET process has sprung up and replaced planar MOSFET due to their superior performance, power efficiency and scalability. The paper attempts to design a 6T SRAM memory cell in which it change PG transistors from NMOS to PMOS based on FINFET process. The PMOS SRAM memory cell is beneficial to area, speed and power consumption because the same size of PMOS drive capability is close to or even exceeds NMOS. From the results of simulation, we can see that although our new design can improve read and write speed and write margin (WM), the read static-noise margin (RSNM) deteriorates in worse corners. Hence, it need read assist circuits to improve RSNM.
{"title":"A New 6T SRAM Memory Cell Based on FINFET Process","authors":"Yaqi Ma, Lijun Zhang, Jinchen Liu","doi":"10.1109/ICICM50929.2020.9292226","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292226","url":null,"abstract":"With the development of semiconductor process, CMOS circuit size continues to shrink and the bulk silicon process has been difficult to meet the performance and power requirements of devices and circuits. At the same time, FINFET process has sprung up and replaced planar MOSFET due to their superior performance, power efficiency and scalability. The paper attempts to design a 6T SRAM memory cell in which it change PG transistors from NMOS to PMOS based on FINFET process. The PMOS SRAM memory cell is beneficial to area, speed and power consumption because the same size of PMOS drive capability is close to or even exceeds NMOS. From the results of simulation, we can see that although our new design can improve read and write speed and write margin (WM), the read static-noise margin (RSNM) deteriorates in worse corners. Hence, it need read assist circuits to improve RSNM.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130177734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292290
MingWen Meng, Zhiqun Cheng, Peng Xu, Guohua Liu
In this paper, an outphasing power amplifier(PA) with novel combiner is proposed. By replacing quarter wavelength impedance in classic structure with series microstrip lines with stop-band suppression, the proposed circuit achieved wide bandwidth while ensuring acceptable efficiency and linearity. Analytical and ADS simulation are presented in this work, an outphasing PA operating at center frequency 3.1GHz with 200MHz bandwidth is realized. The simulated results show excellent agreement in all cases considered.
{"title":"Improved Combiner Design for Broadband Outphasing Power Amplifier","authors":"MingWen Meng, Zhiqun Cheng, Peng Xu, Guohua Liu","doi":"10.1109/ICICM50929.2020.9292290","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292290","url":null,"abstract":"In this paper, an outphasing power amplifier(PA) with novel combiner is proposed. By replacing quarter wavelength impedance in classic structure with series microstrip lines with stop-band suppression, the proposed circuit achieved wide bandwidth while ensuring acceptable efficiency and linearity. Analytical and ADS simulation are presented in this work, an outphasing PA operating at center frequency 3.1GHz with 200MHz bandwidth is realized. The simulated results show excellent agreement in all cases considered.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"191 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131957765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292222
Yuqing Liang, Yan Wang, Haoshan Zhang, Anping He
This article proposes a novel asynchronous CIOS algorithm and its asynchronous architecture that can accelerate the encryption and decryption of RSA cryptosystem without increasing area. This algorithm merges two loops of the classical CIOS algorithm with the following advantages: reducing the number of operations by half, decreasing the complexity of hardware implementation by facilitation of the asynchronous pipelined parallel calculation, and saving the resources. Experimental results show that the average calculation time of our algorithm is only 9.8us, which is 36.5% faster than the classical one. In addition, our algorithm is also embedded in an asynchronous 1024-bits RSA cryptographic circuit, compared with the CIOS algorithm, the encryption and decryption speed are increased by 37.5%.
{"title":"aCIOSm4: An Asynchronous CIOS Algorithm","authors":"Yuqing Liang, Yan Wang, Haoshan Zhang, Anping He","doi":"10.1109/ICICM50929.2020.9292222","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292222","url":null,"abstract":"This article proposes a novel asynchronous CIOS algorithm and its asynchronous architecture that can accelerate the encryption and decryption of RSA cryptosystem without increasing area. This algorithm merges two loops of the classical CIOS algorithm with the following advantages: reducing the number of operations by half, decreasing the complexity of hardware implementation by facilitation of the asynchronous pipelined parallel calculation, and saving the resources. Experimental results show that the average calculation time of our algorithm is only 9.8us, which is 36.5% faster than the classical one. In addition, our algorithm is also embedded in an asynchronous 1024-bits RSA cryptographic circuit, compared with the CIOS algorithm, the encryption and decryption speed are increased by 37.5%.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133189190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292201
Rengang Li, Tuo Li, Kai Liu, Gang Liu, Peng Yao, R. A
With SoC becoming a prevailing trend, it is quite necessary to ensure the performance of SoC. Because the performance of SoC depends on the performance of processor, the processor core should have adequate clock frequency. Therefore, it is of great importance to investigate logic synthesis strategy for improving clock frequency of processor core, which belongs to a research gap. Some efforts have been made for bridging the gap in this paper. Specifically, the ARM core was chosen as the processor core, and logic synthesis strategy based on LVT devices was proposed to improve clock frequency of ARM core. When only RVT devices were included within constraints setting, the clock frequency of ARM core after logic synthesis was 486MHz. As LVT devices were introduced within constraints setting, some changes regarding the clock frequency happened. With the introduced proportion of 28%, 43% and 54%, the clock frequency respectively reached 576MHz, 697MHz and 636MHz. It was inferred the clock frequency after logic synthesis and proportion of LVT devices presented the approximate parabolic relationship. The clock frequency first increased and then decreased with the increase of LVT devices proportion. The mechanism for presenting such relationship was given. Therefore, logic synthesis strategy based on LVT devices contributed to increasing the clock frequency of ARM core. It should be noted that the proportion of LVT devices should be set within a reasonable scope for the strategy. The reasonable scope ensured the clock frequency to locate at the upper part of parabola. Within the reasonable scope, the factor of power consumption was further taken into consideration. When the mapped circuits needed to avoid potential negative effects of high power consumption at a certain extent, the proportion of LVT devices should be near the endpoint of reasonable scope. However, when the mapped circuits must pursue high performance, the proportion of LVT devices should be near the peak point.
{"title":"A Study of Logic Synthesis Strategy Based on LVT Devices for Increasing Clock Frequency of SoC Processor Core","authors":"Rengang Li, Tuo Li, Kai Liu, Gang Liu, Peng Yao, R. A","doi":"10.1109/ICICM50929.2020.9292201","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292201","url":null,"abstract":"With SoC becoming a prevailing trend, it is quite necessary to ensure the performance of SoC. Because the performance of SoC depends on the performance of processor, the processor core should have adequate clock frequency. Therefore, it is of great importance to investigate logic synthesis strategy for improving clock frequency of processor core, which belongs to a research gap. Some efforts have been made for bridging the gap in this paper. Specifically, the ARM core was chosen as the processor core, and logic synthesis strategy based on LVT devices was proposed to improve clock frequency of ARM core. When only RVT devices were included within constraints setting, the clock frequency of ARM core after logic synthesis was 486MHz. As LVT devices were introduced within constraints setting, some changes regarding the clock frequency happened. With the introduced proportion of 28%, 43% and 54%, the clock frequency respectively reached 576MHz, 697MHz and 636MHz. It was inferred the clock frequency after logic synthesis and proportion of LVT devices presented the approximate parabolic relationship. The clock frequency first increased and then decreased with the increase of LVT devices proportion. The mechanism for presenting such relationship was given. Therefore, logic synthesis strategy based on LVT devices contributed to increasing the clock frequency of ARM core. It should be noted that the proportion of LVT devices should be set within a reasonable scope for the strategy. The reasonable scope ensured the clock frequency to locate at the upper part of parabola. Within the reasonable scope, the factor of power consumption was further taken into consideration. When the mapped circuits needed to avoid potential negative effects of high power consumption at a certain extent, the proportion of LVT devices should be near the endpoint of reasonable scope. However, when the mapped circuits must pursue high performance, the proportion of LVT devices should be near the peak point.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124920026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292302
Bowen Wu, Zongming Duan, Yan Wang, Wei Lv
This paper presents A 1 to 4 GHz tri-directional RF amplifier based on 0.18um technology for digital array radar applications. A wideband matching from 1 to 4 GHz at RF port is achieved while the circuit is working in both TX and RX mode. The circuits consist of a variable gain low noise amplifier, a drive amplifier and a single pole double throw switch. The circuit shows gain from 7.6 to 14.2 dB, and the noise figure is less than 5.3 dB with −3dBm@2.4GHz input P-1dB compression point in RX, while gain of 9.9dB and output P-1dB compression point is 11.4dBm@2.4GHz in TX. The chip size is 2.25mm*0.97mm (with pads).
{"title":"A 1∼4GHz Tri-Directional RF Amplifier Based on CMOS Technology for Digital Array Radars","authors":"Bowen Wu, Zongming Duan, Yan Wang, Wei Lv","doi":"10.1109/ICICM50929.2020.9292302","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292302","url":null,"abstract":"This paper presents A 1 to 4 GHz tri-directional RF amplifier based on 0.18um technology for digital array radar applications. A wideband matching from 1 to 4 GHz at RF port is achieved while the circuit is working in both TX and RX mode. The circuits consist of a variable gain low noise amplifier, a drive amplifier and a single pole double throw switch. The circuit shows gain from 7.6 to 14.2 dB, and the noise figure is less than 5.3 dB with −3dBm@2.4GHz input P-1dB compression point in RX, while gain of 9.9dB and output P-1dB compression point is 11.4dBm@2.4GHz in TX. The chip size is 2.25mm*0.97mm (with pads).","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122047987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292217
Haoshan Zhang, Yuqing Liang, Taiyi Zhang, Anping He
With the continuous advantage of integrated circuit manufacturing technology, the design and implementation of chips are increasingly constrained by the global clock. Asynchronous circuits have become remarkable again because of their advantages of low power consumption, high electromagnetic robustness, and higher average rate compared to synchronous circuits. But the lack of commercial EDA support makes the design of asynchronous circuits difficult. This paper presents a clock replacement method that converts a synchronous circuit into the corresponding asynchronous type which follows the BBD protocol, and discusses the key delay matching in detail. Finally, based on this method, we implemented an asynchronous 8051 MCU, and the common commands are tested by simulation, the results show that the MCU works normally, proving the simplicity and feasibility of the clock replacement method.
{"title":"An Applicable Method of Clock Replacing with BBD Asynchronous Circuit","authors":"Haoshan Zhang, Yuqing Liang, Taiyi Zhang, Anping He","doi":"10.1109/ICICM50929.2020.9292217","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292217","url":null,"abstract":"With the continuous advantage of integrated circuit manufacturing technology, the design and implementation of chips are increasingly constrained by the global clock. Asynchronous circuits have become remarkable again because of their advantages of low power consumption, high electromagnetic robustness, and higher average rate compared to synchronous circuits. But the lack of commercial EDA support makes the design of asynchronous circuits difficult. This paper presents a clock replacement method that converts a synchronous circuit into the corresponding asynchronous type which follows the BBD protocol, and discusses the key delay matching in detail. Finally, based on this method, we implemented an asynchronous 8051 MCU, and the common commands are tested by simulation, the results show that the MCU works normally, proving the simplicity and feasibility of the clock replacement method.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122783490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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