Artificial intelligence and machine learning have been widely used to replace human work. Analog integrated circuit design needs to adjust a large number of circuit parameters to satisfy the balance between various performance metrics, which now mostly rely on the experience of designers and sometimes of the intuitions. Machine learning has demonstrated the potential to aid the design of analog integrated circuits in the literature, whilst most of them adopted particle swarm intelligence and Bayesian optimization. However, the model training time and simulation run time are substantial when any circuit structure modification occurs. In this paper, Recurrent Neural Network (RNN) was used to automatically optimize the parameters sizing by giving requested performance. Training data sets for the RNN of component parameters and circuit performance were simulated using Cadence Spectre. After training for only 15 minutes, RNN learns to predict parameters by inputting gain, bandwidth, power and frequency, which can make critical circuit design decision significantly faster. The reliability and applicability of the algorithm was verified through the parameter prediction of integrated operational amplifier and VCO.
{"title":"LSTM-RNN Based Analog IC Automated Sizing Model for Operational Amplifier and VCO","authors":"Zihan Yang, Wensi Wang, Zhijie Chen, Qianhui Fan, Xuanchong Chen","doi":"10.1109/ICICM50929.2020.9292252","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292252","url":null,"abstract":"Artificial intelligence and machine learning have been widely used to replace human work. Analog integrated circuit design needs to adjust a large number of circuit parameters to satisfy the balance between various performance metrics, which now mostly rely on the experience of designers and sometimes of the intuitions. Machine learning has demonstrated the potential to aid the design of analog integrated circuits in the literature, whilst most of them adopted particle swarm intelligence and Bayesian optimization. However, the model training time and simulation run time are substantial when any circuit structure modification occurs. In this paper, Recurrent Neural Network (RNN) was used to automatically optimize the parameters sizing by giving requested performance. Training data sets for the RNN of component parameters and circuit performance were simulated using Cadence Spectre. After training for only 15 minutes, RNN learns to predict parameters by inputting gain, bandwidth, power and frequency, which can make critical circuit design decision significantly faster. The reliability and applicability of the algorithm was verified through the parameter prediction of integrated operational amplifier and VCO.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126524623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292166
Weiwei Zhou, Zhiqun Cheng, Y. Guo
In this paper, a novel design method for dual-polarized patch antennas is presented for base station applications. The proposed antenna is a low-cost design with a simple configuration, which avoids using the conventional high-cost multilayer PCB technology. The antenna is composed of four intersected loop resonators, which are connected to each other at the center. By using the electric and magnetic coupling from the intersected loop resonators, two orthogonal radiating modes are excited from the top radiating patch. With the differential feed on the intersected loop resonators, high port isolation and low cross-polarization level are obtained. Compared to the traditionally designed capacitively coupled antenna, two times wider impedance bandwidth is obtained for the proposed antenna with high isolation (>45.5 dB) and low cross polarization level (< −28 dB). The employed antenna are bend upward to maintain a small aperture size, so that the realized element still fits in traditional base station antenna (BSA) array. The antenna is matched across the band from 1.7 to 3.7 GHz, which can cover both the LTE band from 1.7 to 2.7 GHz and the 5G (sub-6 GHz) band from 3.3 to 3.6 GHz simultaneously.
{"title":"A Dual-Polarized Patch Antenna With Electric and Magnetic Coupling Feed for 5G Base Stations","authors":"Weiwei Zhou, Zhiqun Cheng, Y. Guo","doi":"10.1109/ICICM50929.2020.9292166","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292166","url":null,"abstract":"In this paper, a novel design method for dual-polarized patch antennas is presented for base station applications. The proposed antenna is a low-cost design with a simple configuration, which avoids using the conventional high-cost multilayer PCB technology. The antenna is composed of four intersected loop resonators, which are connected to each other at the center. By using the electric and magnetic coupling from the intersected loop resonators, two orthogonal radiating modes are excited from the top radiating patch. With the differential feed on the intersected loop resonators, high port isolation and low cross-polarization level are obtained. Compared to the traditionally designed capacitively coupled antenna, two times wider impedance bandwidth is obtained for the proposed antenna with high isolation (>45.5 dB) and low cross polarization level (< −28 dB). The employed antenna are bend upward to maintain a small aperture size, so that the realized element still fits in traditional base station antenna (BSA) array. The antenna is matched across the band from 1.7 to 3.7 GHz, which can cover both the LTE band from 1.7 to 2.7 GHz and the 5G (sub-6 GHz) band from 3.3 to 3.6 GHz simultaneously.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124872184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292131
Qihao Yin, Chunfeng Bai
This paper presents a CMOS buffer for near-rail voltage. Compared with conventional OTA-based structure, an additional super source follower is added in the loop, which hence maintains fairly high loop-gain even when the input voltage is very close to the power supply voltage or ground. The voltage-drop between the buffered voltage and the rail can be as low as 10 mV. Besides, the output impedance can be lower as the proposed buffer entails larger load capacitor.
{"title":"A CMOS Reference Voltage Buffer Designed for Near-rail Voltage","authors":"Qihao Yin, Chunfeng Bai","doi":"10.1109/ICICM50929.2020.9292131","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292131","url":null,"abstract":"This paper presents a CMOS buffer for near-rail voltage. Compared with conventional OTA-based structure, an additional super source follower is added in the loop, which hence maintains fairly high loop-gain even when the input voltage is very close to the power supply voltage or ground. The voltage-drop between the buffered voltage and the rail can be as low as 10 mV. Besides, the output impedance can be lower as the proposed buffer entails larger load capacitor.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121510808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292297
Ming Ni, Yan Han, Hakbong Kim
This manuscript presents a high-pass filter for neural signals processing. An operational transconductance amplifier-capacitor (OTA-C) filter architecture is chosen to decrease the power consumption and the active area. The on-chip body bias technique is adopted to reduce the offset of the bandwidth due to the process, voltage and temperature (PVT) variation. The proposed filter is designed in 40 nm CMOS technology. Simulation results indicate that it has a signal bandwidth located above 300 Hz, dynamic range of 68 dB, and a power consumption of 14 nW at 1.1 V supply.
{"title":"A High-pass Filter with On-chip Body Bias Technique for Neural Signals Processing","authors":"Ming Ni, Yan Han, Hakbong Kim","doi":"10.1109/ICICM50929.2020.9292297","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292297","url":null,"abstract":"This manuscript presents a high-pass filter for neural signals processing. An operational transconductance amplifier-capacitor (OTA-C) filter architecture is chosen to decrease the power consumption and the active area. The on-chip body bias technique is adopted to reduce the offset of the bandwidth due to the process, voltage and temperature (PVT) variation. The proposed filter is designed in 40 nm CMOS technology. Simulation results indicate that it has a signal bandwidth located above 300 Hz, dynamic range of 68 dB, and a power consumption of 14 nW at 1.1 V supply.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"11 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131477998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292206
J. Ren, Xu Ding, Xiao-ning Xin, Hua-Han Chen
To solve the problems of NAND Flash with the reduction of size and the increase of information stored in the storage unit, the erase life and reliability of Flash are reduced, this paper uses Non-binary Low-density Parity-check (NB-LDPC) hard decision technology solves these problems. By using methods such as excluding self-input messages and using initial channel messages in calculation, Compared with the traditional binary LDPC decoding algorithm, this algorithm can successfully perform fast decoding. When the bit error rate is less than 10−4, the coding gain was increased by at least 0.5 dB. Simulation results show that the algorithm can avoid low error leveling and significantly reduce the bit error rate in storage applications with high code length and high transmission rate, and improve the decoding success rate. It is conducive to the fast decoding of the memory. The research results can provide the necessary conditions for the accurate decoding and automated operation of the NAND Flash later.
{"title":"An NB-LDPC decoder Algorithm combined using channel information for Storage Application","authors":"J. Ren, Xu Ding, Xiao-ning Xin, Hua-Han Chen","doi":"10.1109/ICICM50929.2020.9292206","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292206","url":null,"abstract":"To solve the problems of NAND Flash with the reduction of size and the increase of information stored in the storage unit, the erase life and reliability of Flash are reduced, this paper uses Non-binary Low-density Parity-check (NB-LDPC) hard decision technology solves these problems. By using methods such as excluding self-input messages and using initial channel messages in calculation, Compared with the traditional binary LDPC decoding algorithm, this algorithm can successfully perform fast decoding. When the bit error rate is less than 10−4, the coding gain was increased by at least 0.5 dB. Simulation results show that the algorithm can avoid low error leveling and significantly reduce the bit error rate in storage applications with high code length and high transmission rate, and improve the decoding success rate. It is conducive to the fast decoding of the memory. The research results can provide the necessary conditions for the accurate decoding and automated operation of the NAND Flash later.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128881249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292165
Xiaoxia Song, Yumei Zhang, F. Yu, Yongbo Zhai
In this paper, the ubiquitous muti-beam beamwidth of the Rotman lens is tentative studied using widening technique. Phase weighted beam synthesis is adopted, and matched cables are connected between ports of the lens array and antennas. The measured widening pattern and un-widening pattern are compared, which demonstrates that the beam of the Rotman lens can be widened through phase weighting. Then, the measured database is analyzed. Results show that, the phase deviation of phase value inputted into the ports of the lens array must be considered when widening the beam.
{"title":"Research on Beam Widening of Rotman Lens","authors":"Xiaoxia Song, Yumei Zhang, F. Yu, Yongbo Zhai","doi":"10.1109/ICICM50929.2020.9292165","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292165","url":null,"abstract":"In this paper, the ubiquitous muti-beam beamwidth of the Rotman lens is tentative studied using widening technique. Phase weighted beam synthesis is adopted, and matched cables are connected between ports of the lens array and antennas. The measured widening pattern and un-widening pattern are compared, which demonstrates that the beam of the Rotman lens can be widened through phase weighting. Then, the measured database is analyzed. Results show that, the phase deviation of phase value inputted into the ports of the lens array must be considered when widening the beam.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114756263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292160
J. Meng, Yue Yu, Rongrong Zhan, Xiaojiang Zheng, Zhicheng Li
From the perspective of improving the speed and reliability of power system relay protection, this paper proposes a relay protection hardware design based on dual high-performance SoC. In the design, the parallel redundant software and hardware system architecture is used to realize separate and independent operations of protection function and startup function, with heterogeneous asymmetric multiprocessing mode and off-chip DDR controller that supports ECC error correction adopted to ensure the strict real-time performance and data reliability of protection sampling and calculation functions. Furthermore, by the method of integrating AD sampling preprocessing module and FFT acceleration processor in the on-chip high-performance FPGA, the speed of relay protection data processing and actions are improved.
{"title":"Design of Special Chips for Relay Protection Based on Dual High-Performance SoC","authors":"J. Meng, Yue Yu, Rongrong Zhan, Xiaojiang Zheng, Zhicheng Li","doi":"10.1109/ICICM50929.2020.9292160","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292160","url":null,"abstract":"From the perspective of improving the speed and reliability of power system relay protection, this paper proposes a relay protection hardware design based on dual high-performance SoC. In the design, the parallel redundant software and hardware system architecture is used to realize separate and independent operations of protection function and startup function, with heterogeneous asymmetric multiprocessing mode and off-chip DDR controller that supports ECC error correction adopted to ensure the strict real-time performance and data reliability of protection sampling and calculation functions. Furthermore, by the method of integrating AD sampling preprocessing module and FFT acceleration processor in the on-chip high-performance FPGA, the speed of relay protection data processing and actions are improved.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131955360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292279
Jiaqi Fan, Shengming Huang, Q. Duan
This paper presents a logic control scheme and its implementing circuit that can carry out precise and convenient control of the stepper motor current. The logic control scheme can complete the control of the stepper motor's speed, steering and step length by using only four control inputs. Based on the mode selection, a variety of subdivision driving modes such as full step, half step, 1/4 step, 1/8 step, 1/16 step, 1/32 step can be realized, which greatly reduces the number and simplifies complexity of external control signals. It is verified by simulations that the control scheme is able to provide accurate current control signals for driving stepper motors.
{"title":"Novel Index Mode Control Scheme and Circuit for Driving Stepper Motor","authors":"Jiaqi Fan, Shengming Huang, Q. Duan","doi":"10.1109/ICICM50929.2020.9292279","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292279","url":null,"abstract":"This paper presents a logic control scheme and its implementing circuit that can carry out precise and convenient control of the stepper motor current. The logic control scheme can complete the control of the stepper motor's speed, steering and step length by using only four control inputs. Based on the mode selection, a variety of subdivision driving modes such as full step, half step, 1/4 step, 1/8 step, 1/16 step, 1/32 step can be realized, which greatly reduces the number and simplifies complexity of external control signals. It is verified by simulations that the control scheme is able to provide accurate current control signals for driving stepper motors.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133584242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292254
Yan Zhang, Shuqin Geng, Xiaohong Peng, Zifeng Wang, Haonan Tang, Shuaiqi Yan
In this paper, we use Python script to read the function detailed description documents of CAN-FD IP, extract the required information according to the main keywords and other information, and automatically generate the qualified System Verilog constrained randomized register configuration stimulator. The simulation results show that the stimulator can meet the design requirements for the configuration of excitation, and can effectively improve the design efficiency of the verification platform.
{"title":"Research on Automatic Generation of Stimulator Based on CAN-FD Verification Platform","authors":"Yan Zhang, Shuqin Geng, Xiaohong Peng, Zifeng Wang, Haonan Tang, Shuaiqi Yan","doi":"10.1109/ICICM50929.2020.9292254","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292254","url":null,"abstract":"In this paper, we use Python script to read the function detailed description documents of CAN-FD IP, extract the required information according to the main keywords and other information, and automatically generate the qualified System Verilog constrained randomized register configuration stimulator. The simulation results show that the stimulator can meet the design requirements for the configuration of excitation, and can effectively improve the design efficiency of the verification platform.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125808738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292141
Haonan Tang, Shuqin Geng, Xiaohong Peng, Shuaiqi Yan, Yan Zhang, Zifeng Wang
Based on the quick sorting algorithm, this paper uses verilog language to implement the RTL design of the ID sorting module applied to the CAN bus controller, and performs functional simulation on the module. Simulation results show that the ID sorting module designed in this paper can quickly sort up to 64 different ID numbers and output correct sequence to meet the design requirements. Using a parametric design strategy, the ID sorting module designed in this paper can configure parameters to achieve the function of sorting a larger number of random sequences to meet different needs, and has high scalability and practicality.
{"title":"A Design of ID Sorting Module Based on Quick Sorting Algorithm","authors":"Haonan Tang, Shuqin Geng, Xiaohong Peng, Shuaiqi Yan, Yan Zhang, Zifeng Wang","doi":"10.1109/ICICM50929.2020.9292141","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292141","url":null,"abstract":"Based on the quick sorting algorithm, this paper uses verilog language to implement the RTL design of the ID sorting module applied to the CAN bus controller, and performs functional simulation on the module. Simulation results show that the ID sorting module designed in this paper can quickly sort up to 64 different ID numbers and output correct sequence to meet the design requirements. Using a parametric design strategy, the ID sorting module designed in this paper can configure parameters to achieve the function of sorting a larger number of random sequences to meet different needs, and has high scalability and practicality.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"299 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122156919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：