Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292152
YiBai Zhang, Fei Yang
This paper presents an active single pole double throw switch (SPDT), with Gallium Nitride on Silicon Carbide (GaN/SiC) millimeter wave process, working in the D-Band (110-170 GHz) frequency range. A single branch of the switch consists of the combination of a shunt transistor and a common-source transistor, achieving low insertion loss in the transmission state as well as good isolation in the isolation state. The simulation results of the monolithic microwave integrated circuits (MMICs) SPDT switch demonstrate a minimum insertion loss of 0.64 dB with 3 dB bandwidths of 35 GHz. Within the 3 dB bandwidth the isolation of the switch is higher than 19.7 dB.
{"title":"A D-Band Active Single Pole Double Throw Switch in 60-nm GaN/SiC Technology","authors":"YiBai Zhang, Fei Yang","doi":"10.1109/ICICM50929.2020.9292152","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292152","url":null,"abstract":"This paper presents an active single pole double throw switch (SPDT), with Gallium Nitride on Silicon Carbide (GaN/SiC) millimeter wave process, working in the D-Band (110-170 GHz) frequency range. A single branch of the switch consists of the combination of a shunt transistor and a common-source transistor, achieving low insertion loss in the transmission state as well as good isolation in the isolation state. The simulation results of the monolithic microwave integrated circuits (MMICs) SPDT switch demonstrate a minimum insertion loss of 0.64 dB with 3 dB bandwidths of 35 GHz. Within the 3 dB bandwidth the isolation of the switch is higher than 19.7 dB.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126275469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292224
Xuecheng Xu, Xiangjun Lu, Xie An
In view of the electromagnetic interference (EMI) of Tesla coil on intelligent electronic lock, the structure and internal circuit of Tesla jammer were analyzed firstly. Then, a near-field probe was made by using coaxial cable to simulate the electromagnetic field coupling of the closed loop and the wire as receiving antenna in the actual circuit. The results show that the electromagnetic field distribution of Tesla jammer is related to the spatial position, interference frequency and interference direction. Then, the electromagnetic immunity test platform of integrated circuit (IC) was built to test the interference of master IC for intelligent electronic lock under different space angles, interference frequencies and interference amplitudes. Regardless of the working state of the system, the coupling efficiency of IC in EMI environment is consistent in frequency selection, and the influence of angle change on the electromagnetic coupling voltage of IC pins presents a specific change rule. Finally, the electromagnetic coupling effect of IC pins under any interference intensity was extrapolated based on the variation law of pin coupling voltage and interference intensity.
{"title":"Research on Electromagnetic Interference of Integrated Circuit for Intelligent Electronic Lock","authors":"Xuecheng Xu, Xiangjun Lu, Xie An","doi":"10.1109/ICICM50929.2020.9292224","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292224","url":null,"abstract":"In view of the electromagnetic interference (EMI) of Tesla coil on intelligent electronic lock, the structure and internal circuit of Tesla jammer were analyzed firstly. Then, a near-field probe was made by using coaxial cable to simulate the electromagnetic field coupling of the closed loop and the wire as receiving antenna in the actual circuit. The results show that the electromagnetic field distribution of Tesla jammer is related to the spatial position, interference frequency and interference direction. Then, the electromagnetic immunity test platform of integrated circuit (IC) was built to test the interference of master IC for intelligent electronic lock under different space angles, interference frequencies and interference amplitudes. Regardless of the working state of the system, the coupling efficiency of IC in EMI environment is consistent in frequency selection, and the influence of angle change on the electromagnetic coupling voltage of IC pins presents a specific change rule. Finally, the electromagnetic coupling effect of IC pins under any interference intensity was extrapolated based on the variation law of pin coupling voltage and interference intensity.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123003784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292273
Zhen Chen, Youming Zhang, Xusheng Tang, Junjie Li, F. Huang, N. Jiang
A low power consumption, high-speed and wide division ratio range programmable frequency divider designed in 0.18 mumathrm{m}$ SiGe process is presented. The circuit consists of 4/5 dual-modulus prescaler, 5-bit subtraction counter and control logic. The combination of D flip-flops and logic gates effectively reduces the transmission delay and improves the operating frequency of the dual-modulus prescaler. The pulse counter and the swallow counter are merged into one, which reduces the chip area. A novel control logic is adopted to reduce the minimum frequency division ratio by allowing the S value equal to 0. The whole frequency divider is composed of TSPC (true-single-phase-clocked) D flip-flops and complementary CMOS logic gates without static power consumption. The simulation results indicate that the programmable frequency divider has a 4.7 GHz maximum operating frequency, and achieves a continuous division ratio range from 16 to 159, with a power consumption of 5.9 mA at 1.8 V supply voltage at the maximum operating frequency.
提出了一种采用0.18 mu mathm {m}$ SiGe工艺设计的低功耗、高速、宽分频比范围可编程分频器。该电路由4/5双模预分频器、5位减法计数器和控制逻辑组成。D触发器与逻辑门的组合有效地降低了传输延迟，提高了双模预分频器的工作频率。将脉冲计数器和燕子计数器合二为一，减小了芯片面积。采用一种新颖的控制逻辑，允许S值等于0，从而降低最小分频比。整个分频器由TSPC(真单相时钟)D触发器和互补的CMOS逻辑门组成，没有静态功耗。仿真结果表明，该可编程分频器最大工作频率为4.7 GHz，连续分频比范围为16 ~ 159，最大工作频率为1.8 V电源电压时的功耗为5.9 mA。
{"title":"Design of Low Power Consumption, High-Speed and Wide Division Ratio Range Programmable Frequency Divider","authors":"Zhen Chen, Youming Zhang, Xusheng Tang, Junjie Li, F. Huang, N. Jiang","doi":"10.1109/ICICM50929.2020.9292273","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292273","url":null,"abstract":"A low power consumption, high-speed and wide division ratio range programmable frequency divider designed in 0.18 mumathrm{m}$ SiGe process is presented. The circuit consists of 4/5 dual-modulus prescaler, 5-bit subtraction counter and control logic. The combination of D flip-flops and logic gates effectively reduces the transmission delay and improves the operating frequency of the dual-modulus prescaler. The pulse counter and the swallow counter are merged into one, which reduces the chip area. A novel control logic is adopted to reduce the minimum frequency division ratio by allowing the S value equal to 0. The whole frequency divider is composed of TSPC (true-single-phase-clocked) D flip-flops and complementary CMOS logic gates without static power consumption. The simulation results indicate that the programmable frequency divider has a 4.7 GHz maximum operating frequency, and achieves a continuous division ratio range from 16 to 159, with a power consumption of 5.9 mA at 1.8 V supply voltage at the maximum operating frequency.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117306685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292266
Yiwei Wu, Ruirong Wu
Phase linear characteristic is an important parameter of RF transceiver module in phased array radar system. This paper analyzes the causes of phase nonlinear based on the mechanism of which, and puts forward four methods of optimizing the phase linear. Finally, an X-band RF transceiver module is designed and manufactured to verify the effectiveness of the methods. The test results show that by using the methods proposed, the phase distortion of the RF transceiver module can be improved obviously.
{"title":"Optimization design of phase characteristics of RF transceiver module in radar system","authors":"Yiwei Wu, Ruirong Wu","doi":"10.1109/ICICM50929.2020.9292266","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292266","url":null,"abstract":"Phase linear characteristic is an important parameter of RF transceiver module in phased array radar system. This paper analyzes the causes of phase nonlinear based on the mechanism of which, and puts forward four methods of optimizing the phase linear. Finally, an X-band RF transceiver module is designed and manufactured to verify the effectiveness of the methods. The test results show that by using the methods proposed, the phase distortion of the RF transceiver module can be improved obviously.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114913200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292262
Liu Yang, Xiangliang Jin, Yixing Chen
A design of color holographic display system realized by using single chip liquid crystal on silicon (LCoS) is proposed. In this system, FPGA converts HDMI signal of the color hologram with frame rate of 60Hz to VGA signal of RGB holograms with frame rate of 180Hz and then output the signal to LCoS, at the same time, light the corresponding laser, which realizes a real-time time-division multiplexing color hologram display. In addition, in order to improve the linear phase characteristics of LCoS to get the better quality of hologram reconstruction, the analog calibration and flatness calibration are carried out. Finally, the feasibility of the system is verified by building the optical path and making color hologram.
{"title":"A Real-Time Color Holographic Display System by Time Division Multiplexing Based on LCoS","authors":"Liu Yang, Xiangliang Jin, Yixing Chen","doi":"10.1109/ICICM50929.2020.9292262","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292262","url":null,"abstract":"A design of color holographic display system realized by using single chip liquid crystal on silicon (LCoS) is proposed. In this system, FPGA converts HDMI signal of the color hologram with frame rate of 60Hz to VGA signal of RGB holograms with frame rate of 180Hz and then output the signal to LCoS, at the same time, light the corresponding laser, which realizes a real-time time-division multiplexing color hologram display. In addition, in order to improve the linear phase characteristics of LCoS to get the better quality of hologram reconstruction, the analog calibration and flatness calibration are carried out. Finally, the feasibility of the system is verified by building the optical path and making color hologram.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114916641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292147
Yang Yang, Lu Tang
An automatic frequency calibration (AFC) based on high-speed counter is proposed for all-digital phase-locked loop(ADPLL). The AFC module is designed for coarse and medium calibration. The calibration mode is updated after the frequency difference is 0. For the frequency difference is accurate, the AFC adopts double-edge counting and satisfies the relation of real frequency and target frequency. The AFC and counter circuit implemented in a 40nm CMOS process occupies $2358.8mumathrm{m}2$. Under the condition that the reference frequency is 100MHz and the DCO output frequency is 1GHz, the calibration needs about $5mumathrm{s}$ in the best case, and $21mumathrm{s}$ in the worst case.
{"title":"Automatic Frequency Calibration Module based on High-speed Counter","authors":"Yang Yang, Lu Tang","doi":"10.1109/ICICM50929.2020.9292147","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292147","url":null,"abstract":"An automatic frequency calibration (AFC) based on high-speed counter is proposed for all-digital phase-locked loop(ADPLL). The AFC module is designed for coarse and medium calibration. The calibration mode is updated after the frequency difference is 0. For the frequency difference is accurate, the AFC adopts double-edge counting and satisfies the relation of real frequency and target frequency. The AFC and counter circuit implemented in a 40nm CMOS process occupies $2358.8mumathrm{m}2$. Under the condition that the reference frequency is 100MHz and the DCO output frequency is 1GHz, the calibration needs about $5mumathrm{s}$ in the best case, and $21mumathrm{s}$ in the worst case.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128147291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292135
Liang Guo, Tao Zeng, Wang Liao, Jiang Hou, Pengfei Liao
This paper presents a programmable current reference for analog and mixed signal system. The proposed circuit was designed in a standard 65nm CMOS process. Current reference is an IP hard core with temperature independent (TIND) current and proportional to absolute temperature (PTAT) current, the IP core has built-in op amp and a bias for temperature compensated, the simulation results show temperature coefficient (TC) of ITIND, IPTAT10, IPTAT20 and IPTAT40 as low as 20 ppm/°C, 1111.11 ppm/°C, 2222.22 ppm/°C, 4444.44 ppm/°C over a temperature range of 180°C (55°C to 125°C) respectively. It consumes 1.44mW in global mode, while operating on 1.2V power supply, its area is only $145mumathrm{m}times 235mumathrm{m}$.
{"title":"A Programmable Wide-Range Temperature Compensated Current Reference","authors":"Liang Guo, Tao Zeng, Wang Liao, Jiang Hou, Pengfei Liao","doi":"10.1109/ICICM50929.2020.9292135","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292135","url":null,"abstract":"This paper presents a programmable current reference for analog and mixed signal system. The proposed circuit was designed in a standard 65nm CMOS process. Current reference is an IP hard core with temperature independent (TIND) current and proportional to absolute temperature (PTAT) current, the IP core has built-in op amp and a bias for temperature compensated, the simulation results show temperature coefficient (TC) of ITIND, IPTAT10, IPTAT20 and IPTAT40 as low as 20 ppm/°C, 1111.11 ppm/°C, 2222.22 ppm/°C, 4444.44 ppm/°C over a temperature range of 180°C (55°C to 125°C) respectively. It consumes 1.44mW in global mode, while operating on 1.2V power supply, its area is only $145mumathrm{m}times 235mumathrm{m}$.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133092831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292301
Junye Ma, Xian Tang, W. Ng, Mingming Zhang
A high-efficiency active rectifier for wireless power transfer is presented in this work. Adaptive off-delay compensation is adopted that is based on reverse current detection and bias current control. Simulation results in a commercial 0.18mumathrm{m}$ CMOS technology show that the proposed scheme effectively eliminates the influence of the off-delay of the comparator and the peak efficiency of the rectifier is 92.5% when the rectifier works under 13.56MHz.
{"title":"A High-Efficiency Active Rectifier with Adaptive Off-Delay Compensation for Wireless Power Transfer Systems","authors":"Junye Ma, Xian Tang, W. Ng, Mingming Zhang","doi":"10.1109/ICICM50929.2020.9292301","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292301","url":null,"abstract":"A high-efficiency active rectifier for wireless power transfer is presented in this work. Adaptive off-delay compensation is adopted that is based on reverse current detection and bias current control. Simulation results in a commercial 0.18mumathrm{m}$ CMOS technology show that the proposed scheme effectively eliminates the influence of the off-delay of the comparator and the peak efficiency of the rectifier is 92.5% when the rectifier works under 13.56MHz.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"16 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132148532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292245
Dantong Wu, Chunqi Qian, Xiaoyu Zhang, Z. Wang, Xu Liu
This paper proposes a capacitance sensing circuit which converts the change of input capacitance into digital code as output signal. The whole CDC circuit is designed using SMIC 0.18 mumathrm{m}$ CMOS process technology in cadence. It contains an AFE circuit and an advanced single-slop ADC circuit. The CDC circuit which has a high dynamic range can measure the capacitor ranging from 1fF to 1pF, even with the large input parasitic capacitance. The AFE module is improved base on traditional C-V by adding subtracting and level shifting circuit to eliminate the influence of parasitic capacitor in the circuit. Simulation results show that the sensitivity of the AFE circuit is 0.95 fF/mV and the sensitivity of the CDC circuit is 1 fF/digital. Conversion time for each measurement is $65 mumathrm{s}$ and the current consumption of the circuit is 1.1 mA.
本文提出了一种电容传感电路，将输入电容的变化转换成数字编码作为输出信号。整个CDC电路采用中芯国际0.18 mu mathm {m}$ CMOS工艺技术进行设计。它包含一个AFE电路和一个先进的单斜率ADC电路。CDC电路具有高动态范围，即使在较大的输入寄生电容下，也可以测量1fF到1pF的电容。AFE模块在传统C-V的基础上进行了改进，增加了减法和移电平电路，消除了电路中寄生电容的影响。仿真结果表明，AFE电路的灵敏度为0.95 fF/mV, CDC电路的灵敏度为1 fF/数字。每次测量的转换时间为$65 mu maththrm {s}$，电路的电流消耗为1.1 mA。
{"title":"Design of a Capacitance Measurement Circuit with Input Parasitic Capacitance Elimination","authors":"Dantong Wu, Chunqi Qian, Xiaoyu Zhang, Z. Wang, Xu Liu","doi":"10.1109/ICICM50929.2020.9292245","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292245","url":null,"abstract":"This paper proposes a capacitance sensing circuit which converts the change of input capacitance into digital code as output signal. The whole CDC circuit is designed using SMIC 0.18 mumathrm{m}$ CMOS process technology in cadence. It contains an AFE circuit and an advanced single-slop ADC circuit. The CDC circuit which has a high dynamic range can measure the capacitor ranging from 1fF to 1pF, even with the large input parasitic capacitance. The AFE module is improved base on traditional C-V by adding subtracting and level shifting circuit to eliminate the influence of parasitic capacitor in the circuit. Simulation results show that the sensitivity of the AFE circuit is 0.95 fF/mV and the sensitivity of the CDC circuit is 1 fF/digital. Conversion time for each measurement is $65 mumathrm{s}$ and the current consumption of the circuit is 1.1 mA.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"317 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133865422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292240
M. Shuaib
To design data converters main challenges are high resolution, high speed, and low power. Operational amplifiers (op-amps) are core building blocks in such mixed signal systems to overcome these issues. As high resolution is linked to op-amp's high dc gain and high speed demands single pole response and large unity gain frequency. This paper deals with design of two stage opamp with class AB as output stage and it has been simulated in 0.18um TSMC CMOS technology. This design achieves high low frequency gain(92dB), good gain bandwidth product(19.07MHz) and low power. To stabilize this op-amp techniques used are Miller compensation, which has compensation capacitor ($C_{m}$) and zero nulling resistor ($R_{Z}$), in this design $R_{Z}$ has been implemented with PMOS transistor along with transconductance ($g_{m2}$) of second stage, which is set by current is this stage in order to push non dominant pole ($f_{nd}$) to a higher frequency in order to get better gain band width product(GBW) and good phase margin.
{"title":"92dB DC-Gain Two-Stage Class AB Fully-Differentail Op-amp","authors":"M. Shuaib","doi":"10.1109/ICICM50929.2020.9292240","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292240","url":null,"abstract":"To design data converters main challenges are high resolution, high speed, and low power. Operational amplifiers (op-amps) are core building blocks in such mixed signal systems to overcome these issues. As high resolution is linked to op-amp's high dc gain and high speed demands single pole response and large unity gain frequency. This paper deals with design of two stage opamp with class AB as output stage and it has been simulated in 0.18um TSMC CMOS technology. This design achieves high low frequency gain(92dB), good gain bandwidth product(19.07MHz) and low power. To stabilize this op-amp techniques used are Miller compensation, which has compensation capacitor ($C_{m}$) and zero nulling resistor ($R_{Z}$), in this design $R_{Z}$ has been implemented with PMOS transistor along with transconductance ($g_{m2}$) of second stage, which is set by current is this stage in order to push non dominant pole ($f_{nd}$) to a higher frequency in order to get better gain band width product(GBW) and good phase margin.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115790102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：