Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292182
Peng Xu, Zhiqun Cheng, Zhiwei Zhang, MingWen Meng
This paper presented a four-stage E-band power amplifier monolithic microwave integrated circuits(MMIC) based on GaN high-electron-mobility transistor(HEMT) with 60nm of gate length. The layout of the proposed circuit shows that the small-signal gain of 21–23dB and power added efficiency(PAE) of 25.5%–27.5% in the E-band low frequency (71–76GHz). The saturated output power of greater than 32.6dBm(1.8W) is achieved with the power gain of more than 12.6 dB and the linear power gain of more than 20dB. The power density of around 1.4W/mm is achieved at the final stage.
{"title":"High Efficiency GaN HEMT E-Band Power Amplifier MMIC with 1.8W Output Power","authors":"Peng Xu, Zhiqun Cheng, Zhiwei Zhang, MingWen Meng","doi":"10.1109/ICICM50929.2020.9292182","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292182","url":null,"abstract":"This paper presented a four-stage E-band power amplifier monolithic microwave integrated circuits(MMIC) based on GaN high-electron-mobility transistor(HEMT) with 60nm of gate length. The layout of the proposed circuit shows that the small-signal gain of 21–23dB and power added efficiency(PAE) of 25.5%–27.5% in the E-band low frequency (71–76GHz). The saturated output power of greater than 32.6dBm(1.8W) is achieved with the power gain of more than 12.6 dB and the linear power gain of more than 20dB. The power density of around 1.4W/mm is achieved at the final stage.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123636218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292213
Tianyu Liu, Chunfeng Bai
This paper presents a novel voltage follower, which is implemented in a 40nm CMOS process and under a supply of 1.1-V. In order to adapt to limited headroom, a low-threshold PMOS is used as the input transistor, and a novel low-voltage current source is proposed. Hence, high linearity and improved common-mode input range is obtained. The OIP3 reaches 28.7 dBm, and the common-mode input range is 0∼790 mV.
{"title":"A 1.1-V 40-nm CMOS High Linearity Voltage Follower with Improved CM Input Range","authors":"Tianyu Liu, Chunfeng Bai","doi":"10.1109/ICICM50929.2020.9292213","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292213","url":null,"abstract":"This paper presents a novel voltage follower, which is implemented in a 40nm CMOS process and under a supply of 1.1-V. In order to adapt to limited headroom, a low-threshold PMOS is used as the input transistor, and a novel low-voltage current source is proposed. Hence, high linearity and improved common-mode input range is obtained. The OIP3 reaches 28.7 dBm, and the common-mode input range is 0∼790 mV.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129560340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/icicm50929.2020.9292204
{"title":"[Copyright notice]","authors":"","doi":"10.1109/icicm50929.2020.9292204","DOIUrl":"https://doi.org/10.1109/icicm50929.2020.9292204","url":null,"abstract":"","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128476484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292176
Tianyu Shen, Youming Zhang, Xusheng Tang, Junjie Li, F. Huang, N. Jiang
This paper describes a CMOS power amplifier (PA). It discusses how to compromise the size and structure of the transistor in the design of the power amplifier, and to elaborate on the design of the transistor for the parasitics when the frequency increases. The power amplifier designed in this paper adopts a two-stage cascade structure. It works in the Class-AB state. It uses the third-order Chebyshev network for output impedance matching to achieve large saturation power output. A third-order Butterworth network is used as the inter-stage matching, and achieves high power transmission efficiency from the driver stage to the power stage through a Norton transformation. This paper also discusses how to further widen the bandwidth of the power amplifier as well as improving the linearity. Simulation results shows that, the output saturation power (Psat) is greater than 25.5 dBm from 1.1 GHz to 2.9 GHz, the maximum Psat is 27.6 dBm, and the peak power added efficiency (PAE) is 34.9% ∼ 49.4%.
{"title":"A 1.1 ∼ 2.9 GHz High Efficiency CMOS Power Amplifier","authors":"Tianyu Shen, Youming Zhang, Xusheng Tang, Junjie Li, F. Huang, N. Jiang","doi":"10.1109/ICICM50929.2020.9292176","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292176","url":null,"abstract":"This paper describes a CMOS power amplifier (PA). It discusses how to compromise the size and structure of the transistor in the design of the power amplifier, and to elaborate on the design of the transistor for the parasitics when the frequency increases. The power amplifier designed in this paper adopts a two-stage cascade structure. It works in the Class-AB state. It uses the third-order Chebyshev network for output impedance matching to achieve large saturation power output. A third-order Butterworth network is used as the inter-stage matching, and achieves high power transmission efficiency from the driver stage to the power stage through a Norton transformation. This paper also discusses how to further widen the bandwidth of the power amplifier as well as improving the linearity. Simulation results shows that, the output saturation power (Psat) is greater than 25.5 dBm from 1.1 GHz to 2.9 GHz, the maximum Psat is 27.6 dBm, and the peak power added efficiency (PAE) is 34.9% ∼ 49.4%.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"34 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120857471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes the design of a 20-GHz phased-array receiver based on 65nm CMOS. 6-bit phase control and 6-bit gain control are implemented by a passive vector-sum phase shifter with transformer-based compact quadrature generator and programmable gain amplifiers, moreover automatic state-selecting program is employed to realize high-precision phase/gain control. The simulated results indicate that the receiver achieve 29-32 dB gain and better than 2.9 dB noise figure in the frequency range of 18-23 GHz. 1.8 degree RMS phase error and 0.45 dB RMS gain error are obtained for phase control, 0.16 dB RMS gain error and 1.1 degree phase error are obtained for gain control. It is indicated that excellent phase and gain control performances are demonstrated.
{"title":"Design of a 20-GHz Phased-Array Receiver with high-precision Gain and Phase Control in 65nm CMOS","authors":"Xiao Li, Wei Lv, Yongjie Li, Yan Wang, Siwei Huang, Zongming Duan","doi":"10.1109/ICICM50929.2020.9292132","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292132","url":null,"abstract":"This paper describes the design of a 20-GHz phased-array receiver based on 65nm CMOS. 6-bit phase control and 6-bit gain control are implemented by a passive vector-sum phase shifter with transformer-based compact quadrature generator and programmable gain amplifiers, moreover automatic state-selecting program is employed to realize high-precision phase/gain control. The simulated results indicate that the receiver achieve 29-32 dB gain and better than 2.9 dB noise figure in the frequency range of 18-23 GHz. 1.8 degree RMS phase error and 0.45 dB RMS gain error are obtained for phase control, 0.16 dB RMS gain error and 1.1 degree phase error are obtained for gain control. It is indicated that excellent phase and gain control performances are demonstrated.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129064226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292276
W. Lai, S. Jang, Hsiu-An Yeh, M. Juang
This letter designs a low power CMOS LC-tank injection locked frequency tripler (ILFT) fabricated in 90 nm CMOS process. The differential-input and differential-output ILFT circuit is composed of a first-harmonic injection-locked oscillator (ILO) and a pMOSFET mixer-type frequency tripler to supply an injection current to the ILO. At the supply voltage of 0.4 V, the free-running oscillation frequency of the ILO is from 12.39 GHz to 12.86 GHz. The dc power consumption is 0.312 mW. At the incident power of 0 dBm, the input locking range is from the incident frequency 3.5 GHz to 5.2 GHz to provide an output signal source from the frequency 10.5 GHz to 15.6 GHz.
{"title":"A Low-Power Injection-Locked Frequency Tripler in 90 nm CMOS Technology","authors":"W. Lai, S. Jang, Hsiu-An Yeh, M. Juang","doi":"10.1109/ICICM50929.2020.9292276","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292276","url":null,"abstract":"This letter designs a low power CMOS LC-tank injection locked frequency tripler (ILFT) fabricated in 90 nm CMOS process. The differential-input and differential-output ILFT circuit is composed of a first-harmonic injection-locked oscillator (ILO) and a pMOSFET mixer-type frequency tripler to supply an injection current to the ILO. At the supply voltage of 0.4 V, the free-running oscillation frequency of the ILO is from 12.39 GHz to 12.86 GHz. The dc power consumption is 0.312 mW. At the incident power of 0 dBm, the input locking range is from the incident frequency 3.5 GHz to 5.2 GHz to provide an output signal source from the frequency 10.5 GHz to 15.6 GHz.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132372829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292261
Zhiqiang Lu, Yuze Niu, Zhongjian Chen, Bowei An, Yacong Zhang, Wengao Lu
This paper presents a low power cryogenic readout integrated circuit(ROIC) with large charge handling capacity for $640times 512$ infrared focal plane array(IRFPA). An innovative structure using two-stage cascaded source followers in output buffer circuit is proposed to reduce the power consumption of the readout integrated circuit and ensure high linearity of the output voltage. Besides, the area of the integration capacitor in pixel array is maintained as large as possible to ensure large charge handling capacity through a special-shape layout structure. The readout integrated circuit implements frame rate of 100Hz, charge handling capacity of 7.28Me−, nonlinearity of 0.87‰ and power consumption of 61mW with $4times 10text{MHz}$ output rate when the integration mode is integration while reading(IWR).
{"title":"A Low Power High Linearity Cryogenic Readout Integrated Circuit with Large Charge Handling Capacity for $10mumathrm{m}$ Pitch $640times 512$ Infrared Focal Plane Array","authors":"Zhiqiang Lu, Yuze Niu, Zhongjian Chen, Bowei An, Yacong Zhang, Wengao Lu","doi":"10.1109/ICICM50929.2020.9292261","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292261","url":null,"abstract":"This paper presents a low power cryogenic readout integrated circuit(ROIC) with large charge handling capacity for $640times 512$ infrared focal plane array(IRFPA). An innovative structure using two-stage cascaded source followers in output buffer circuit is proposed to reduce the power consumption of the readout integrated circuit and ensure high linearity of the output voltage. Besides, the area of the integration capacitor in pixel array is maintained as large as possible to ensure large charge handling capacity through a special-shape layout structure. The readout integrated circuit implements frame rate of 100Hz, charge handling capacity of 7.28Me−, nonlinearity of 0.87‰ and power consumption of 61mW with $4times 10text{MHz}$ output rate when the integration mode is integration while reading(IWR).","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128770134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In order to improve output power of Si-based transmitter, a Ku-band highly-integrated power amplifier is designed, fabricated and measured. The proposed amplifier adopts a two-stage common-source differential topology, and capacitor-neutralized technology is used both stages in order to enhance the stability and gain performance of amplifier by neutralizing the gate-drain parasitic capacitance. For improving the output power, the second-stage employ a two-way power-combining structure, and the transformer-based power combiner is designed according to the optimum impedance of power matching. The measured results indicate that the power amplifier achieve 26.8 dB gain, 17.4 dBm 1-dB-compressed output power, 22.6 dBm saturated output power and 30% peak power added efficiency at 15.5 GHz with 570 mW DC power consumption.
{"title":"A Ku-Band High-Integrated CMOS Power Amplifier","authors":"Xiao Li, Wei Lv, Yongjie Li, Yan Wang, Siwei Huang, Zongming Duan","doi":"10.1109/ICICM50929.2020.9292263","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292263","url":null,"abstract":"In order to improve output power of Si-based transmitter, a Ku-band highly-integrated power amplifier is designed, fabricated and measured. The proposed amplifier adopts a two-stage common-source differential topology, and capacitor-neutralized technology is used both stages in order to enhance the stability and gain performance of amplifier by neutralizing the gate-drain parasitic capacitance. For improving the output power, the second-stage employ a two-way power-combining structure, and the transformer-based power combiner is designed according to the optimum impedance of power matching. The measured results indicate that the power amplifier achieve 26.8 dB gain, 17.4 dBm 1-dB-compressed output power, 22.6 dBm saturated output power and 30% peak power added efficiency at 15.5 GHz with 570 mW DC power consumption.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129055368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292208
Huan Li, Shenghua Zhai, Wei Wang
This paper proposes a Modified Chip-By-Chip (M-CBC) algorithm for iterative multi-user detector in Scrambled Coded Multiple Access (SCMA) systems. In the traditional SCMA system receiver, the number of iterative times is fixed and the best performance can only achieve by setting a larger iterative time, which results the system in poor flexibility. The M-CBC algorithm can adapt the number of iterations according to the convergence threshold calculated by the soft information of decoder. It solves the problem of how to set the iterative times and the simulation results show that the algorithm in this paper reduces the complexity of the receiver without losing system performance.
{"title":"A Multi-User Detector with Adaptive Iterative times in Scrambled Coded Multiple Access (SCMA) Systems","authors":"Huan Li, Shenghua Zhai, Wei Wang","doi":"10.1109/ICICM50929.2020.9292208","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292208","url":null,"abstract":"This paper proposes a Modified Chip-By-Chip (M-CBC) algorithm for iterative multi-user detector in Scrambled Coded Multiple Access (SCMA) systems. In the traditional SCMA system receiver, the number of iterative times is fixed and the best performance can only achieve by setting a larger iterative time, which results the system in poor flexibility. The M-CBC algorithm can adapt the number of iterations according to the convergence threshold calculated by the soft information of decoder. It solves the problem of how to set the iterative times and the simulation results show that the algorithm in this paper reduces the complexity of the receiver without losing system performance.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114905556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292257
Leiyi Wang, Chunfeng Bai, Heming Zhao
A novel beat-frequency (BF) time quantizer with zero steady-state offset is proposed. The digital low-dropout (DLDO) regulator based on this quantizer can eliminate its inherent steady-state output error caused by the previous quantizer, thus improving its output accuracy (OA). At the same time, this quantizer retains the characteristic of adaptive sampling clock. So that it has the advantages of zero steady-state offset, high quantization resolution, fast transient response speed and low power consumption. This paper designs the proposed quantizer based on a 40-nm technology and simulates it at only 1V supply voltage. The simulation results show that its steady-state offset is zero.
{"title":"A Novel Beat-Frequency Time Quantizer With Zero Steady-State Offset For Fully Integrated Digital LDOs","authors":"Leiyi Wang, Chunfeng Bai, Heming Zhao","doi":"10.1109/ICICM50929.2020.9292257","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292257","url":null,"abstract":"A novel beat-frequency (BF) time quantizer with zero steady-state offset is proposed. The digital low-dropout (DLDO) regulator based on this quantizer can eliminate its inherent steady-state output error caused by the previous quantizer, thus improving its output accuracy (OA). At the same time, this quantizer retains the characteristic of adaptive sampling clock. So that it has the advantages of zero steady-state offset, high quantization resolution, fast transient response speed and low power consumption. This paper designs the proposed quantizer based on a 40-nm technology and simulates it at only 1V supply voltage. The simulation results show that its steady-state offset is zero.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126243925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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