The past five years has witnessed tremendous success of deep learning (DL) algorithm in the computer vision field, attributing to its high degree of accuracy on numerous visual tasks. Unfortunately, for the development of programmable vision chips, algorithm verification remains a major challenge due to the high computational complexity of the DL neural network. In this paper, we propose a novel chip-level verification method to address the common issues including low efficiency and poor reusability in verifying vision chips. In contrast to the block-level verification technique, this method focuses on the rapid implementation of the complete DL algorithm in chip-level verification, fulfilling the advanced demands of vision chip prior to the tape-out. The experiments on MobileNet-v1 indicates the significant reduction of the simulation time and debugging overheads via the proposed verification method.
{"title":"A Chip-Level Verification Method for Programmable Vision Chip Based on Deep Learning Algorithms","authors":"Xuemin Zheng, Mingxin Zhao, Qian Luo, Shuangming Yu, Liyuan Liu, N. Wu","doi":"10.1109/ICICM50929.2020.9292281","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292281","url":null,"abstract":"The past five years has witnessed tremendous success of deep learning (DL) algorithm in the computer vision field, attributing to its high degree of accuracy on numerous visual tasks. Unfortunately, for the development of programmable vision chips, algorithm verification remains a major challenge due to the high computational complexity of the DL neural network. In this paper, we propose a novel chip-level verification method to address the common issues including low efficiency and poor reusability in verifying vision chips. In contrast to the block-level verification technique, this method focuses on the rapid implementation of the complete DL algorithm in chip-level verification, fulfilling the advanced demands of vision chip prior to the tape-out. The experiments on MobileNet-v1 indicates the significant reduction of the simulation time and debugging overheads via the proposed verification method.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130462023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292288
Shu-rui Cao, Qingkui Yu, He Wang, Yi Sun, He Lv, B. Mei, Morigen, Pengwei Li, Hongwei Zhang, M. Tang
Silicon Carbide (SiC) Junction Barrier Schottky Diodes (JBS Diodes) were exposed to 50MeV and 90MeV protons up to a fluence of $5times 10^{10}text{cm}^{-2}$. During irradiation, the reverse leakage current decreased with the accumulation of fluence and no SEB occurred. By comparing the electrical characteristics before and after irradiation, it was analyzed that leakage current decreasing was related to the increase of barrier height and the reduction of carrier concentration. It was considered that no SEB occurring was associated with the lower proton fluence and biased voltage.
{"title":"Radiation Effects on Silicon Carbide Junction Barrier Schottky Diodes Caused by High Energy Proton","authors":"Shu-rui Cao, Qingkui Yu, He Wang, Yi Sun, He Lv, B. Mei, Morigen, Pengwei Li, Hongwei Zhang, M. Tang","doi":"10.1109/ICICM50929.2020.9292288","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292288","url":null,"abstract":"Silicon Carbide (SiC) Junction Barrier Schottky Diodes (JBS Diodes) were exposed to 50MeV and 90MeV protons up to a fluence of $5times 10^{10}text{cm}^{-2}$. During irradiation, the reverse leakage current decreased with the accumulation of fluence and no SEB occurred. By comparing the electrical characteristics before and after irradiation, it was analyzed that leakage current decreasing was related to the increase of barrier height and the reduction of carrier concentration. It was considered that no SEB occurring was associated with the lower proton fluence and biased voltage.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126917672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292264
Fangyuan Ren, Dezhi Xing, Jun Huang, Sizhu Shao, Shuai Tang, Yao Wang
A segmented Mach-Zehnder Modulators (MZM) driver using 0.13 mumathrm{m}$ SiGe BICMOS with a simulated differential output swing of 3 Vppd and total power consumption of 0.98W is reported in this paper. A compact modeling of the Segmented-Electrode MZM designed using Verilog-A is developed for hybrid BICMOS and photonic system-level simulation in integrated circuit (IC) design environment. Six sub-blocks of the Segmented-Electrode MZM in silicon photonic process platform are discussed and critical device functions of each sub-block is given. A good open eye diagram of the optical output power at 25 Gb/s data rate is shown in this paper as a co-simulation result. The transmitter's −3 dB bandwidth is 23 GHz. The whole Segmented-Electrode MZM transmitter achieves an extinction ratio of 9 dB.
本文报道了一种采用0.13 mu maththrm {m}$ SiGe BICMOS的分段马赫-曾德尔调制器(MZM)驱动器，模拟差分输出摆幅为3 Vppd，总功耗为0.98W。在集成电路(IC)设计环境下，利用Verilog-A软件设计了一个紧凑的分段电极MZM模型，用于混合BICMOS和光子系统级仿真。讨论了硅光子加工平台中分段电极MZM的6个子模块，给出了每个子模块的关键器件功能。作为联合仿真结果，本文给出了在25gb /s数据速率下光输出功率的良好开眼图。发射机的- 3db带宽为23ghz。整个分段电极MZM发射机的消光比达到9db。
{"title":"Compact Modeling and Photoelectric Co-simulation of Hybrid BICMOS-Photonic Segmented-Electrode MZM Transmitter","authors":"Fangyuan Ren, Dezhi Xing, Jun Huang, Sizhu Shao, Shuai Tang, Yao Wang","doi":"10.1109/ICICM50929.2020.9292264","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292264","url":null,"abstract":"A segmented Mach-Zehnder Modulators (MZM) driver using 0.13 mumathrm{m}$ SiGe BICMOS with a simulated differential output swing of 3 Vppd and total power consumption of 0.98W is reported in this paper. A compact modeling of the Segmented-Electrode MZM designed using Verilog-A is developed for hybrid BICMOS and photonic system-level simulation in integrated circuit (IC) design environment. Six sub-blocks of the Segmented-Electrode MZM in silicon photonic process platform are discussed and critical device functions of each sub-block is given. A good open eye diagram of the optical output power at 25 Gb/s data rate is shown in this paper as a co-simulation result. The transmitter's −3 dB bandwidth is 23 GHz. The whole Segmented-Electrode MZM transmitter achieves an extinction ratio of 9 dB.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121526964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292205
Chao Yan, Z. Zhan, Hao Song, Shuaishuai Hu
A Ka band highly integrated multifunctional board for active phased array antenna is proposed based on multilayer microwave and digital composite board technology. The antenna radiation array, RF feed network, power divider network, beam control distribution network and other circuits are integrated in the board. The key microwave circuits and interconnections in the multifunctional board are analyzed and optimized by simulation software. The simulation results show that the design satisfied the requirements of the system appropriately. The size of multifunctional board is only $173text{mm}times 40text{mm}times 3.4text{mm}$, and the total weight is less than 60g, which has a bright application prospect on the platforms where the volume and weight are strictly limited.
{"title":"Design of a Highly Integrated Multifunctional Microwave Digital Composite Board for Active Phased Array Antenna","authors":"Chao Yan, Z. Zhan, Hao Song, Shuaishuai Hu","doi":"10.1109/ICICM50929.2020.9292205","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292205","url":null,"abstract":"A Ka band highly integrated multifunctional board for active phased array antenna is proposed based on multilayer microwave and digital composite board technology. The antenna radiation array, RF feed network, power divider network, beam control distribution network and other circuits are integrated in the board. The key microwave circuits and interconnections in the multifunctional board are analyzed and optimized by simulation software. The simulation results show that the design satisfied the requirements of the system appropriately. The size of multifunctional board is only $173text{mm}times 40text{mm}times 3.4text{mm}$, and the total weight is less than 60g, which has a bright application prospect on the platforms where the volume and weight are strictly limited.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123101057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292272
Hao Guo, Youming Zhang, Xusheng Tang, Junjie Li, F. Huang, N. Jiang
In this paper, a fully integrated bandwidth tunable low-pass filter based on 0.13 mu mathrm{m}$ CMOS technology is proposed. Active-RC structure is selected as the basic filtering unit. In order to achieve better suppression characteristics, 3-stage Sallen-Key second-order low-pass filter units are adopted as cascading. The filter tunable by 15 steps from 4 to 60 MHz in steps of 4 MHz. The double cutoff frequency suppression is greater than 30dB and the IIP3 is 14.2dBm. The power supply voltage used for this chip is 1.2V with occupying 0.2 mm2 area.
本文提出了一种基于0.13 mu mathrm{m}$ CMOS技术的全集成带宽可调低通滤波器。选择Active-RC结构作为基本过滤单元。为了获得更好的抑制特性，采用三级Sallen-Key二阶低通滤波器单元进行级联。该滤波器可调15步从4到60兆赫在4兆赫的步骤。双截止频率抑制大于30dB, IIP3为14.2dBm。该芯片使用的电源电压为1.2V，占地面积为0.2 mm2。
{"title":"Design of CMOS Bandwidth Tunable Low-Pass Filter","authors":"Hao Guo, Youming Zhang, Xusheng Tang, Junjie Li, F. Huang, N. Jiang","doi":"10.1109/ICICM50929.2020.9292272","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292272","url":null,"abstract":"In this paper, a fully integrated bandwidth tunable low-pass filter based on 0.13 mu mathrm{m}$ CMOS technology is proposed. Active-RC structure is selected as the basic filtering unit. In order to achieve better suppression characteristics, 3-stage Sallen-Key second-order low-pass filter units are adopted as cascading. The filter tunable by 15 steps from 4 to 60 MHz in steps of 4 MHz. The double cutoff frequency suppression is greater than 30dB and the IIP3 is 14.2dBm. The power supply voltage used for this chip is 1.2V with occupying 0.2 mm2 area.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124965263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292194
He Lv, Hongwei Zhang, B. Mei, Qingkui Yu, Yi Sun, Pengwei Li
Non-volatile memories play important roles in aerospace electronic systems for data storage. Among them, the resistive random access memory (ReRAM) is a non-volatile memory with no charge storage. ReRAM has the advantages of fast erase speed, high storage density, high repetition times, multiple storage and three-dimensional storage. This paper introduces the working principle of ReRAM, selects a typical commercial ReRAM memory as the research object, and conducts the heavy ion and proton single event effect sensitivity test. According to the test results, the sensitive parts of the chip are analyzed. The functional interrupts rate of single event effect on orbit is calculated and predicted by using the special software foreCAST, and the specific suggestions for on orbit application are given. It is proved that the device has good anti-radiation performance by flight test.
{"title":"Research on Heavy Ion and Proton Irradiation Test of a ReRAM Memory","authors":"He Lv, Hongwei Zhang, B. Mei, Qingkui Yu, Yi Sun, Pengwei Li","doi":"10.1109/ICICM50929.2020.9292194","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292194","url":null,"abstract":"Non-volatile memories play important roles in aerospace electronic systems for data storage. Among them, the resistive random access memory (ReRAM) is a non-volatile memory with no charge storage. ReRAM has the advantages of fast erase speed, high storage density, high repetition times, multiple storage and three-dimensional storage. This paper introduces the working principle of ReRAM, selects a typical commercial ReRAM memory as the research object, and conducts the heavy ion and proton single event effect sensitivity test. According to the test results, the sensitive parts of the chip are analyzed. The functional interrupts rate of single event effect on orbit is calculated and predicted by using the special software foreCAST, and the specific suggestions for on orbit application are given. It is proved that the device has good anti-radiation performance by flight test.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131105400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In order to meet the needs of training, a simulator for operation and maintenance of electronic control system is developed as a kind of teaching and training equipment. The simulated training device can not only meet all the requirements of the working process of the real simulation of electronic control system, but also use the computer visualization technology and virtual technology, has a good man-machine interface, clear graphics and quick operation function, real-time simulation of launchers work, in the form of intuitive vivid real-time display the working state and various performance parameters of electric control system and provides a good visualization environment. At the same time, the system can also be on the computer host, operation panel fault settings, fault data management, sums up the law of failure, provides scientific basis for the electronic control system maintenance and maintenance equipment reserve, to improve the ability of analysis and problem solving of maintenance personnel.
{"title":"Design and Implementation of Hardware Circuit of Operation and Maintenance Simulator for an Electronic Control System","authors":"Xuedong Xue, Xude Cheng, Jian Qin, Shuai Zhang, Wei Peng","doi":"10.1109/ICICM50929.2020.9292184","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292184","url":null,"abstract":"In order to meet the needs of training, a simulator for operation and maintenance of electronic control system is developed as a kind of teaching and training equipment. The simulated training device can not only meet all the requirements of the working process of the real simulation of electronic control system, but also use the computer visualization technology and virtual technology, has a good man-machine interface, clear graphics and quick operation function, real-time simulation of launchers work, in the form of intuitive vivid real-time display the working state and various performance parameters of electric control system and provides a good visualization environment. At the same time, the system can also be on the computer host, operation panel fault settings, fault data management, sums up the law of failure, provides scientific basis for the electronic control system maintenance and maintenance equipment reserve, to improve the ability of analysis and problem solving of maintenance personnel.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116512915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292306
Michael Chang
This paper provides supply-induced jitter-aware sensitivity and systematic modeling approach for analyzing supply noise induced timing jitter in high-speed I/O interfaces with using the Laplace transform method to perform the jitter generated by the supply noise in the time domain compared to present general analysis methods. One of the proposed models is the supply induced jitter transfer function. The proposed methodology provides an appropriate level of correlation and efficient method on high speed interface at system level the approach captures the interaction of the blocks through the regulators and the power distribution network (PDN). The goal is to provide sufficient performance for efficient system solutions in the early stages of design and achieve success at the system level.
{"title":"A Novel Laplace Transform Modeling for Supply Induced Jitter Sensitivity of SERDES Transmitter","authors":"Michael Chang","doi":"10.1109/ICICM50929.2020.9292306","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292306","url":null,"abstract":"This paper provides supply-induced jitter-aware sensitivity and systematic modeling approach for analyzing supply noise induced timing jitter in high-speed I/O interfaces with using the Laplace transform method to perform the jitter generated by the supply noise in the time domain compared to present general analysis methods. One of the proposed models is the supply induced jitter transfer function. The proposed methodology provides an appropriate level of correlation and efficient method on high speed interface at system level the approach captures the interaction of the blocks through the regulators and the power distribution network (PDN). The goal is to provide sufficient performance for efficient system solutions in the early stages of design and achieve success at the system level.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"245 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121876038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292298
Jian Yang, Xiangliang Jin
In the field of medical microwave hyperthermia, if the detection of the heating temperature is inaccurate, it will seriously endanger the health of patients. However, the active temperature sensor is severely affected by external electromagnetic interference, and the temperature measurement accuracy cannot reach the desired effect. Therefore, the fluorescent optical fiber temperature sensor has been widely used in the above mentioned complicated fields due to its insulation characteristics. In order to further improve the detection accuracy of the fluorescent fiber temperature sensor, the algorithm for extracting the fluorescence lifetime is a key part of the system to improve the accuracy. In this paper, the accuracy of the fluorescence lifetime extracted by the integral area ratio algorithm, FFT algorithm, and least squares fitting algorithm is verified by simulation and experiments. According to the simulation results, the FFT algorithm and the integral area ratio algorithm are completely unaffected by the DC bias of the system, and the least squares fitting algorithm is more sensitive to the DC bias of the system. Compared with the integral area ratio algorithm and the least squares fitting algorithm, the absolute errors of the fluorescence lifetime extracted by the FFT algorithm are reduced by 31% and 45%, respectively. In addition, the running time of the three data processing algorithms was also tested. The test results show that the processing time of the integral area ratio algorithm is reduced by about 99.55% and 93% respectively compared with the least squares fitting algorithm and the FFT algorithm. In summary, the simulation and experimental test results in this paper can provide an important reference for the data processing implementation of fluorescent optical fiber temperature sensors.
{"title":"Design and Analysis of Data Processing Algorithm for Fluorescent Optical Fiber Temperature Sensor","authors":"Jian Yang, Xiangliang Jin","doi":"10.1109/ICICM50929.2020.9292298","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292298","url":null,"abstract":"In the field of medical microwave hyperthermia, if the detection of the heating temperature is inaccurate, it will seriously endanger the health of patients. However, the active temperature sensor is severely affected by external electromagnetic interference, and the temperature measurement accuracy cannot reach the desired effect. Therefore, the fluorescent optical fiber temperature sensor has been widely used in the above mentioned complicated fields due to its insulation characteristics. In order to further improve the detection accuracy of the fluorescent fiber temperature sensor, the algorithm for extracting the fluorescence lifetime is a key part of the system to improve the accuracy. In this paper, the accuracy of the fluorescence lifetime extracted by the integral area ratio algorithm, FFT algorithm, and least squares fitting algorithm is verified by simulation and experiments. According to the simulation results, the FFT algorithm and the integral area ratio algorithm are completely unaffected by the DC bias of the system, and the least squares fitting algorithm is more sensitive to the DC bias of the system. Compared with the integral area ratio algorithm and the least squares fitting algorithm, the absolute errors of the fluorescence lifetime extracted by the FFT algorithm are reduced by 31% and 45%, respectively. In addition, the running time of the three data processing algorithms was also tested. The test results show that the processing time of the integral area ratio algorithm is reduced by about 99.55% and 93% respectively compared with the least squares fitting algorithm and the FFT algorithm. In summary, the simulation and experimental test results in this paper can provide an important reference for the data processing implementation of fluorescent optical fiber temperature sensors.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127713532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292181
Kui Wang, Lu Tang
This paper presents a millimeter-wave digitally controlled oscillator (DCO) using the digital controlled transmission lines (TLs) technology to achieve a wide frequency tuning range. To optimize frequency resolution of the fine tuning, a transformer is designed to attenuate the frequency fine tuning sensitivity of the C-2C switched capacitor (SC) ladder circuit. The simulated results show that the proposed DCO attains frequency tuning range from 77.1 to 88.6GHz. Its frequency resolution is around 200kHz. The phase noise is −94.4 dBc/Hz at 1-MHz frequency offset at 77.5GHz. The DCO is fabricated in 40nm CMOS process, and its core chip size is only 0.067mm2.
{"title":"A 77.1-88.6 GHz Digitally Controlled Oscillator with High Frequency Resolution in 40nm CMOS","authors":"Kui Wang, Lu Tang","doi":"10.1109/ICICM50929.2020.9292181","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292181","url":null,"abstract":"This paper presents a millimeter-wave digitally controlled oscillator (DCO) using the digital controlled transmission lines (TLs) technology to achieve a wide frequency tuning range. To optimize frequency resolution of the fine tuning, a transformer is designed to attenuate the frequency fine tuning sensitivity of the C-2C switched capacitor (SC) ladder circuit. The simulated results show that the proposed DCO attains frequency tuning range from 77.1 to 88.6GHz. Its frequency resolution is around 200kHz. The phase noise is −94.4 dBc/Hz at 1-MHz frequency offset at 77.5GHz. The DCO is fabricated in 40nm CMOS process, and its core chip size is only 0.067mm2.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123626554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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