CAN-FD bus protocol has a high effective data rate and is widely used in automobile internal bus. This paper introduces the design of CAN-FD protocol controller driver based on Cortex-M0 processor, analyzes the development process of CAN-FD driver in detail, realizes multi node communication by communicating with other CAN-FD nodes, and uses CAN-FD analyzer and logic analyzer to grasp the CAN-FD frame on the physical bus. Through the actual CAN-FD communication project, this paper completes the design process of the driven, and provides a reference value for the driven design of other CAN-FD devices.
{"title":"The Driven Design of CAN-FD Bus Controller Based on Cortex-M0","authors":"Zifeng Wang, Shuqin Geng, Xiaohong Peng, Yan Zhang, Shuaiqi Yan, Haonan Tang","doi":"10.1109/ICICM50929.2020.9292197","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292197","url":null,"abstract":"CAN-FD bus protocol has a high effective data rate and is widely used in automobile internal bus. This paper introduces the design of CAN-FD protocol controller driver based on Cortex-M0 processor, analyzes the development process of CAN-FD driver in detail, realizes multi node communication by communicating with other CAN-FD nodes, and uses CAN-FD analyzer and logic analyzer to grasp the CAN-FD frame on the physical bus. Through the actual CAN-FD communication project, this paper completes the design process of the driven, and provides a reference value for the driven design of other CAN-FD devices.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"781 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115758998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292250
Jiayi Wang, N. Tan, Yangfan Zhou, Ting Li, Junhu Xia
The study presents a module-level and system-level hierarchical UVM (Universal Verification Methodology) verification platform for a RISC-V SoC. At the module level, the platform generates constrained random stimulants to drive testing for module functions. The degree of the verification completeness is measured through the code coverage and the functional coverage. At the system level, the platform integrates the module-level environments and analyzes the interrupt and the sleep-and-wake-up characteristics of the RISC-V core. The timing correctness of the signals is checked by assertions. Compared with FPGA verification, the UVM verification platform has the advantages of shorter cycle, higher efficiency, better reusability, and makes it easier to measure the coverage. The simulation results show that the functions of the RISC-V SoC are correct and the functional coverage meets the requirements.
{"title":"A UVM Verification Platform for RISC-V SoC from Module to System Level","authors":"Jiayi Wang, N. Tan, Yangfan Zhou, Ting Li, Junhu Xia","doi":"10.1109/ICICM50929.2020.9292250","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292250","url":null,"abstract":"The study presents a module-level and system-level hierarchical UVM (Universal Verification Methodology) verification platform for a RISC-V SoC. At the module level, the platform generates constrained random stimulants to drive testing for module functions. The degree of the verification completeness is measured through the code coverage and the functional coverage. At the system level, the platform integrates the module-level environments and analyzes the interrupt and the sleep-and-wake-up characteristics of the RISC-V core. The timing correctness of the signals is checked by assertions. Compared with FPGA verification, the UVM verification platform has the advantages of shorter cycle, higher efficiency, better reusability, and makes it easier to measure the coverage. The simulation results show that the functions of the RISC-V SoC are correct and the functional coverage meets the requirements.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114599216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292260
Y. Morgan, M. Abouelatta, M. El-Banna, A. Shaker
This paper proposes a novel Si-TFET based on a tapered channel structure. The taper-channel design presented in this work provides a higher thickness at the source side than at the drain side, whereas the gate oxide is lesser at the source than at the drain side. The structure is investigated by varying the taper channel length and thickness using Silvaco TCAD simulation. It is found that, by engineering a taper length of 30 nm and thickness of 6 nm, a minimum subthreshold and ambipolar conduction as well as higher ON/OFF current ratio are achieved. The ambipolar current of the optimized structure is approximately $10^{-14} mathrm{A}/mu mathrm{m}$ compared to 10−10 A/µm regarding the conventional structure. Also, the OFF current is decreased to about $10^{-17} mathrm{A}/mu mathrm{m}$ with a little drop in ION; however, an increase in the (ON/OFF) current ratio is obtained.
{"title":"Tapered-Shape Channel Engineering for Suppression of Ambipolar Current in TFET","authors":"Y. Morgan, M. Abouelatta, M. El-Banna, A. Shaker","doi":"10.1109/ICICM50929.2020.9292260","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292260","url":null,"abstract":"This paper proposes a novel Si-TFET based on a tapered channel structure. The taper-channel design presented in this work provides a higher thickness at the source side than at the drain side, whereas the gate oxide is lesser at the source than at the drain side. The structure is investigated by varying the taper channel length and thickness using Silvaco TCAD simulation. It is found that, by engineering a taper length of 30 nm and thickness of 6 nm, a minimum subthreshold and ambipolar conduction as well as higher ON/OFF current ratio are achieved. The ambipolar current of the optimized structure is approximately $10^{-14} mathrm{A}/mu mathrm{m}$ compared to 10−10 A/µm regarding the conventional structure. Also, the OFF current is decreased to about $10^{-17} mathrm{A}/mu mathrm{m}$ with a little drop in ION; however, an increase in the (ON/OFF) current ratio is obtained.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"40 34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116605696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292144
Changhang Luo, Jietao Diao, Changlin Chen
The processing of Convolutional Neural Network (CNN) involves a large amount of data movements and thus usually causes significant latency and energy consumption. Resistive Random Access Memory (ReRAM) based CNN accelerators with Processing-In-Memory (PIM) architecture are deemed as a promising solution to improve the energy efficiency. However, the weight mapping methods and the corresponding dataflow in state of the art accelerators are not yet well designed to fully explore the possible data reuse in the CNN inference. In this paper, we propose a new ReRAM based PIM architecture named FullReuse in which all types of data reuse are realized with novel simple hardware circuit. The latency and energy consumption in the buffer and interconnect for data movements are minimized. Experiments with the VGG-network on the NeuroSim platform shows that the FullReuse can achieve up to 1.6 times improvement in the processing speed when compare with state of the art accelerators with comparable power efficiency and 14% area overhead.
{"title":"FullReuse: A Novel ReRAM-based CNN Accelerator Reusing Data in Multiple Levels","authors":"Changhang Luo, Jietao Diao, Changlin Chen","doi":"10.1109/ICICM50929.2020.9292144","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292144","url":null,"abstract":"The processing of Convolutional Neural Network (CNN) involves a large amount of data movements and thus usually causes significant latency and energy consumption. Resistive Random Access Memory (ReRAM) based CNN accelerators with Processing-In-Memory (PIM) architecture are deemed as a promising solution to improve the energy efficiency. However, the weight mapping methods and the corresponding dataflow in state of the art accelerators are not yet well designed to fully explore the possible data reuse in the CNN inference. In this paper, we propose a new ReRAM based PIM architecture named FullReuse in which all types of data reuse are realized with novel simple hardware circuit. The latency and energy consumption in the buffer and interconnect for data movements are minimized. Experiments with the VGG-network on the NeuroSim platform shows that the FullReuse can achieve up to 1.6 times improvement in the processing speed when compare with state of the art accelerators with comparable power efficiency and 14% area overhead.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116947319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292236
Lulu Li, Yingmei Chen, En Zhu
A 28Gbaud/s PAM4 large-swing optical modulator driver is designed in 0.13-mu mathrm{m}$ SiGe BiCOMS technology. The designed driver includes variable gain amplifier, continuous time linear equalizer and main driver stage. Group delay peak-peak value and bandwidth bottleneck from MZM are challenges to achieve high speed optical interconnect at 28Gbaud/s. A compensation technique of de-emphasis and pre-emphasis is also adopted to reduce group-delay variation and broaden bandwidth, respectively. Simulation results show that the driver features gain of 20dB, −3dB bandwidth of 25GHz by utilizing pre-emphasis circuit and CTLE, and it delivers a differential output swing of 4Vpp. The group-delay variation of the driver is 3.1ps by using de-emphasis circuit, which is less than ±0.1UI.
{"title":"A 28Gbaud/s 4Vpp PAM4 MZ Modulator Driver in 0.13mu mathrm{m}$ SiGe BiCMOS Technology","authors":"Lulu Li, Yingmei Chen, En Zhu","doi":"10.1109/ICICM50929.2020.9292236","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292236","url":null,"abstract":"A 28Gbaud/s PAM4 large-swing optical modulator driver is designed in 0.13-mu mathrm{m}$ SiGe BiCOMS technology. The designed driver includes variable gain amplifier, continuous time linear equalizer and main driver stage. Group delay peak-peak value and bandwidth bottleneck from MZM are challenges to achieve high speed optical interconnect at 28Gbaud/s. A compensation technique of de-emphasis and pre-emphasis is also adopted to reduce group-delay variation and broaden bandwidth, respectively. Simulation results show that the driver features gain of 20dB, −3dB bandwidth of 25GHz by utilizing pre-emphasis circuit and CTLE, and it delivers a differential output swing of 4Vpp. The group-delay variation of the driver is 3.1ps by using de-emphasis circuit, which is less than ±0.1UI.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115970349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292193
Shize Guo, Lu Tang, Xusheng Tang, Qin Li, N. Jiang
In this paper, an 840GHz monolithic frequency tripler is designed based on a $25-mu mathrm{m}$ GaAs substrate and planar Schottky diode. In order to improve the conversion efficiency, an improved balance structure is used in the circuit. This structure balances the RF path while suppressing even harmonics. An electromagnetic model of planar Schottky diodes is established based on physical characteristics. The passive part of the frequency tripler is electromagnetic simulated. At a 10dBm input power, the peak conversion efficiency of the frequency tripler is 5.82%, and the maximum output power is −2.35dBm. In the frequency range of 839 GHz to 849 GHz, the conversion efficiency is typically greater than 3%.
本文设计了一种基于25 μ m GaAs衬底和平面肖特基二极管的840GHz单片三频器。为了提高转换效率，电路中采用了改进的平衡结构。这种结构平衡了射频路径，同时抑制了均匀谐波。基于肖特基二极管的物理特性，建立了平面肖特基二极管的电磁模型。对三倍器的无源部分进行了电磁仿真。在输入功率为10dBm时，三倍器的峰值转换效率为5.82%，最大输出功率为−2.35dBm。在839ghz ~ 849ghz频率范围内，转换效率一般大于3%。
{"title":"An 840GHz GaAs Monolithic Improved Balanced Frequency Tripler","authors":"Shize Guo, Lu Tang, Xusheng Tang, Qin Li, N. Jiang","doi":"10.1109/ICICM50929.2020.9292193","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292193","url":null,"abstract":"In this paper, an 840GHz monolithic frequency tripler is designed based on a $25-mu mathrm{m}$ GaAs substrate and planar Schottky diode. In order to improve the conversion efficiency, an improved balance structure is used in the circuit. This structure balances the RF path while suppressing even harmonics. An electromagnetic model of planar Schottky diodes is established based on physical characteristics. The passive part of the frequency tripler is electromagnetic simulated. At a 10dBm input power, the peak conversion efficiency of the frequency tripler is 5.82%, and the maximum output power is −2.35dBm. In the frequency range of 839 GHz to 849 GHz, the conversion efficiency is typically greater than 3%.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126407177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292155
Haoran Weng, Weilin Xu
Instead of active noise-shaping with power hungry amplifiers, a 2nd order passive noise-shaping module with 8-bit asynchronous successive approximation register (SAR) ADC is presented in this paper. This 2nd order passive noise-shaping module only composes of 4 switches and 4 capacitors, which is benefit for chip area saving. In addition, only one noise-shaping module is needed in differential signal processing, while traditional design needs two modules. The three-input comparator has been optimized to decrease kick-back noise. Simulation results show that the ADC achieves 11.6-bit ENOB with 2MHz signal bandwidth and 80MS/s sampling-rate in 45nm CMOS process, and power consumption is 300uW.
{"title":"A 2MHz-Bandwidth 11.6-bit ENOB Noise-shaping SAR ADC with 2nd Order Passive Integrator","authors":"Haoran Weng, Weilin Xu","doi":"10.1109/ICICM50929.2020.9292155","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292155","url":null,"abstract":"Instead of active noise-shaping with power hungry amplifiers, a 2nd order passive noise-shaping module with 8-bit asynchronous successive approximation register (SAR) ADC is presented in this paper. This 2nd order passive noise-shaping module only composes of 4 switches and 4 capacitors, which is benefit for chip area saving. In addition, only one noise-shaping module is needed in differential signal processing, while traditional design needs two modules. The three-input comparator has been optimized to decrease kick-back noise. Simulation results show that the ADC achieves 11.6-bit ENOB with 2MHz signal bandwidth and 80MS/s sampling-rate in 45nm CMOS process, and power consumption is 300uW.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126124224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a 16-bit 1MS/s successive approximation register (SAR) analog-to-digital converters (ADC) for precision measurement in 180nm technology. High-bit sampling makes the bridge capacitor become unit capacitance, which solves the problem of fractional capacitor mismatch. In addition, thermometer-coded capacitors are used to improve linearity. The prototype achieves 104.3dB spurious-free dynamic range (SFDR) at 3.9kHz input signal while operating at sampling rate of 1 MS/s and the power consumption is 7.85 mW.
{"title":"A 16bit 1MS/s High-Bit Sampling SAR ADC with Improved Binary-Weighted Capacitive Array","authors":"Bowei An, Shoudong Huang, Zhongjian Chen, Zhiqiang Lu, Wengao Lu, Yacong Zhang","doi":"10.1109/ICICM50929.2020.9292270","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292270","url":null,"abstract":"This paper presents a 16-bit 1MS/s successive approximation register (SAR) analog-to-digital converters (ADC) for precision measurement in 180nm technology. High-bit sampling makes the bridge capacitor become unit capacitance, which solves the problem of fractional capacitor mismatch. In addition, thermometer-coded capacitors are used to improve linearity. The prototype achieves 104.3dB spurious-free dynamic range (SFDR) at 3.9kHz input signal while operating at sampling rate of 1 MS/s and the power consumption is 7.85 mW.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"931 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133417076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292233
Yang Wang, Xiangliang Jin
This work proposes a double-snapback dual direction silicon controlled rectifier(DS-DDSCR) electrostatic discharge protection(ESD) device by using the embedded GGNMOS structure. Based on the traditional SCR structure, it is improved by embedded structure and the double-snapback mechanism is used to achieve better voltage clamping capability. The working mechanism of proposed DS-DDSCR is simulated through equivalent circuit and two-dimensional device simulation. The device simulation results show that this double-snapback embedded structure can provide an effective design idea for ESD protection of standard BCD process.
{"title":"Design and Simulation of the Double-Snapback Dual Direction Silicon Controlled Rectifier Device with Embedded GGNMOS Structure","authors":"Yang Wang, Xiangliang Jin","doi":"10.1109/ICICM50929.2020.9292233","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292233","url":null,"abstract":"This work proposes a double-snapback dual direction silicon controlled rectifier(DS-DDSCR) electrostatic discharge protection(ESD) device by using the embedded GGNMOS structure. Based on the traditional SCR structure, it is improved by embedded structure and the double-snapback mechanism is used to achieve better voltage clamping capability. The working mechanism of proposed DS-DDSCR is simulated through equivalent circuit and two-dimensional device simulation. The device simulation results show that this double-snapback embedded structure can provide an effective design idea for ESD protection of standard BCD process.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132959087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292215
Xiaotong Lai, Youming Zhang, Xusheng Tang, Junjie Li, F. Huang, N. Jiang
In this paper, a wideband variable gain amplifier based on 40nm CMOS technology is presented. The VGA consists of two cascaded cascode amplifiers. The common gate transistors are used as switches to control the current injected into the resonator load in order to control voltage gain. A switched capacitor array is implemented in the resonator to control center frequency. The VGA has a frequency range of 13.5 GHz to 18 GHz and achieves a 1 dB bandwidth of 2 GHz. The gain tuning range is −14 dB to 11 dB and −6 dB to 19 dB at low and high band, respectively, with a gain resolution of 1.5 dB. The input 1 dB compression point is about −16 dBm.
本文提出了一种基于40nm CMOS技术的宽带可变增益放大器。VGA由两个级联级联放大器组成。普通栅极晶体管用作开关来控制注入谐振器负载的电流，以控制电压增益。在谐振腔内采用开关电容阵列来控制中心频率。VGA的工作频率范围为13.5 GHz ~ 18ghz, 1db带宽为2ghz。增益调谐范围分别为- 14 dB ~ 11 dB和- 6 dB ~ 19 dB，增益分辨率为1.5 dB。输入1db压缩点约为−16dbm。
{"title":"A Radio Frequency Wideband Variable Gain Amplifier Design Based on 40nm CMOS Technology","authors":"Xiaotong Lai, Youming Zhang, Xusheng Tang, Junjie Li, F. Huang, N. Jiang","doi":"10.1109/ICICM50929.2020.9292215","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292215","url":null,"abstract":"In this paper, a wideband variable gain amplifier based on 40nm CMOS technology is presented. The VGA consists of two cascaded cascode amplifiers. The common gate transistors are used as switches to control the current injected into the resonator load in order to control voltage gain. A switched capacitor array is implemented in the resonator to control center frequency. The VGA has a frequency range of 13.5 GHz to 18 GHz and achieves a 1 dB bandwidth of 2 GHz. The gain tuning range is −14 dB to 11 dB and −6 dB to 19 dB at low and high band, respectively, with a gain resolution of 1.5 dB. The input 1 dB compression point is about −16 dBm.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133882666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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