Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292161
Ma Jie, Yang Fei, Tang HuaiYu
This paper describes the design of a D-band wide-band SPDT switch using 60nm GaN HEMT technology. The broadband characteristic has been realized by using the parasitic capacitance of the off-state HEMTs to form an artificial transmission line. The equivalent circuits of the on and off state HEMTs are developed and the design parameters of the traveling-wave switch have been calculated. The simulation results demonstrate that the insertion loss is less than 7dB, minimum Isolation on off state is 20dB over 130∼150GHz, the chip size is $1.5text{mm}^{ast}1.5text{mm}$.
本文介绍了一种采用60nm GaN HEMT技术的d波段宽带SPDT开关的设计。利用离态hemt的寄生电容形成人工传输线，实现了其宽带特性。设计了导通和关断状态hemt的等效电路，计算了行波开关的设计参数。仿真结果表明，在130 ~ 150GHz范围内，插入损耗小于7dB，最小隔离开关状态为20dB，芯片尺寸为$1.5text{mm}^{ast}1.5text{mm}$。
{"title":"Millimeter-Wave SPDT Switch MMICs With Travelling Wave Concept","authors":"Ma Jie, Yang Fei, Tang HuaiYu","doi":"10.1109/ICICM50929.2020.9292161","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292161","url":null,"abstract":"This paper describes the design of a D-band wide-band SPDT switch using 60nm GaN HEMT technology. The broadband characteristic has been realized by using the parasitic capacitance of the off-state HEMTs to form an artificial transmission line. The equivalent circuits of the on and off state HEMTs are developed and the design parameters of the traveling-wave switch have been calculated. The simulation results demonstrate that the insertion loss is less than 7dB, minimum Isolation on off state is 20dB over 130∼150GHz, the chip size is $1.5text{mm}^{ast}1.5text{mm}$.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131036945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292303
W. Lai
This article presents a 24GHz doppler radar detection, high gain, receiver frontend for cancelling random heart rate sensing by deep neural network (DNN) in noncontact healthcare applications. The proposed heart rate sensing with algorithm, different frequencies and phase offsets are synthesized and integrated with simulation to train the DNN analysis. This article promoted integrated circuit in LNA, Mixer and bandpass filter with array antenna for contribution of doppler radar heart rate detection Experimental results demonstrate that the proposed idea can alleviate the noise cancellation and stable signal when body movement or normal respiration motion for 24GHz doppler radar vital sign detection.
{"title":"Design of Receiver Frontend with Deep Neural Network for Doppler Radar Heart Rate Detection","authors":"W. Lai","doi":"10.1109/ICICM50929.2020.9292303","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292303","url":null,"abstract":"This article presents a 24GHz doppler radar detection, high gain, receiver frontend for cancelling random heart rate sensing by deep neural network (DNN) in noncontact healthcare applications. The proposed heart rate sensing with algorithm, different frequencies and phase offsets are synthesized and integrated with simulation to train the DNN analysis. This article promoted integrated circuit in LNA, Mixer and bandpass filter with array antenna for contribution of doppler radar heart rate detection Experimental results demonstrate that the proposed idea can alleviate the noise cancellation and stable signal when body movement or normal respiration motion for 24GHz doppler radar vital sign detection.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124143065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292198
Yuliang Ma, Chunfeng Bai, Yang Wang, Donghai Qiao
A low noise CMOS bandgap voltage reference is designed using the noise reduction technique of chopper stabilization in this paper. The mechanism of the proposed chopper technique is discussed in detail and the corresponding circuit was designed and fabricated using a high temperature and high pressure CMOS 0.18mu m$ technology. The experimental results show that the output noise power spectral density was reduced by 60dB at 1Hz. In addition, the untrimmed voltage reference has a temperature coefficient in the −45°C to +175°C range of 43ppm/°C (mean) at a +5 V power supply.
{"title":"A Low Noise CMOS Bandgap Voltage Reference Using Chopper Stabilization Technique","authors":"Yuliang Ma, Chunfeng Bai, Yang Wang, Donghai Qiao","doi":"10.1109/ICICM50929.2020.9292198","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292198","url":null,"abstract":"A low noise CMOS bandgap voltage reference is designed using the noise reduction technique of chopper stabilization in this paper. The mechanism of the proposed chopper technique is discussed in detail and the corresponding circuit was designed and fabricated using a high temperature and high pressure CMOS 0.18mu m$ technology. The experimental results show that the output noise power spectral density was reduced by 60dB at 1Hz. In addition, the untrimmed voltage reference has a temperature coefficient in the −45°C to +175°C range of 43ppm/°C (mean) at a +5 V power supply.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116708381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-23DOI: 10.1109/ICICM50929.2020.9292156
Yeran Jin, Bo Zhou, Yujie Liu, Jida Peng
A sub-1-V low-complexity crystal oscillator (XTO) is fabricated in 65-nm CMOS. The proposed crystal oscillator has lower power dissipation and better frequency accuracy performance than reported ones. The crystal oscillator is based on the conventional three-point Colpitts architecture. The oscillator core consists of a constant $g_{mathrm{m}}$ gain stage, a quartz crystal and two load capacitors, followed by a single-ended self-biased band-passed amplifier. Experimental results show that the presented XTO generates a 12-MHz reference clock, achieving the phase noise of −95 dBc/Hz at 100-Hz offset frequency and the frequency inaccuracy of 1.2 ppm. The proposed crystal oscillator has an active area of 0.01 mm2 and the power dissipation is $32 mu mathrm{W}$ from a 0.8-V supply.
{"title":"A 0.8-V Low-Power Low-Cost CMOS Crystal Oscillator with High Frequency Accuracy","authors":"Yeran Jin, Bo Zhou, Yujie Liu, Jida Peng","doi":"10.1109/ICICM50929.2020.9292156","DOIUrl":"https://doi.org/10.1109/ICICM50929.2020.9292156","url":null,"abstract":"A sub-1-V low-complexity crystal oscillator (XTO) is fabricated in 65-nm CMOS. The proposed crystal oscillator has lower power dissipation and better frequency accuracy performance than reported ones. The crystal oscillator is based on the conventional three-point Colpitts architecture. The oscillator core consists of a constant $g_{mathrm{m}}$ gain stage, a quartz crystal and two load capacitors, followed by a single-ended self-biased band-passed amplifier. Experimental results show that the presented XTO generates a 12-MHz reference clock, achieving the phase noise of −95 dBc/Hz at 100-Hz offset frequency and the frequency inaccuracy of 1.2 ppm. The proposed crystal oscillator has an active area of 0.01 mm2 and the power dissipation is $32 mu mathrm{W}$ from a 0.8-V supply.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121661149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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