Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346996
K. Ishibashi, S. Ohbayashi, K. Eikyu, M. Tanizawa, Y. Tsukamoto, K. Osada, M. Miyazaki, M. Yamaoka
The obstacles for low power SOC are leakage and variability of MOS transistors. Many circuit techniques have been proposed to tackle these issues. An adaptive body bias technique for logics and a source line voltage control technique for memories are inevitable techniques. Precise analysis of timing for logics and electrical stability for memories are keys to optimizing low voltage operations and they need precise Spice models that handle the variability
{"title":"Circuit Technologies for Reducing the Power of SOC and Issues on Transistor Models","authors":"K. Ishibashi, S. Ohbayashi, K. Eikyu, M. Tanizawa, Y. Tsukamoto, K. Osada, M. Miyazaki, M. Yamaoka","doi":"10.1109/IEDM.2006.346996","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346996","url":null,"abstract":"The obstacles for low power SOC are leakage and variability of MOS transistors. Many circuit techniques have been proposed to tackle these issues. An adaptive body bias technique for logics and a source line voltage control technique for memories are inevitable techniques. Precise analysis of timing for logics and electrical stability for memories are keys to optimizing low voltage operations and they need precise Spice models that handle the variability","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134050588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346926
A. Kaneko, A. Yagishita, K. Yahashi, T. Kubota, M. Omura, K. Matsuo, I. Mizushima, K. Okano, H. Kawasaki, T. Izumida, T. Kanemura, N. Aoki, A. Kinoshita, J. Koga, S. Inaba, K. Ishimaru, Y. Toyoshima, H. Ishiuchi, K. Suguro, K. Eguchi, Y. Tsunashima
High-performance CMOS-FinFET with dopant-segregated Schottky source/drain (DS-Schottky S/D) technology has been demonstrated. Thanks to the low parasitic resistance in DS-Schottky S/D, high drive current of 960 muA/mum was achieved for nFET with Lg = 15 nm and Wfin =15 nm at Vd= 1.0 V and Ioff= 100 nA/mum. Furthermore, the propagation delay time has been successfully improved down to less than 5 ps in the ring oscillator with DS-Schottky S/D CMOS-FinFET with 15 nm gate length
{"title":"High-Performance FinFET with Dopant-Segregated Schottky Source/Drain","authors":"A. Kaneko, A. Yagishita, K. Yahashi, T. Kubota, M. Omura, K. Matsuo, I. Mizushima, K. Okano, H. Kawasaki, T. Izumida, T. Kanemura, N. Aoki, A. Kinoshita, J. Koga, S. Inaba, K. Ishimaru, Y. Toyoshima, H. Ishiuchi, K. Suguro, K. Eguchi, Y. Tsunashima","doi":"10.1109/IEDM.2006.346926","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346926","url":null,"abstract":"High-performance CMOS-FinFET with dopant-segregated Schottky source/drain (DS-Schottky S/D) technology has been demonstrated. Thanks to the low parasitic resistance in DS-Schottky S/D, high drive current of 960 muA/mum was achieved for nFET with Lg = 15 nm and Wfin =15 nm at Vd= 1.0 V and Ioff= 100 nA/mum. Furthermore, the propagation delay time has been successfully improved down to less than 5 ps in the ring oscillator with DS-Schottky S/D CMOS-FinFET with 15 nm gate length","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134296913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346955
T. Ernst, C. Dupré, C. Isheden, É. Bernard, R. Ritzenthaler, V. Maffini-Alvaro, J. Barbe, F. de Crécy, A. Toffoli, C. Vizioz, S. Borel, F. Andrieu, V. Delaye, D. Lafond, G. Rabillé, J. Hartmann, M. Rivoire, B. Guillaumot, A. Suhm, P. Rivallin, O. Faynot, G. Ghibaudo, S. Deleonibus
Three- and four-level matrices of 15 times 70 nm Si Nano-Beams have been integrated with a novel CMOS gate-all-around process (GAA) down to 80 nm gate length. Thanks to this 3D-GAA extension of a Finfet process, a more than 5times higher current density per layout surface is achieved compared to planar transistors with the same gate stack (HfO 2/TiN/Poly-Si). For the first time, several properties of this novel 3D architecture are explored: (i) HfO2/TiN gate stack is integrated, (ii) electrons and holes mobilities are measured on 150 beams matrices (3 levels) and compared to those of planar transistors (hi) a sub-100nm channel width is demonstrated and (iv) specific 3D integration challenges like zipping between nano-beams are discussed
{"title":"Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack","authors":"T. Ernst, C. Dupré, C. Isheden, É. Bernard, R. Ritzenthaler, V. Maffini-Alvaro, J. Barbe, F. de Crécy, A. Toffoli, C. Vizioz, S. Borel, F. Andrieu, V. Delaye, D. Lafond, G. Rabillé, J. Hartmann, M. Rivoire, B. Guillaumot, A. Suhm, P. Rivallin, O. Faynot, G. Ghibaudo, S. Deleonibus","doi":"10.1109/IEDM.2006.346955","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346955","url":null,"abstract":"Three- and four-level matrices of 15 times 70 nm Si Nano-Beams have been integrated with a novel CMOS gate-all-around process (GAA) down to 80 nm gate length. Thanks to this 3D-GAA extension of a Finfet process, a more than 5times higher current density per layout surface is achieved compared to planar transistors with the same gate stack (HfO 2/TiN/Poly-Si). For the first time, several properties of this novel 3D architecture are explored: (i) HfO2/TiN gate stack is integrated, (ii) electrons and holes mobilities are measured on 150 beams matrices (3 levels) and compared to those of planar transistors (hi) a sub-100nm channel width is demonstrated and (iv) specific 3D integration challenges like zipping between nano-beams are discussed","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"269 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133311148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346940
P. Palestri, R. Clerc, D. Esseni, L. Lucci, L. Selmi
This paper examines, by means of multi-subband-Monte-Carlo (MSMC) simulations, the prediction of the well known compact formula for back-scattering in nanoMOSFETs, analyzing the effect of carrier degeneracy and complex scattering mechanisms on the back-scattering. The paper also addresses the definition of an appropriate mean-free-path and its relationship to the low-field mobility
{"title":"Multi-Subband-Monte-Carlo investigation of the mean free path and of the kT layer in degenerated quasi ballistic nanoMOSFETs","authors":"P. Palestri, R. Clerc, D. Esseni, L. Lucci, L. Selmi","doi":"10.1109/IEDM.2006.346940","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346940","url":null,"abstract":"This paper examines, by means of multi-subband-Monte-Carlo (MSMC) simulations, the prediction of the well known compact formula for back-scattering in nanoMOSFETs, analyzing the effect of carrier degeneracy and complex scattering mechanisms on the back-scattering. The paper also addresses the definition of an appropriate mean-free-path and its relationship to the low-field mobility","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133315711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346811
T. Irisawa, T. Numata, T. Tezuka, N. Sugiyama, S. Takagi
Electron transport properties in biaxially strained UTB MOSFETs and uniaxially strained tri-gate MOSFETs are experimentally investigated. It is found that the strain is still effective even in UTB regime and the mobility enhancement of 1.4 against control thick (20 nm) SOI is preserved in devices with TSoi = 2.4 nm. We also demonstrate 2.0x mobility enhancement in tri-gate nMOSFETs with uniaxial <110> tensile strain that is favored not only on (100) but also on (110) sidewall
{"title":"Electron Transport Properties of Ultrathin-body and Tri-gate SOI nMOSFETs with Biaxial and Uniaxial Strain","authors":"T. Irisawa, T. Numata, T. Tezuka, N. Sugiyama, S. Takagi","doi":"10.1109/IEDM.2006.346811","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346811","url":null,"abstract":"Electron transport properties in biaxially strained UTB MOSFETs and uniaxially strained tri-gate MOSFETs are experimentally investigated. It is found that the strain is still effective even in UTB regime and the mobility enhancement of 1.4 against control thick (20 nm) SOI is preserved in devices with TSoi = 2.4 nm. We also demonstrate 2.0x mobility enhancement in tri-gate nMOSFETs with uniaxial <110> tensile strain that is favored not only on (100) but also on (110) sidewall","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132357352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346839
K. Cho, S. Suk, Y. Yeoh, Ming Li, K. Yeo, Dong-Won Kim, S. Hwang, Donggun Park, B. Ryu
the authors report transport experiments on gate-all-around (GAA) TSNWFETs fabricated by top-down CMOS processes. The nanowire with 45 nm gate length exhibits single electron tunneling, and the total capacitance extracted from the measured data is in good agreement with the self-capacitance of an ideal cylinder. The nanowire with 125 nm gate length shows conductance quantization suggesting ballistic transport. The temperature dependence of the conductance steps is consistent with the crossover from classical to ballistic
{"title":"Observation of Single Electron Tunneling and Ballistic Transport in Twin Silicon Nanowire MOSFETs (TSNWFETs) Fabricated by Top-Down CMOS Process","authors":"K. Cho, S. Suk, Y. Yeoh, Ming Li, K. Yeo, Dong-Won Kim, S. Hwang, Donggun Park, B. Ryu","doi":"10.1109/IEDM.2006.346839","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346839","url":null,"abstract":"the authors report transport experiments on gate-all-around (GAA) TSNWFETs fabricated by top-down CMOS processes. The nanowire with 45 nm gate length exhibits single electron tunneling, and the total capacitance extracted from the measured data is in good agreement with the self-capacitance of an ideal cylinder. The nanowire with 125 nm gate length shows conductance quantization suggesting ballistic transport. The temperature dependence of the conductance steps is consistent with the crossover from classical to ballistic","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132418026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346779
J.C. Lin, A. Oates, H. Tseng, Y. Liao, T. Chung, K. Huang, P. Tong, S.H. Yau, Y.F. Wang
The paper presents a comprehensive study of the impact of NBTI on SRAM Vccmin stability. The authors describe a novel simulation technique to predict the between - die statistical distribution of Vccmin drift due to NBTI. While the drift is a fundamental phenomenon, it was shown that by cell design and transistor process optimization, the drift can be reduced to tolerable levels
{"title":"Prediction and Control of NBTI -- Induced SRAM Vccmin Drift","authors":"J.C. Lin, A. Oates, H. Tseng, Y. Liao, T. Chung, K. Huang, P. Tong, S.H. Yau, Y.F. Wang","doi":"10.1109/IEDM.2006.346779","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346779","url":null,"abstract":"The paper presents a comprehensive study of the impact of NBTI on SRAM Vccmin stability. The authors describe a novel simulation technique to predict the between - die statistical distribution of Vccmin drift due to NBTI. While the drift is a fundamental phenomenon, it was shown that by cell design and transistor process optimization, the drift can be reduced to tolerable levels","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132711478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346950
K. Joo, Changrok Moon, Sungnam Lee, Xiofeng Wang, J. Yang, I. Yeo, Duckhyung Lee, O. Nam, U. Chung, J. Moon, B. Ryu
ZnO or AlxGa1-xN charge trap device showed large memory window (>7V) with fast P/E speed (plusmn17 V, 100 (_is) and excellent retention (10-year memory window of 6 V with small charge loss rate; ~l/5 of that of Si3N4). GaN and ZnO trap devices also showed the photo-sensitive programming due to their optoelectronics properties, providing the possibility of developing new type of high performance image sensor (QE ~ 80%)
{"title":"Novel Charge Trap Devices with NCBO Trap Layers for NVM or Image Sensor","authors":"K. Joo, Changrok Moon, Sungnam Lee, Xiofeng Wang, J. Yang, I. Yeo, Duckhyung Lee, O. Nam, U. Chung, J. Moon, B. Ryu","doi":"10.1109/IEDM.2006.346950","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346950","url":null,"abstract":"ZnO or AlxGa1-xN charge trap device showed large memory window (>7V) with fast P/E speed (plusmn17 V, 100 (_is) and excellent retention (10-year memory window of 6 V with small charge loss rate; ~l/5 of that of Si3N4). GaN and ZnO trap devices also showed the photo-sensitive programming due to their optoelectronics properties, providing the possibility of developing new type of high performance image sensor (QE ~ 80%)","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114531419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346766
C. Lee, A. Sazonov, J. Robertson, A. Nathan, M. Esmaeili-Rad, P. Servati, W. Milne
CMOS nanocrystalline silicon thin film transistors with high field effect mobility are reported. The transistors were directly deposited by radio-frequency plasma enhanced chemical vapor deposition at 150 degC. The transistors show maximum field effect mobility of 450 cm2/V-s for electrons and 100 cm2/V-s for holes at room temperature. We attribute the high mobilities to a reduction of the oxygen content, which acts as an accidental donor. Indeed, secondary ion mass spectrometry measurements show that the impurity concentration in the nanocrystalline Si layer is comparable to, or lower than, the defect density in the material, which is already low thanks to hydrogen passivation
{"title":"How to Achieve High Mobility Thin Film Transistors by Direct Deposition of Silicon Using 13.56 MHz RF PECVD?","authors":"C. Lee, A. Sazonov, J. Robertson, A. Nathan, M. Esmaeili-Rad, P. Servati, W. Milne","doi":"10.1109/IEDM.2006.346766","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346766","url":null,"abstract":"CMOS nanocrystalline silicon thin film transistors with high field effect mobility are reported. The transistors were directly deposited by radio-frequency plasma enhanced chemical vapor deposition at 150 degC. The transistors show maximum field effect mobility of 450 cm2/V-s for electrons and 100 cm2/V-s for holes at room temperature. We attribute the high mobilities to a reduction of the oxygen content, which acts as an accidental donor. Indeed, secondary ion mass spectrometry measurements show that the impurity concentration in the nanocrystalline Si layer is comparable to, or lower than, the defect density in the material, which is already low thanks to hydrogen passivation","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116299927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346810
T. Mizuno, T. Irisawa, N. Hirashita, Y. Moriyama, T. Numata, T. Tezuka, N. Sugiyama, S. Takagi
We have experimentally studied a new (HO)-surface anisotropic strained-SOI, using the combination of partially-strained global SGOI substrates and the uniaxial relaxation effects in the narrow SiGe layers. We have demonstrated much larger drain current Id enhancement of (110) anisotropic strained-SOIs against (HO)-SOIs than that of biaxial-strained ones. The optimum (110) strained-SOI CMOS consists of the biaxial strained n-MOS and the anisotropic strained p-MOS for the larger drain currents and the simple fabrication processes
{"title":"Novel Anisotropic Strain Engineering on (110)-Surface SOI CMOS Devices using Combination of Local/Global Strain Techniques","authors":"T. Mizuno, T. Irisawa, N. Hirashita, Y. Moriyama, T. Numata, T. Tezuka, N. Sugiyama, S. Takagi","doi":"10.1109/IEDM.2006.346810","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346810","url":null,"abstract":"We have experimentally studied a new (HO)-surface anisotropic strained-SOI, using the combination of partially-strained global SGOI substrates and the uniaxial relaxation effects in the narrow SiGe layers. We have demonstrated much larger drain current Id enhancement of (110) anisotropic strained-SOIs against (HO)-SOIs than that of biaxial-strained ones. The optimum (110) strained-SOI CMOS consists of the biaxial strained n-MOS and the anisotropic strained p-MOS for the larger drain currents and the simple fabrication processes","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114611813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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