Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346772
A. Neugroschel, G. Bersuker, R. Choi, C. Cochrane, P. Lenahan, D. Heh, C. Young, C. Kang, B. Lee, R. Jammy
Extraction of the intrinsic NBTI degradation rate in the high-k pMOSFETs was found to require correction of the measured threshold voltage shift (DeltaVTH) for the fast transient charging contribution caused by the charge trapping in pre-existing defects in high-k films. The proposed analysis methodology leads to a significantly lower estimated lifetime than that obtained by the generally used approach. It was determined that the interface state generation process contains a fast component most likely associated with the defects in the SiO2 interfacial layer induced by the overlaying high-k film. An intrinsic interface state generation rate obtained by subtracting the fast trapping component is found to be similar to that of the conventional SiO2 dielectric
{"title":"An Accurate Lifetime Analysis Methodology Incorporating Governing NBTI Mechanisms in High-k/SiO2 Gate Stacks","authors":"A. Neugroschel, G. Bersuker, R. Choi, C. Cochrane, P. Lenahan, D. Heh, C. Young, C. Kang, B. Lee, R. Jammy","doi":"10.1109/IEDM.2006.346772","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346772","url":null,"abstract":"Extraction of the intrinsic NBTI degradation rate in the high-k pMOSFETs was found to require correction of the measured threshold voltage shift (DeltaVTH) for the fast transient charging contribution caused by the charge trapping in pre-existing defects in high-k films. The proposed analysis methodology leads to a significantly lower estimated lifetime than that obtained by the generally used approach. It was determined that the interface state generation process contains a fast component most likely associated with the defects in the SiO2 interfacial layer induced by the overlaying high-k film. An intrinsic interface state generation rate obtained by subtracting the fast trapping component is found to be similar to that of the conventional SiO2 dielectric","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129135383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346831
R. Sugino, T. Ito
A novel technique in creating a cavity by using a membrane of Si-native oxide has been developed. The membrane of Si-native oxide was formed by high-selectivity Cl2 etching of Si which surface was treated by wet chemicals. Following film deposition onto the membrane which was supported by SiO2 mask can make a cavity in the substrate. The advantage of this technique is its ability to maintain the CD of cavity even after film deposition to seal the via-opening
{"title":"A Formation of Si Native Oxide Membrane Using High-Selectivity Etching and Applications for Nano-Pipe Array and Micro-Diaphragm on Si Substrate","authors":"R. Sugino, T. Ito","doi":"10.1109/IEDM.2006.346831","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346831","url":null,"abstract":"A novel technique in creating a cavity by using a membrane of Si-native oxide has been developed. The membrane of Si-native oxide was formed by high-selectivity Cl2 etching of Si which surface was treated by wet chemicals. Following film deposition onto the membrane which was supported by SiO2 mask can make a cavity in the substrate. The advantage of this technique is its ability to maintain the CD of cavity even after film deposition to seal the via-opening","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"39 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116725155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346854
G. He, M. Le, P. Partyka, R. Hess, G. Kim, R. Lee, R. Bryie, E. Sovero, M. Helix, R. Milano
A second-generation 0.5 mum InP double heterojunction bipolar transistor (DHBT) technology has been developed with outstanding manufacturability and scalability for advanced RF and mixed-signal integrated-circuit applications. It incorporates self-aligned refractory-metal-based ohmic contacts, ledge passivation for both the EB and BC junctions, and a mature interconnect process. Through process and epi-structure optimization, recent experimental high-speed devices yielded over 400 GHz fT and 450 GHz fmax, and separately, high-power devices yielded BVCEO over 20 V with knee voltage under 0.5 V
第二代0.5毫安InP双异质结双极晶体管(DHBT)技术已经开发出来，具有出色的可制造性和可扩展性，适用于先进的射频和混合信号集成电路应用。它采用自对准耐火金属基欧姆触点，EB和BC结的边缘钝化，以及成熟的互连工艺。通过工艺和外接结构优化，最近的实验高速器件的fT和fmax分别超过400 GHz和450 GHz，大功率器件的BVCEO分别超过20 V，膝电压低于0.5 V
{"title":"Recent Advances in InP DHBT Manufacturing Technology","authors":"G. He, M. Le, P. Partyka, R. Hess, G. Kim, R. Lee, R. Bryie, E. Sovero, M. Helix, R. Milano","doi":"10.1109/IEDM.2006.346854","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346854","url":null,"abstract":"A second-generation 0.5 mum InP double heterojunction bipolar transistor (DHBT) technology has been developed with outstanding manufacturability and scalability for advanced RF and mixed-signal integrated-circuit applications. It incorporates self-aligned refractory-metal-based ohmic contacts, ledge passivation for both the EB and BC junctions, and a mature interconnect process. Through process and epi-structure optimization, recent experimental high-speed devices yielded over 400 GHz fT and 450 GHz fmax, and separately, high-power devices yielded BVCEO over 20 V with knee voltage under 0.5 V","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115190475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346927
Sung Hwan Kim, C. Oh, Y. L. Choi, Sung I. Hong, N. Kim, H. Bae, Sung-Han Kim, H. Park, J. Yoon, I. Park, Dong-Won Kim, Donggun Park, B. Ryu
In this article, we proposed and successfully demonstrated 25 nm TiN metal gate nanorod transistors with laterally and vertically scaled actives without process burdens. They showed the excellent short channel effect immunity and high current drivability DIBLs are below 40 mV/V and subthreshold swings are nearly ideal values showing no temperature dependency. The driving currents of 1.4 mA/mum for nMOS and 1.0 mA/mum for pMOS are achieved at Ioff=100 nA/mum and VD =1.0 V. Thus, it is proven that laterally and vertically scaled nanorod transistors can be a promising solution for ultimate scaling
{"title":"Highly Manufacturable TiN Metal Gate Nanorod Transistors Realized on Silicon-On-ONO (SOONO) Substrate","authors":"Sung Hwan Kim, C. Oh, Y. L. Choi, Sung I. Hong, N. Kim, H. Bae, Sung-Han Kim, H. Park, J. Yoon, I. Park, Dong-Won Kim, Donggun Park, B. Ryu","doi":"10.1109/IEDM.2006.346927","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346927","url":null,"abstract":"In this article, we proposed and successfully demonstrated 25 nm TiN metal gate nanorod transistors with laterally and vertically scaled actives without process burdens. They showed the excellent short channel effect immunity and high current drivability DIBLs are below 40 mV/V and subthreshold swings are nearly ideal values showing no temperature dependency. The driving currents of 1.4 mA/mum for nMOS and 1.0 mA/mum for pMOS are achieved at Ioff=100 nA/mum and VD =1.0 V. Thus, it is proven that laterally and vertically scaled nanorod transistors can be a promising solution for ultimate scaling","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115212281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346813
R. Donaton, D. Chidambarrao, J. Johnson, P. Chang, Yaocheng Liu, W. Henson, J. Holt, Xi Li, Jinghong Li, A. Domenicucci, A. Madan, K. Rim, C. Wann
A novel device structure containing a SiGe stressor is used to impose tensile strain in nMOSFET channel. 400MPa of uniaxial tensile stress is induced in the Si channel through elastic relaxation/strain of the SiGe/Si bi-layer structure. This strain results in 40% mobility enhancement and 15% drive current improvement for sub-60nm devices compared to the control device with no strain
{"title":"Design and Fabrication of MOSFETs with a Reverse Embedded SiGe (Rev. e-SiGe) Structure","authors":"R. Donaton, D. Chidambarrao, J. Johnson, P. Chang, Yaocheng Liu, W. Henson, J. Holt, Xi Li, Jinghong Li, A. Domenicucci, A. Madan, K. Rim, C. Wann","doi":"10.1109/IEDM.2006.346813","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346813","url":null,"abstract":"A novel device structure containing a SiGe stressor is used to impose tensile strain in nMOSFET channel. 400MPa of uniaxial tensile stress is induced in the Si channel through elastic relaxation/strain of the SiGe/Si bi-layer structure. This strain results in 40% mobility enhancement and 15% drive current improvement for sub-60nm devices compared to the control device with no strain","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122565255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346945
R. Ohba, Y. Mitani, N. Sugiyama, S. Fujita
25nm gate length bulk-planar SONOS-type memory, which has Si nanocrystalline layer between double tunnel oxides, shows excellent memory characteristics due to Coulomb blockade and quantum confinement in Si nanocrystals. A direct evidence of great advantage in trade-off between charge retention and w/e speed is shown experimentally, and it is shown that further device scaling and improvement are possible by Si nanocrystal size scaling. Double tunnel junction SONOS-type memory is a strong candidate in less than 25nm region
{"title":"25 nm Planar Bulk SONOS-type Memory with Double Tunnel Junction","authors":"R. Ohba, Y. Mitani, N. Sugiyama, S. Fujita","doi":"10.1109/IEDM.2006.346945","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346945","url":null,"abstract":"25nm gate length bulk-planar SONOS-type memory, which has Si nanocrystalline layer between double tunnel oxides, shows excellent memory characteristics due to Coulomb blockade and quantum confinement in Si nanocrystals. A direct evidence of great advantage in trade-off between charge retention and w/e speed is shown experimentally, and it is shown that further device scaling and improvement are possible by Si nanocrystal size scaling. Double tunnel junction SONOS-type memory is a strong candidate in less than 25nm region","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121779446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346768
M. Esmaeili-Rad, A. Sazonov, A. Nathan
We report performance characteristics of nanocrystalline silicon thin-film transistors (TFTs) fabricated at 280 degC by plasma-enhanced chemical vapor deposition. The TFTs exhibit field-effect mobility of 0.8 cm2V-1s-1, threshold voltage of 4 V, on/off current ratio about 108 with an off-current of 10-13 A, and subthreshold slope of 0.8 V/dec. Bias stress measurements show that the TFT is 3-5 times more stable than the hydrogenated amorphous silicon (a-Si:H) counterpart, with a shift in threshold voltage that is less than 5 % at a gate voltage of 15 V
{"title":"High Stability, Low Leakage Nanocrystalline Silicon Bottom Gate Thin Film Transistors for AMOLED Displays","authors":"M. Esmaeili-Rad, A. Sazonov, A. Nathan","doi":"10.1109/IEDM.2006.346768","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346768","url":null,"abstract":"We report performance characteristics of nanocrystalline silicon thin-film transistors (TFTs) fabricated at 280 degC by plasma-enhanced chemical vapor deposition. The TFTs exhibit field-effect mobility of 0.8 cm2V-1s-1, threshold voltage of 4 V, on/off current ratio about 108 with an off-current of 10-13 A, and subthreshold slope of 0.8 V/dec. Bias stress measurements show that the TFT is 3-5 times more stable than the hydrogenated amorphous silicon (a-Si:H) counterpart, with a shift in threshold voltage that is less than 5 % at a gate voltage of 15 V","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124771828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346871
K. Saraswat, C. O. Chui, Donghyun Kim, T. Krishnamohan, A. Pethe
Channel materials with high mobility are needed for future nodes to meet the ITRS requirements of MOSFETs. In this work we assess the performance of Si, Ge, and III-V materials like GaAs, InAs and InSb which may perform better than even very highly strained-Si
{"title":"High Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs","authors":"K. Saraswat, C. O. Chui, Donghyun Kim, T. Krishnamohan, A. Pethe","doi":"10.1109/IEDM.2006.346871","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346871","url":null,"abstract":"Channel materials with high mobility are needed for future nodes to meet the ITRS requirements of MOSFETs. In this work we assess the performance of Si, Ge, and III-V materials like GaAs, InAs and InSb which may perform better than even very highly strained-Si","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124980346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346824
Y. Shih, E. Lai, J. Hsieh, T. Hsu, M.D. Wu, C. Lu, K. Ni, T.Y. Chou, L.W. Yang, K. Hsieh, M. Liaw, W.P. Lu, K.C. Chen, J. Ku, F. Ni, R. Liu, Chih-Yuan Lu
Multi-bit/cell nitride trapping NVM (Eitan et al., 2000 and 2005) using BTBT-HH erase suffers an "apparent" VT loss due to interface trap (NIT) generation. The array-nitride-sealing (ANS) ONO process (Shih et al., 2005) eliminates this VT loss by blocking hydrogen from the interface. In this work we further outfit the ANS-ONO process with a nitridized Si/SiO2 interface. By introducing a rapid thermal nitridation (RTN) after a low-energy buried diffusion (BD) implantation, the new process provides not only more immunity to HH-induced NIT generation but also a path to scale the BD. A 256Mb testing chip is successfully fabricated by the new approach with excellent natural good yield (>80%) and reliability. Our new process integration shows excellent reliability, scalability, and manufacturability for multi-bit/cell nitride trapping memory
{"title":"Highly Scalable and Reliable Multi-bit/cell Nitride Trapping Nonvolatile Memory Using Enhanced ANS-ONO Process with A Nitridized Interface","authors":"Y. Shih, E. Lai, J. Hsieh, T. Hsu, M.D. Wu, C. Lu, K. Ni, T.Y. Chou, L.W. Yang, K. Hsieh, M. Liaw, W.P. Lu, K.C. Chen, J. Ku, F. Ni, R. Liu, Chih-Yuan Lu","doi":"10.1109/IEDM.2006.346824","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346824","url":null,"abstract":"Multi-bit/cell nitride trapping NVM (Eitan et al., 2000 and 2005) using BTBT-HH erase suffers an \"apparent\" VT loss due to interface trap (NIT) generation. The array-nitride-sealing (ANS) ONO process (Shih et al., 2005) eliminates this VT loss by blocking hydrogen from the interface. In this work we further outfit the ANS-ONO process with a nitridized Si/SiO2 interface. By introducing a rapid thermal nitridation (RTN) after a low-energy buried diffusion (BD) implantation, the new process provides not only more immunity to HH-induced NIT generation but also a path to scale the BD. A 256Mb testing chip is successfully fabricated by the new approach with excellent natural good yield (>80%) and reliability. Our new process integration shows excellent reliability, scalability, and manufacturability for multi-bit/cell nitride trapping memory","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122112422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346853
W. Snodgrass, W. Hafez, N. Harff, M. Feng
Pseudomorphic InP HBTs (PHBTs) with a vertically scaled design implementing a 12.5 nm base and 55 nm collector exhibit record current gain cutoff frequency performance of fT=765 GHz when measured at 25°C. When cooled to -55°C, fT improves more than 10% to fT=845 GHz due to enhanced electron transport and reduced parasitic charging delays as determined by small signal equivalent circuit parameter extraction. Peak performance current density Jc=18.7 mA/μm2 and BVCEO =1.65 V
{"title":"Pseudomorphic InP/InGaAs Heterojunction Bipolar Transistors (PHBTs) Experimentally Demonstrating fT = 765 GHz at 25°C Increasing to fT = 845 GHz at -55°C","authors":"W. Snodgrass, W. Hafez, N. Harff, M. Feng","doi":"10.1109/IEDM.2006.346853","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346853","url":null,"abstract":"Pseudomorphic InP HBTs (PHBTs) with a vertically scaled design implementing a 12.5 nm base and 55 nm collector exhibit record current gain cutoff frequency performance of f<sub>T</sub>=765 GHz when measured at 25°C. When cooled to -55°C, f<sub>T</sub> improves more than 10% to f<sub>T</sub>=845 GHz due to enhanced electron transport and reduced parasitic charging delays as determined by small signal equivalent circuit parameter extraction. Peak performance current density J<sub>c</sub>=18.7 mA/μm<sup>2</sup> and BV<sub>CEO</sub> =1.65 V","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123168201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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