Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346739
M. Pourfath, H. Kosina, S. Selberherr
The performance of carbon nanotube field-effect transistors has been studied based on the non-equilibrium Green's function formalism. The effects of elastic and inelastic scattering and the impact of parameters, such as electron-phonon coupling strength and phonon energy, on the device performance are analyzed. The effect of scaling of the source-gate spacer, drain-gate spacer, and gate length is studied. The results for devices with different barrier heights at the metal-CNT interface are discussed
{"title":"A Comprehensive Study of Carbon Nanotube Based Transistors: The Effects of Geometrical, Interface Barrier, and Scattering Parameters","authors":"M. Pourfath, H. Kosina, S. Selberherr","doi":"10.1109/IEDM.2006.346739","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346739","url":null,"abstract":"The performance of carbon nanotube field-effect transistors has been studied based on the non-equilibrium Green's function formalism. The effects of elastic and inelastic scattering and the impact of parameters, such as electron-phonon coupling strength and phonon energy, on the device performance are analyzed. The effect of scaling of the source-gate spacer, drain-gate spacer, and gate length is studied. The results for devices with different barrier heights at the metal-CNT interface are discussed","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129986229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346802
M. Micovic, A. Kurdoghlian, P. Hashimoto, M. Hu, M. Antcliffe, P. Willadsen, W. Wong, R. Bowen, I. Milosavljevic, Adele E. Schmitz, M. Wetzel, David H. Chow
In this paper we report high frequency GaN power device and measured power performance of the first W-band (75 GHz-110 GHz) MMIC fabricated in GaN material system. The first W-band GaN MMIC with 150 mum of output gate periphery produces 316 mW of continuous wave output power (power density =2.1 W/m) at a frequency of 80.5 GHz and has associated power gain of 17.5 dB. By comparison the reported state of the art for other solid state technologies in W-band is 427 mW measured in a pulsed mode on an InP HEMT MMIC with 1600 mum of output periphery (power density = 0.26 W/mm). The reported result demonstrates tremendous superiority of GaN device technology for power applications at frequencies greater than 75 GHz
{"title":"GaN HFET for W-band Power Applications","authors":"M. Micovic, A. Kurdoghlian, P. Hashimoto, M. Hu, M. Antcliffe, P. Willadsen, W. Wong, R. Bowen, I. Milosavljevic, Adele E. Schmitz, M. Wetzel, David H. Chow","doi":"10.1109/IEDM.2006.346802","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346802","url":null,"abstract":"In this paper we report high frequency GaN power device and measured power performance of the first W-band (75 GHz-110 GHz) MMIC fabricated in GaN material system. The first W-band GaN MMIC with 150 mum of output gate periphery produces 316 mW of continuous wave output power (power density =2.1 W/m) at a frequency of 80.5 GHz and has associated power gain of 17.5 dB. By comparison the reported state of the art for other solid state technologies in W-band is 427 mW measured in a pulsed mode on an InP HEMT MMIC with 1600 mum of output periphery (power density = 0.26 W/mm). The reported result demonstrates tremendous superiority of GaN device technology for power applications at frequencies greater than 75 GHz","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130176546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346993
T. Ezaki, G. Suzuki, K. Konno, O. Matsushima, Y. Mizukane, D. Navarro, M. Miyake, N. Sadachika, H. Mattausch, M. Miura-Mattausch
The paper developed a photodiode (PD) model for circuit simulation considering, contrary to existing models, the transient carrier generation explicitly in the solution of the continuity equation. The developed model is compatible with conventional compact electrical device models and is demonstrated to enable accurate simulation of opto-electronic integrated circuits. The electric field distribution along the depth direction of the PD is found to cause a tail in the photo current, which has an adverse effect on optical response of PD and the performance of opto-electronic circuits. The developed opto-electronic circuit model is also applicable to predict how circuit performance is improved with respect to the improvement of photo diode characteristics
{"title":"Physics-Based Photodiode Model Enabling Consistent Opto-Electronic Circuit Simulation","authors":"T. Ezaki, G. Suzuki, K. Konno, O. Matsushima, Y. Mizukane, D. Navarro, M. Miyake, N. Sadachika, H. Mattausch, M. Miura-Mattausch","doi":"10.1109/IEDM.2006.346993","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346993","url":null,"abstract":"The paper developed a photodiode (PD) model for circuit simulation considering, contrary to existing models, the transient carrier generation explicitly in the solution of the continuity equation. The developed model is compatible with conventional compact electrical device models and is demonstrated to enable accurate simulation of opto-electronic integrated circuits. The electric field distribution along the depth direction of the PD is found to cause a tail in the photo current, which has an adverse effect on optical response of PD and the performance of opto-electronic circuits. The developed opto-electronic circuit model is also applicable to predict how circuit performance is improved with respect to the improvement of photo diode characteristics","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128649706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346846
T. Shino, Naoki Kusunoki, T. Higashi, Takashi Ohsawa, K. Fujita, K. Hatsuda, Nobuyuki Ikumi, Fumiyoshi Matsuoka, Yasuyuki Kajitani, Ryo Fukuda, Yoji Watanabe, Yoshihiro Minami, A. Sakamoto, Jun Nishimura, Hiroomi Nakajima, M. Morikado, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama
Technologies and improved performance of the floating body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the floating body cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant
{"title":"Floating Body RAM Technology and its Scalability to 32nm Node and Beyond","authors":"T. Shino, Naoki Kusunoki, T. Higashi, Takashi Ohsawa, K. Fujita, K. Hatsuda, Nobuyuki Ikumi, Fumiyoshi Matsuoka, Yasuyuki Kajitani, Ryo Fukuda, Yoji Watanabe, Yoshihiro Minami, A. Sakamoto, Jun Nishimura, Hiroomi Nakajima, M. Morikado, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama","doi":"10.1109/IEDM.2006.346846","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346846","url":null,"abstract":"Technologies and improved performance of the floating body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the floating body cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124571357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346838
K. Yeo, S. Suk, Ming Li, Y. Yeoh, K. Cho, Ki-Ha Hong, Seon-Pil Yun, Mong Sup Lee, N. Cho, Kwan-heum Lee, D. Hwang, Bokkyoung Park, Dong-Won Kim, Donggun Park, B. Ryu
GAA TSNWFET with 15 nm gate length and 4 nm radius nanowires is demonstrated and shows excellent short channel immunity. p-TSNWFET shows high driving current of 1.94 mA/mum while n-TSNWFET shows on-current of 1.44 mA/mum. Merits of TSNWFET and performance enhancement of p-TSNWFET are explored using 3D and quantum simulation
{"title":"Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires","authors":"K. Yeo, S. Suk, Ming Li, Y. Yeoh, K. Cho, Ki-Ha Hong, Seon-Pil Yun, Mong Sup Lee, N. Cho, Kwan-heum Lee, D. Hwang, Bokkyoung Park, Dong-Won Kim, Donggun Park, B. Ryu","doi":"10.1109/IEDM.2006.346838","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346838","url":null,"abstract":"GAA TSNWFET with 15 nm gate length and 4 nm radius nanowires is demonstrated and shows excellent short channel immunity. p-TSNWFET shows high driving current of 1.94 mA/mum while n-TSNWFET shows on-current of 1.44 mA/mum. Merits of TSNWFET and performance enhancement of p-TSNWFET are explored using 3D and quantum simulation","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129921300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346920
Y.S. Kim, Y. Shimamune, M. Fukuda, A. Katakami, A. Hatada, K. Kawamura, H. Ohta, T. Sakuma, Y. Hayami, H. Morioka, J. Ogura, T. Minami, N. Tamura, T. Mori, M. Kojima, K. Sukegawa, K. Hashimoto, M. Miyajima, S. Satoh, T. Sugii
The impact of defects on the short channel effects (SCE) and the drivability of a pMOSFET with a SiGe source/drain is described, and useful methods to reduce defect formation are suggested. The influence of defects on device performance is found to become more severe as recess depth increases and/or channel length decreases. By optimizing the epitaxial process, including an in-situ precleaning step, the initial defect density is reduced, and by introducing a cap layer on a SiGe layer, the thermal stability of the SiGe layer is improved. The optimized devices enhance mobility 42% by maximizing the strain effect and provide better SCE characteristics by suppressing boron diffusion
{"title":"Suppression of Defect Formation and Their Impact on Short Channel Effects and Drivability of pMOSFET with SiGe Source/Drain","authors":"Y.S. Kim, Y. Shimamune, M. Fukuda, A. Katakami, A. Hatada, K. Kawamura, H. Ohta, T. Sakuma, Y. Hayami, H. Morioka, J. Ogura, T. Minami, N. Tamura, T. Mori, M. Kojima, K. Sukegawa, K. Hashimoto, M. Miyajima, S. Satoh, T. Sugii","doi":"10.1109/IEDM.2006.346920","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346920","url":null,"abstract":"The impact of defects on the short channel effects (SCE) and the drivability of a pMOSFET with a SiGe source/drain is described, and useful methods to reduce defect formation are suggested. The influence of defects on device performance is found to become more severe as recess depth increases and/or channel length decreases. By optimizing the epitaxial process, including an in-situ precleaning step, the initial defect density is reduced, and by introducing a cap layer on a SiGe layer, the thermal stability of the SiGe layer is improved. The optimized devices enhance mobility 42% by maximizing the strain effect and provide better SCE characteristics by suppressing boron diffusion","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127277732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346988
M. Kobayashi, T. Hiramoto
We fabricated [100] and [110] directed nano wire MOSFET (NWFET), which works as NFET and PFET in the same channel. By comparing [100] and [110] direction, significantly small threshold voltage (Vth) fluctuation is experimentally observed in [110] PFET for the first time. This result supports the superiority of [110] NW PFET. Extremely narrow NWFET works as single-electron/single-hole transistors (SET/SHT). By comparing [100] and [110] direction, channel direction dependence of Coulomb blockade (CB) oscillations is experimentally clarified for the first time. We realize the highest performance in [100] SHT
{"title":"Experimental Study on Quantum Structure of Silicon Nano Wire and Its Impact on Nano Wire MOSFET and Single-Electron Transistor","authors":"M. Kobayashi, T. Hiramoto","doi":"10.1109/IEDM.2006.346988","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346988","url":null,"abstract":"We fabricated [100] and [110] directed nano wire MOSFET (NWFET), which works as NFET and PFET in the same channel. By comparing [100] and [110] direction, significantly small threshold voltage (Vth) fluctuation is experimentally observed in [110] PFET for the first time. This result supports the superiority of [110] NW PFET. Extremely narrow NWFET works as single-electron/single-hole transistors (SET/SHT). By comparing [100] and [110] direction, channel direction dependence of Coulomb blockade (CB) oscillations is experimentally clarified for the first time. We realize the highest performance in [100] SHT","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126988830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346959
Y. Tateshita, J. Wang, K. Nagano, T. Hirano, Y. Miyanami, T. Ikuta, T. Kataoka, Y. Kikuchi, S. Yamaguchi, T. Ando, K. Tai, R. Matsumoto, S. Fujita, C. Yamane, R. Yamamoto, S. Kanda, K. Kugimiya, T. Kimura, T. Ohchi, Y. Yamamoto, Y. Nagahama, Y. Hagimoto, H. Wakabayashi, Y. Tagawa, M. Tsukamoto, H. Iwamoto, M. Saito, S. Kadomura, N. Nagashima
CMOS technologies using metal/high-k damascene gate stacks with uniaxial strained silicon channels were developed. Gate electrodes of HfSix and TiN were applied to nFETs and pFETs, respectively. TiN/HfO2 damascene gate stacks and epitaxial SiGe source/drains were successfully integrated for the first time. As a result, drive currents of 1050 and 710 muA/mum at Vdd=l V, Ioff=100 nA/um and Tinv=1.6 nm were obtained for the nFETs and pFETs. The further integration of pFETs on (110) substrates contributed to a higher drive current of 830 muA/mum. These performances were realized under low gate leakage currents of 0.03 A/cm2 and below
{"title":"High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates","authors":"Y. Tateshita, J. Wang, K. Nagano, T. Hirano, Y. Miyanami, T. Ikuta, T. Kataoka, Y. Kikuchi, S. Yamaguchi, T. Ando, K. Tai, R. Matsumoto, S. Fujita, C. Yamane, R. Yamamoto, S. Kanda, K. Kugimiya, T. Kimura, T. Ohchi, Y. Yamamoto, Y. Nagahama, Y. Hagimoto, H. Wakabayashi, Y. Tagawa, M. Tsukamoto, H. Iwamoto, M. Saito, S. Kadomura, N. Nagashima","doi":"10.1109/IEDM.2006.346959","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346959","url":null,"abstract":"CMOS technologies using metal/high-k damascene gate stacks with uniaxial strained silicon channels were developed. Gate electrodes of HfSix and TiN were applied to nFETs and pFETs, respectively. TiN/HfO2 damascene gate stacks and epitaxial SiGe source/drains were successfully integrated for the first time. As a result, drive currents of 1050 and 710 muA/mum at Vdd=l V, Ioff=100 nA/um and Tinv=1.6 nm were obtained for the nFETs and pFETs. The further integration of pFETs on (110) substrates contributed to a higher drive current of 830 muA/mum. These performances were realized under low gate leakage currents of 0.03 A/cm2 and below","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115919492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346798
E. Piner, S. Singhal, P. Rajagopal, R. Therrien, J. Roberts, Tao Li, A. Hanson, J. W. Johnson, I. Kizilyalli, K. Linthicum
AlGaN/GaN HFET devices demonstrate remarkable performance. For commercial acceptance of this technology, long-term device stability must meet stringent industry standards. We review the current status of GaN reliability and contrast it with the requirement for commercial viability. Results analyzing degradation pertaining to buffer leakage and gate diode forward failure is presented
{"title":"Device Degradation Phenomena in GaN HFET Technology: Status, Mechanisms, and Opportunities","authors":"E. Piner, S. Singhal, P. Rajagopal, R. Therrien, J. Roberts, Tao Li, A. Hanson, J. W. Johnson, I. Kizilyalli, K. Linthicum","doi":"10.1109/IEDM.2006.346798","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346798","url":null,"abstract":"AlGaN/GaN HFET devices demonstrate remarkable performance. For commercial acceptance of this technology, long-term device stability must meet stringent industry standards. We review the current status of GaN reliability and contrast it with the requirement for commercial viability. Results analyzing degradation pertaining to buffer leakage and gate diode forward failure is presented","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121132352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346986
R. Leuschner, U. Klostermann, H. Park, F. Dahmani, R. Dittrich, C. Grigis, K. Hernan, S. Mege, C. Park, M. C. Clech, G. Y. Lee, S. Bournat, L. Altimime, G. Mueller
We report on a novel thermal select (TS) MRAM with multilevel programming capability. Exchange bias pinning of a magnetic free layer (FL) was used to achieve a thermally stable bit and to reduce writing currents. This report shows experimental data for a TS-based magnetic tunnel junction (MTJ) with a size of 50 times90 nm2, the smallest size reported so far. Multilevel capability with 2 bits per 1-transistor and 1-MTJ (1T1MTJ) is also demonstrated on a 70 times 140 nm2 MTJ. With the advanced 2-bit cell concept, a 70% increase in effective bit density can be achieved at 65 nm technology node
{"title":"Thermal Select MRAM with a 2-bit Cell Capability for beyond 65 nm Technology Node","authors":"R. Leuschner, U. Klostermann, H. Park, F. Dahmani, R. Dittrich, C. Grigis, K. Hernan, S. Mege, C. Park, M. C. Clech, G. Y. Lee, S. Bournat, L. Altimime, G. Mueller","doi":"10.1109/IEDM.2006.346986","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346986","url":null,"abstract":"We report on a novel thermal select (TS) MRAM with multilevel programming capability. Exchange bias pinning of a magnetic free layer (FL) was used to achieve a thermally stable bit and to reduce writing currents. This report shows experimental data for a TS-based magnetic tunnel junction (MTJ) with a size of 50 times90 nm2, the smallest size reported so far. Multilevel capability with 2 bits per 1-transistor and 1-MTJ (1T1MTJ) is also demonstrated on a 70 times 140 nm2 MTJ. With the advanced 2-bit cell concept, a 70% increase in effective bit density can be achieved at 65 nm technology node","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126672375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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