Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346967
G. Van den bosch, S. Demuynck, Z. Tokei, G. Beyer, M. Van Hove, G. Groeseneken
With copper contact technology, CMOS front-end yield and reliability are governed by the quality of the contact barrier stack. Poor barrier quality gives rise to yield loss in junctions and gate dielectrics, and reduced time-to-breakdown with characteristic breakdown signature. Failure analysis reveals the presence of copper silicide as the underlying cause, its impact depending on the exact location of the affected region. With optimized barrier there is no indication for copper related front-end yield and reliability problems
{"title":"Impact of copper contacts on CMOS front-end yield and reliability","authors":"G. Van den bosch, S. Demuynck, Z. Tokei, G. Beyer, M. Van Hove, G. Groeseneken","doi":"10.1109/IEDM.2006.346967","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346967","url":null,"abstract":"With copper contact technology, CMOS front-end yield and reliability are governed by the quality of the contact barrier stack. Poor barrier quality gives rise to yield loss in junctions and gate dielectrics, and reduced time-to-breakdown with characteristic breakdown signature. Failure analysis reveals the presence of copper silicide as the underlying cause, its impact depending on the exact location of the affected region. With optimized barrier there is no indication for copper related front-end yield and reliability problems","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116034536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346966
Young-Joon Park, Ki-Don Lee, W. Hunter
The short length effect on the electromigration (EM) lifetime is a valuable resource to increase current limits in advanced circuits. We model the effect with variable (current density j sensitive) current exponent n for short leads and calculate how much lifetime margin should be observed for a certain EM rule relaxation. The shorter leads have larger (variable) n so that the EM lifetime decreases faster as the current density increases. We utilize an empirical relationship for the dependence of n on j, which includes a parameter nBS for short leads. We find that to achieve a 2times EM rule relaxation, we must confirm > 25times EM lifetime for nBS = 3 and > 125times for nBS = 5. We illustrate an empirical approach for determining nBS
{"title":"A Variable Current Exponent Model for Electromigration Lifetime Relaxation in Short Cu Interconnects","authors":"Young-Joon Park, Ki-Don Lee, W. Hunter","doi":"10.1109/IEDM.2006.346966","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346966","url":null,"abstract":"The short length effect on the electromigration (EM) lifetime is a valuable resource to increase current limits in advanced circuits. We model the effect with variable (current density j sensitive) current exponent n for short leads and calculate how much lifetime margin should be observed for a certain EM rule relaxation. The shorter leads have larger (variable) n so that the EM lifetime decreases faster as the current density increases. We utilize an empirical relationship for the dependence of n on j, which includes a parameter nBS for short leads. We find that to achieve a 2times EM rule relaxation, we must confirm > 25times EM lifetime for nBS = 3 and > 125times for nBS = 5. We illustrate an empirical approach for determining nBS","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121539270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346993
T. Ezaki, G. Suzuki, K. Konno, O. Matsushima, Y. Mizukane, D. Navarro, M. Miyake, N. Sadachika, H. Mattausch, M. Miura-Mattausch
The paper developed a photodiode (PD) model for circuit simulation considering, contrary to existing models, the transient carrier generation explicitly in the solution of the continuity equation. The developed model is compatible with conventional compact electrical device models and is demonstrated to enable accurate simulation of opto-electronic integrated circuits. The electric field distribution along the depth direction of the PD is found to cause a tail in the photo current, which has an adverse effect on optical response of PD and the performance of opto-electronic circuits. The developed opto-electronic circuit model is also applicable to predict how circuit performance is improved with respect to the improvement of photo diode characteristics
{"title":"Physics-Based Photodiode Model Enabling Consistent Opto-Electronic Circuit Simulation","authors":"T. Ezaki, G. Suzuki, K. Konno, O. Matsushima, Y. Mizukane, D. Navarro, M. Miyake, N. Sadachika, H. Mattausch, M. Miura-Mattausch","doi":"10.1109/IEDM.2006.346993","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346993","url":null,"abstract":"The paper developed a photodiode (PD) model for circuit simulation considering, contrary to existing models, the transient carrier generation explicitly in the solution of the continuity equation. The developed model is compatible with conventional compact electrical device models and is demonstrated to enable accurate simulation of opto-electronic integrated circuits. The electric field distribution along the depth direction of the PD is found to cause a tail in the photo current, which has an adverse effect on optical response of PD and the performance of opto-electronic circuits. The developed opto-electronic circuit model is also applicable to predict how circuit performance is improved with respect to the improvement of photo diode characteristics","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128649706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346838
K. Yeo, S. Suk, Ming Li, Y. Yeoh, K. Cho, Ki-Ha Hong, Seon-Pil Yun, Mong Sup Lee, N. Cho, Kwan-heum Lee, D. Hwang, Bokkyoung Park, Dong-Won Kim, Donggun Park, B. Ryu
GAA TSNWFET with 15 nm gate length and 4 nm radius nanowires is demonstrated and shows excellent short channel immunity. p-TSNWFET shows high driving current of 1.94 mA/mum while n-TSNWFET shows on-current of 1.44 mA/mum. Merits of TSNWFET and performance enhancement of p-TSNWFET are explored using 3D and quantum simulation
{"title":"Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires","authors":"K. Yeo, S. Suk, Ming Li, Y. Yeoh, K. Cho, Ki-Ha Hong, Seon-Pil Yun, Mong Sup Lee, N. Cho, Kwan-heum Lee, D. Hwang, Bokkyoung Park, Dong-Won Kim, Donggun Park, B. Ryu","doi":"10.1109/IEDM.2006.346838","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346838","url":null,"abstract":"GAA TSNWFET with 15 nm gate length and 4 nm radius nanowires is demonstrated and shows excellent short channel immunity. p-TSNWFET shows high driving current of 1.94 mA/mum while n-TSNWFET shows on-current of 1.44 mA/mum. Merits of TSNWFET and performance enhancement of p-TSNWFET are explored using 3D and quantum simulation","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129921300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346739
M. Pourfath, H. Kosina, S. Selberherr
The performance of carbon nanotube field-effect transistors has been studied based on the non-equilibrium Green's function formalism. The effects of elastic and inelastic scattering and the impact of parameters, such as electron-phonon coupling strength and phonon energy, on the device performance are analyzed. The effect of scaling of the source-gate spacer, drain-gate spacer, and gate length is studied. The results for devices with different barrier heights at the metal-CNT interface are discussed
{"title":"A Comprehensive Study of Carbon Nanotube Based Transistors: The Effects of Geometrical, Interface Barrier, and Scattering Parameters","authors":"M. Pourfath, H. Kosina, S. Selberherr","doi":"10.1109/IEDM.2006.346739","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346739","url":null,"abstract":"The performance of carbon nanotube field-effect transistors has been studied based on the non-equilibrium Green's function formalism. The effects of elastic and inelastic scattering and the impact of parameters, such as electron-phonon coupling strength and phonon energy, on the device performance are analyzed. The effect of scaling of the source-gate spacer, drain-gate spacer, and gate length is studied. The results for devices with different barrier heights at the metal-CNT interface are discussed","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129986229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346802
M. Micovic, A. Kurdoghlian, P. Hashimoto, M. Hu, M. Antcliffe, P. Willadsen, W. Wong, R. Bowen, I. Milosavljevic, Adele E. Schmitz, M. Wetzel, David H. Chow
In this paper we report high frequency GaN power device and measured power performance of the first W-band (75 GHz-110 GHz) MMIC fabricated in GaN material system. The first W-band GaN MMIC with 150 mum of output gate periphery produces 316 mW of continuous wave output power (power density =2.1 W/m) at a frequency of 80.5 GHz and has associated power gain of 17.5 dB. By comparison the reported state of the art for other solid state technologies in W-band is 427 mW measured in a pulsed mode on an InP HEMT MMIC with 1600 mum of output periphery (power density = 0.26 W/mm). The reported result demonstrates tremendous superiority of GaN device technology for power applications at frequencies greater than 75 GHz
{"title":"GaN HFET for W-band Power Applications","authors":"M. Micovic, A. Kurdoghlian, P. Hashimoto, M. Hu, M. Antcliffe, P. Willadsen, W. Wong, R. Bowen, I. Milosavljevic, Adele E. Schmitz, M. Wetzel, David H. Chow","doi":"10.1109/IEDM.2006.346802","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346802","url":null,"abstract":"In this paper we report high frequency GaN power device and measured power performance of the first W-band (75 GHz-110 GHz) MMIC fabricated in GaN material system. The first W-band GaN MMIC with 150 mum of output gate periphery produces 316 mW of continuous wave output power (power density =2.1 W/m) at a frequency of 80.5 GHz and has associated power gain of 17.5 dB. By comparison the reported state of the art for other solid state technologies in W-band is 427 mW measured in a pulsed mode on an InP HEMT MMIC with 1600 mum of output periphery (power density = 0.26 W/mm). The reported result demonstrates tremendous superiority of GaN device technology for power applications at frequencies greater than 75 GHz","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130176546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346859
C. Wu, B. Hung, A. Chin, S. Wang, W. Chen, X.P. Wang, M. Li, C. Zhu, Y. Jin, H. Tao, S. Chen, M. Liang
The authors report novel 1000degC-stable [Ir3Si-TaN]/HfLaON CMOS for the first time, where the self-aligned and gate-first process are full compatible to current VLSI. Good Phim-eff of 5.08 and 4.24 eV, low Vt of -0.10 and 0.18 V, high mobility of 84 and 217 cm2/Vs at 1.6 nm EOT, and small 85degC BTI <20 mV (10 MV/cm for 1 hr) are measured
{"title":"High Temperature Stable [Ir3Si-TaN]/HfLaON CMOS with Large Work-Function Difference","authors":"C. Wu, B. Hung, A. Chin, S. Wang, W. Chen, X.P. Wang, M. Li, C. Zhu, Y. Jin, H. Tao, S. Chen, M. Liang","doi":"10.1109/IEDM.2006.346859","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346859","url":null,"abstract":"The authors report novel 1000degC-stable [Ir<sub>3</sub>Si-TaN]/HfLaON CMOS for the first time, where the self-aligned and gate-first process are full compatible to current VLSI. Good Phi<sub>m-eff</sub> of 5.08 and 4.24 eV, low V<sub>t</sub> of -0.10 and 0.18 V, high mobility of 84 and 217 cm<sup>2</sup>/Vs at 1.6 nm EOT, and small 85degC BTI <20 mV (10 MV/cm for 1 hr) are measured","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"106 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125987097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346841
L. Bera, H. Nguyen, N. Singh, T. Liow, D.X. Huang, K. Hoe, C. Tung, W. Fang, S. Rustagi, Y. Jiang, G. Lo, N. Balasubramanian, D. Kwong
A novel method for realizing arrays of vertically stacked (e.g., times3 wires stacked) laterally spread out nanowires is presented for the first time using a fully Si-CMOS compatible process. The gate-all-around (GAA) MOSFET devices using these nanowire arrays show excellent performance in terms of near ideal sub-threshold slope (<70 mV/dec), high Ion/Ioff ratio (~107), and low leakage current. Vertical stacking economizes on silicon estate and improves the on-state IDSAT at the same time. Both n- and p-FET devices are demonstrated
{"title":"Three Dimensionally Stacked SiGe Nanowire Array and Gate-All-Around p-MOSFETs","authors":"L. Bera, H. Nguyen, N. Singh, T. Liow, D.X. Huang, K. Hoe, C. Tung, W. Fang, S. Rustagi, Y. Jiang, G. Lo, N. Balasubramanian, D. Kwong","doi":"10.1109/IEDM.2006.346841","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346841","url":null,"abstract":"A novel method for realizing arrays of vertically stacked (e.g., times3 wires stacked) laterally spread out nanowires is presented for the first time using a fully Si-CMOS compatible process. The gate-all-around (GAA) MOSFET devices using these nanowire arrays show excellent performance in terms of near ideal sub-threshold slope (<70 mV/dec), high Ion/Ioff ratio (~107), and low leakage current. Vertical stacking economizes on silicon estate and improves the on-state IDSAT at the same time. Both n- and p-FET devices are demonstrated","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126316388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346818
B. Govoreanu, D. Wellekens, L. Haspeslagh, J. de Vos, J. van Houdt
We describe the low-field leakage through high-k interpoly dielectric stacks in floating gate nonvolatile memories with an inelastic trap-assisted tunneling model, which accounts for arbitrary trap distributions in both energy and space. A systematic investigation of the impact of trap parameters, stack composition, bias and temperature on the leakage is presented, focusing on Al2O3-based stacks. Room- and high-temperature retention data indicate charge loss/gain due to bulk traps in Al2 O3, with an average depth of 2.2 eV and a spread of plusmn0.3 eV. Scalability of Al2O3 IPD stacks below 6.5 nm EOT may be achieved by reducing the trap density by at least 1 order of magnitude
{"title":"Investigation of the low-field leakage through high-k interpoly dielectric stacks and its impact on nonvolatile memory data retention","authors":"B. Govoreanu, D. Wellekens, L. Haspeslagh, J. de Vos, J. van Houdt","doi":"10.1109/IEDM.2006.346818","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346818","url":null,"abstract":"We describe the low-field leakage through high-k interpoly dielectric stacks in floating gate nonvolatile memories with an inelastic trap-assisted tunneling model, which accounts for arbitrary trap distributions in both energy and space. A systematic investigation of the impact of trap parameters, stack composition, bias and temperature on the leakage is presented, focusing on Al2O3-based stacks. Room- and high-temperature retention data indicate charge loss/gain due to bulk traps in Al2 O3, with an average depth of 2.2 eV and a spread of plusmn0.3 eV. Scalability of Al2O3 IPD stacks below 6.5 nm EOT may be achieved by reducing the trap density by at least 1 order of magnitude","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127457569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346912
M. Kittler, M. Reiche, X. Yu, T. Arguirov, O. Vyvenko, W. Seifert, T. Mchedlidze, G. Jia, T. Wilhelm
A novel Si MOS-LED is demonstrated, which is fully compatible with Si technology. It is based on a dislocation network fabricated by wafer direct bonding. Light emission at 1.5 μm was observed when the network was near the Si/SiO2 interface close to/inside the accumulation layer induced by the gate voltage
{"title":"1.5 μm Emission from a Silicon MOS-LED Based on a Dislocation Network","authors":"M. Kittler, M. Reiche, X. Yu, T. Arguirov, O. Vyvenko, W. Seifert, T. Mchedlidze, G. Jia, T. Wilhelm","doi":"10.1109/IEDM.2006.346912","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346912","url":null,"abstract":"A novel Si MOS-LED is demonstrated, which is fully compatible with Si technology. It is based on a dislocation network fabricated by wafer direct bonding. Light emission at 1.5 μm was observed when the network was near the Si/SiO2 interface close to/inside the accumulation layer induced by the gate voltage","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114202613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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