Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346855
Weifeng Zhao, Niu Jin, Guang Chen, Liang Wang, I. Adesida
This paper reports a newly developed fabrication process for monolithic integration of thermally stable InAlAs/InGaAs/InP E/D-HEMTs based on Ir-gate and Ag-ohmic contact technologies. The Ir-gate and Ag-ohmic contacts were annealed simultaneously after passivation using a SiNx layer. Both integrated E/D-HEMTs with gate-length of 0.2 mum demonstrated excellent DC and RF characteristics
本文报道了一种基于Ir-gate和ag -欧姆接触技术的热稳定InAlAs/InGaAs/InP E/ d - hemt单片集成的新工艺。在钝化后，采用SiNx层对Ir-gate和ag -欧姆触点同时退火。两种栅极长度均为0.2 μ m的集成E/ d - hemt均具有优异的直流和射频特性
{"title":"Monolithic integration of thermally stable enhancement-mode and depletion-mode InAlAs/InGaAs/InP HEMTs utilizing Ir-gate and Ag-ohmic contact technologies","authors":"Weifeng Zhao, Niu Jin, Guang Chen, Liang Wang, I. Adesida","doi":"10.1109/IEDM.2006.346855","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346855","url":null,"abstract":"This paper reports a newly developed fabrication process for monolithic integration of thermally stable InAlAs/InGaAs/InP E/D-HEMTs based on Ir-gate and Ag-ohmic contact technologies. The Ir-gate and Ag-ohmic contacts were annealed simultaneously after passivation using a SiNx layer. Both integrated E/D-HEMTs with gate-length of 0.2 mum demonstrated excellent DC and RF characteristics","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133632484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346915
R.T.-P. Lee, T. Liow, K. Tan, A. Lim, Hoong-Shing Wong, P. Lim, D. Lai, G. Lo, C. Tung, G. Samudra, D. Chi, Y. Yeo
In this work, we examined the Schottky-barrier height modulation of NiSi by the incorporation of aluminum (Al), titanium (Ti), erbium (Er), and ytterbium (Yb) in NiSi to form different NiSi-alloys. Among the NiSi-alloy candidates investigated, it was found that the NiAl-alloy silicide provides the most effective Schottky-barrier height lowering (~250 meV) on n-Si(001) substrates. Integration of NiAl-alloy silicides as the source and drain (S/D) silicide material for multiple-gate transistors (MuGFETs) was explored, and shown to deliver a drive current IDsat enhancement of 34% compared to MuGFETs employing NiSi S/D. We further showed that the novel NiAl-alloy silicidation process is compatible with lattice-mismatched silicon-carbon (SiC) S/D stressors. NiAl-alloy silicide is therefore a promising S/D silicide material for reducing the high parasitic series resistance in narrow fin MuGFETs for enhanced device performance
{"title":"Novel Nickel-Alloy Silicides for Source/Drain Contact Resistance Reduction in N-Channel Multiple-Gate Transistors with Sub-35nm Gate Length","authors":"R.T.-P. Lee, T. Liow, K. Tan, A. Lim, Hoong-Shing Wong, P. Lim, D. Lai, G. Lo, C. Tung, G. Samudra, D. Chi, Y. Yeo","doi":"10.1109/IEDM.2006.346915","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346915","url":null,"abstract":"In this work, we examined the Schottky-barrier height modulation of NiSi by the incorporation of aluminum (Al), titanium (Ti), erbium (Er), and ytterbium (Yb) in NiSi to form different NiSi-alloys. Among the NiSi-alloy candidates investigated, it was found that the NiAl-alloy silicide provides the most effective Schottky-barrier height lowering (~250 meV) on n-Si(001) substrates. Integration of NiAl-alloy silicides as the source and drain (S/D) silicide material for multiple-gate transistors (MuGFETs) was explored, and shown to deliver a drive current IDsat enhancement of 34% compared to MuGFETs employing NiSi S/D. We further showed that the novel NiAl-alloy silicidation process is compatible with lattice-mismatched silicon-carbon (SiC) S/D stressors. NiAl-alloy silicide is therefore a promising S/D silicide material for reducing the high parasitic series resistance in narrow fin MuGFETs for enhanced device performance","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131818574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346879
S. Narasimha, K. Onishi, H. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C.-H.J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. van Meer, A. Vayshenker, D. Wehella-gamage, J. Werking, R. Wong, J. Yu, S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Warm, T. Ivers, P. Agnello
We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific performance elements includes enhanced dual-stress liner (DSL), advanced eSiGe, stress memorization (SMT), and advanced anneal (AA). The resulting PFET/NFET Idsat values, at Vdd of 1.0V and 45nm GR gate pitch, are 840muA/mum and 1240muA/mum respectively. The global wiring delay achieved with k=2.4 reflects a 20% reduction compared to k=3.0
{"title":"High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography","authors":"S. Narasimha, K. Onishi, H. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C.-H.J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. van Meer, A. Vayshenker, D. Wehella-gamage, J. Werking, R. Wong, J. Yu, S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Warm, T. Ivers, P. Agnello","doi":"10.1109/IEDM.2006.346879","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346879","url":null,"abstract":"We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific performance elements includes enhanced dual-stress liner (DSL), advanced eSiGe, stress memorization (SMT), and advanced anneal (AA). The resulting PFET/NFET Idsat values, at Vdd of 1.0V and 45nm GR gate pitch, are 840muA/mum and 1240muA/mum respectively. The global wiring delay achieved with k=2.4 reflects a 20% reduction compared to k=3.0","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132197984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.347009
T. Hayashi, Y. Nishida, S. Sakashita, M. Mizutani, S. Yamanari, M. Higashi, T. Kawahara, M. Inoue, J. Yugami, J. Tsuchimoto, K. Shiga, N. Murata, H. Sayama, T. Yamashita, H. Oda, T. Kuroi, T. Eimori, Y. Inoue
High performance LSTP CMISFETs with poly-Si/TiN hybrid gate and high-k dielectric have been studied. Gate depletion is successfully suppressed by in-situ phosphorus doped poly-Si gate for NMIS and by TiN metal gate for PMIS. Vth control for pMIS is accomplished by fluorine implantation into substrate. Optimization of HfSiON formation and TiN removal process is the key to achieve high-reliability. It is demonstrated that this cost-worthy process provides performance which is competitive to reported dual metal CMOS
{"title":"Cost Worthy and High Performance LSTP CMIS; Poly-Si/HfSiON nMIS and Poly-Si/TiN/HfSiON pMIS","authors":"T. Hayashi, Y. Nishida, S. Sakashita, M. Mizutani, S. Yamanari, M. Higashi, T. Kawahara, M. Inoue, J. Yugami, J. Tsuchimoto, K. Shiga, N. Murata, H. Sayama, T. Yamashita, H. Oda, T. Kuroi, T. Eimori, Y. Inoue","doi":"10.1109/IEDM.2006.347009","DOIUrl":"https://doi.org/10.1109/IEDM.2006.347009","url":null,"abstract":"High performance LSTP CMISFETs with poly-Si/TiN hybrid gate and high-k dielectric have been studied. Gate depletion is successfully suppressed by in-situ phosphorus doped poly-Si gate for NMIS and by TiN metal gate for PMIS. Vth control for pMIS is accomplished by fluorine implantation into substrate. Optimization of HfSiON formation and TiN removal process is the key to achieve high-reliability. It is demonstrated that this cost-worthy process provides performance which is competitive to reported dual metal CMOS","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134407083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346912
M. Kittler, M. Reiche, X. Yu, T. Arguirov, O. Vyvenko, W. Seifert, T. Mchedlidze, G. Jia, T. Wilhelm
A novel Si MOS-LED is demonstrated, which is fully compatible with Si technology. It is based on a dislocation network fabricated by wafer direct bonding. Light emission at 1.5 μm was observed when the network was near the Si/SiO2 interface close to/inside the accumulation layer induced by the gate voltage
{"title":"1.5 μm Emission from a Silicon MOS-LED Based on a Dislocation Network","authors":"M. Kittler, M. Reiche, X. Yu, T. Arguirov, O. Vyvenko, W. Seifert, T. Mchedlidze, G. Jia, T. Wilhelm","doi":"10.1109/IEDM.2006.346912","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346912","url":null,"abstract":"A novel Si MOS-LED is demonstrated, which is fully compatible with Si technology. It is based on a dislocation network fabricated by wafer direct bonding. Light emission at 1.5 μm was observed when the network was near the Si/SiO2 interface close to/inside the accumulation layer induced by the gate voltage","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114202613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346967
G. Van den bosch, S. Demuynck, Z. Tokei, G. Beyer, M. Van Hove, G. Groeseneken
With copper contact technology, CMOS front-end yield and reliability are governed by the quality of the contact barrier stack. Poor barrier quality gives rise to yield loss in junctions and gate dielectrics, and reduced time-to-breakdown with characteristic breakdown signature. Failure analysis reveals the presence of copper silicide as the underlying cause, its impact depending on the exact location of the affected region. With optimized barrier there is no indication for copper related front-end yield and reliability problems
{"title":"Impact of copper contacts on CMOS front-end yield and reliability","authors":"G. Van den bosch, S. Demuynck, Z. Tokei, G. Beyer, M. Van Hove, G. Groeseneken","doi":"10.1109/IEDM.2006.346967","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346967","url":null,"abstract":"With copper contact technology, CMOS front-end yield and reliability are governed by the quality of the contact barrier stack. Poor barrier quality gives rise to yield loss in junctions and gate dielectrics, and reduced time-to-breakdown with characteristic breakdown signature. Failure analysis reveals the presence of copper silicide as the underlying cause, its impact depending on the exact location of the affected region. With optimized barrier there is no indication for copper related front-end yield and reliability problems","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116034536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346874
A. Toriumi, K. Kita, H. Irie
Parasitic effects and Matthiessen's rule have been reinvestigated in the inversion layer mobility analysis. It is shown that an advanced split C-V technique newly developed is very useful for characterizing the intrinsic inversion layer mobility in short channel MOSFETs, even with very large parasitic effects. Furthermore, the validity of Matthiessen's rule is experimentally and theoretically investigated through Hall factor analysis
{"title":"Novel Approach to MOS Inversion Layer Mobility Characterization with Advanced Split C-V and Hall Factor Analyses","authors":"A. Toriumi, K. Kita, H. Irie","doi":"10.1109/IEDM.2006.346874","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346874","url":null,"abstract":"Parasitic effects and Matthiessen's rule have been reinvestigated in the inversion layer mobility analysis. It is shown that an advanced split C-V technique newly developed is very useful for characterizing the intrinsic inversion layer mobility in short channel MOSFETs, even with very large parasitic effects. Furthermore, the validity of Matthiessen's rule is experimentally and theoretically investigated through Hall factor analysis","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124703975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346966
Young-Joon Park, Ki-Don Lee, W. Hunter
The short length effect on the electromigration (EM) lifetime is a valuable resource to increase current limits in advanced circuits. We model the effect with variable (current density j sensitive) current exponent n for short leads and calculate how much lifetime margin should be observed for a certain EM rule relaxation. The shorter leads have larger (variable) n so that the EM lifetime decreases faster as the current density increases. We utilize an empirical relationship for the dependence of n on j, which includes a parameter nBS for short leads. We find that to achieve a 2times EM rule relaxation, we must confirm > 25times EM lifetime for nBS = 3 and > 125times for nBS = 5. We illustrate an empirical approach for determining nBS
{"title":"A Variable Current Exponent Model for Electromigration Lifetime Relaxation in Short Cu Interconnects","authors":"Young-Joon Park, Ki-Don Lee, W. Hunter","doi":"10.1109/IEDM.2006.346966","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346966","url":null,"abstract":"The short length effect on the electromigration (EM) lifetime is a valuable resource to increase current limits in advanced circuits. We model the effect with variable (current density j sensitive) current exponent n for short leads and calculate how much lifetime margin should be observed for a certain EM rule relaxation. The shorter leads have larger (variable) n so that the EM lifetime decreases faster as the current density increases. We utilize an empirical relationship for the dependence of n on j, which includes a parameter nBS for short leads. We find that to achieve a 2times EM rule relaxation, we must confirm > 25times EM lifetime for nBS = 3 and > 125times for nBS = 5. We illustrate an empirical approach for determining nBS","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121539270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346783
K. Takeda, R. Yamada, T. Imai, T. Fujiwara, T. Hashimoto, T. Ando
Time-dependent capacitance-density (CD) increase and linearity degradations of HfAlO-MIM capacitors by constant voltage stress were demonstrated for the first time. It was found that extrapolated CD increase after 10 years strongly depends on Al concentration in HfAlO dielectric. Accordingly, Al concentration of more than 14 at.% is required to keep CD increase below 1%. It was also found that the CD increase and linearity degradations (temperature and frequency) originate from the dielectric-loss increase and that the relationships between these parameters quantitatively agree with Gevers' model
{"title":"DC-stress-induced Degradation of Analog Characteristics in HfxAl(1-x)O MIM Capacitors","authors":"K. Takeda, R. Yamada, T. Imai, T. Fujiwara, T. Hashimoto, T. Ando","doi":"10.1109/IEDM.2006.346783","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346783","url":null,"abstract":"Time-dependent capacitance-density (CD) increase and linearity degradations of HfAlO-MIM capacitors by constant voltage stress were demonstrated for the first time. It was found that extrapolated CD increase after 10 years strongly depends on Al concentration in HfAlO dielectric. Accordingly, Al concentration of more than 14 at.% is required to keep CD increase below 1%. It was also found that the CD increase and linearity degradations (temperature and frequency) originate from the dielectric-loss increase and that the relationships between these parameters quantitatively agree with Gevers' model","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126196272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346841
L. Bera, H. Nguyen, N. Singh, T. Liow, D.X. Huang, K. Hoe, C. Tung, W. Fang, S. Rustagi, Y. Jiang, G. Lo, N. Balasubramanian, D. Kwong
A novel method for realizing arrays of vertically stacked (e.g., times3 wires stacked) laterally spread out nanowires is presented for the first time using a fully Si-CMOS compatible process. The gate-all-around (GAA) MOSFET devices using these nanowire arrays show excellent performance in terms of near ideal sub-threshold slope (<70 mV/dec), high Ion/Ioff ratio (~107), and low leakage current. Vertical stacking economizes on silicon estate and improves the on-state IDSAT at the same time. Both n- and p-FET devices are demonstrated
{"title":"Three Dimensionally Stacked SiGe Nanowire Array and Gate-All-Around p-MOSFETs","authors":"L. Bera, H. Nguyen, N. Singh, T. Liow, D.X. Huang, K. Hoe, C. Tung, W. Fang, S. Rustagi, Y. Jiang, G. Lo, N. Balasubramanian, D. Kwong","doi":"10.1109/IEDM.2006.346841","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346841","url":null,"abstract":"A novel method for realizing arrays of vertically stacked (e.g., times3 wires stacked) laterally spread out nanowires is presented for the first time using a fully Si-CMOS compatible process. The gate-all-around (GAA) MOSFET devices using these nanowire arrays show excellent performance in terms of near ideal sub-threshold slope (<70 mV/dec), high Ion/Ioff ratio (~107), and low leakage current. Vertical stacking economizes on silicon estate and improves the on-state IDSAT at the same time. Both n- and p-FET devices are demonstrated","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126316388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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