Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346855
Weifeng Zhao, Niu Jin, Guang Chen, Liang Wang, I. Adesida
This paper reports a newly developed fabrication process for monolithic integration of thermally stable InAlAs/InGaAs/InP E/D-HEMTs based on Ir-gate and Ag-ohmic contact technologies. The Ir-gate and Ag-ohmic contacts were annealed simultaneously after passivation using a SiNx layer. Both integrated E/D-HEMTs with gate-length of 0.2 mum demonstrated excellent DC and RF characteristics
本文报道了一种基于Ir-gate和ag -欧姆接触技术的热稳定InAlAs/InGaAs/InP E/ d - hemt单片集成的新工艺。在钝化后，采用SiNx层对Ir-gate和ag -欧姆触点同时退火。两种栅极长度均为0.2 μ m的集成E/ d - hemt均具有优异的直流和射频特性
{"title":"Monolithic integration of thermally stable enhancement-mode and depletion-mode InAlAs/InGaAs/InP HEMTs utilizing Ir-gate and Ag-ohmic contact technologies","authors":"Weifeng Zhao, Niu Jin, Guang Chen, Liang Wang, I. Adesida","doi":"10.1109/IEDM.2006.346855","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346855","url":null,"abstract":"This paper reports a newly developed fabrication process for monolithic integration of thermally stable InAlAs/InGaAs/InP E/D-HEMTs based on Ir-gate and Ag-ohmic contact technologies. The Ir-gate and Ag-ohmic contacts were annealed simultaneously after passivation using a SiNx layer. Both integrated E/D-HEMTs with gate-length of 0.2 mum demonstrated excellent DC and RF characteristics","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133632484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346915
R.T.-P. Lee, T. Liow, K. Tan, A. Lim, Hoong-Shing Wong, P. Lim, D. Lai, G. Lo, C. Tung, G. Samudra, D. Chi, Y. Yeo
In this work, we examined the Schottky-barrier height modulation of NiSi by the incorporation of aluminum (Al), titanium (Ti), erbium (Er), and ytterbium (Yb) in NiSi to form different NiSi-alloys. Among the NiSi-alloy candidates investigated, it was found that the NiAl-alloy silicide provides the most effective Schottky-barrier height lowering (~250 meV) on n-Si(001) substrates. Integration of NiAl-alloy silicides as the source and drain (S/D) silicide material for multiple-gate transistors (MuGFETs) was explored, and shown to deliver a drive current IDsat enhancement of 34% compared to MuGFETs employing NiSi S/D. We further showed that the novel NiAl-alloy silicidation process is compatible with lattice-mismatched silicon-carbon (SiC) S/D stressors. NiAl-alloy silicide is therefore a promising S/D silicide material for reducing the high parasitic series resistance in narrow fin MuGFETs for enhanced device performance
{"title":"Novel Nickel-Alloy Silicides for Source/Drain Contact Resistance Reduction in N-Channel Multiple-Gate Transistors with Sub-35nm Gate Length","authors":"R.T.-P. Lee, T. Liow, K. Tan, A. Lim, Hoong-Shing Wong, P. Lim, D. Lai, G. Lo, C. Tung, G. Samudra, D. Chi, Y. Yeo","doi":"10.1109/IEDM.2006.346915","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346915","url":null,"abstract":"In this work, we examined the Schottky-barrier height modulation of NiSi by the incorporation of aluminum (Al), titanium (Ti), erbium (Er), and ytterbium (Yb) in NiSi to form different NiSi-alloys. Among the NiSi-alloy candidates investigated, it was found that the NiAl-alloy silicide provides the most effective Schottky-barrier height lowering (~250 meV) on n-Si(001) substrates. Integration of NiAl-alloy silicides as the source and drain (S/D) silicide material for multiple-gate transistors (MuGFETs) was explored, and shown to deliver a drive current IDsat enhancement of 34% compared to MuGFETs employing NiSi S/D. We further showed that the novel NiAl-alloy silicidation process is compatible with lattice-mismatched silicon-carbon (SiC) S/D stressors. NiAl-alloy silicide is therefore a promising S/D silicide material for reducing the high parasitic series resistance in narrow fin MuGFETs for enhanced device performance","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131818574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346879
S. Narasimha, K. Onishi, H. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C.-H.J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. van Meer, A. Vayshenker, D. Wehella-gamage, J. Werking, R. Wong, J. Yu, S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Warm, T. Ivers, P. Agnello
We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific performance elements includes enhanced dual-stress liner (DSL), advanced eSiGe, stress memorization (SMT), and advanced anneal (AA). The resulting PFET/NFET Idsat values, at Vdd of 1.0V and 45nm GR gate pitch, are 840muA/mum and 1240muA/mum respectively. The global wiring delay achieved with k=2.4 reflects a 20% reduction compared to k=3.0
{"title":"High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography","authors":"S. Narasimha, K. Onishi, H. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C.-H.J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. van Meer, A. Vayshenker, D. Wehella-gamage, J. Werking, R. Wong, J. Yu, S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Warm, T. Ivers, P. Agnello","doi":"10.1109/IEDM.2006.346879","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346879","url":null,"abstract":"We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific performance elements includes enhanced dual-stress liner (DSL), advanced eSiGe, stress memorization (SMT), and advanced anneal (AA). The resulting PFET/NFET Idsat values, at Vdd of 1.0V and 45nm GR gate pitch, are 840muA/mum and 1240muA/mum respectively. The global wiring delay achieved with k=2.4 reflects a 20% reduction compared to k=3.0","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132197984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.347009
T. Hayashi, Y. Nishida, S. Sakashita, M. Mizutani, S. Yamanari, M. Higashi, T. Kawahara, M. Inoue, J. Yugami, J. Tsuchimoto, K. Shiga, N. Murata, H. Sayama, T. Yamashita, H. Oda, T. Kuroi, T. Eimori, Y. Inoue
High performance LSTP CMISFETs with poly-Si/TiN hybrid gate and high-k dielectric have been studied. Gate depletion is successfully suppressed by in-situ phosphorus doped poly-Si gate for NMIS and by TiN metal gate for PMIS. Vth control for pMIS is accomplished by fluorine implantation into substrate. Optimization of HfSiON formation and TiN removal process is the key to achieve high-reliability. It is demonstrated that this cost-worthy process provides performance which is competitive to reported dual metal CMOS
{"title":"Cost Worthy and High Performance LSTP CMIS; Poly-Si/HfSiON nMIS and Poly-Si/TiN/HfSiON pMIS","authors":"T. Hayashi, Y. Nishida, S. Sakashita, M. Mizutani, S. Yamanari, M. Higashi, T. Kawahara, M. Inoue, J. Yugami, J. Tsuchimoto, K. Shiga, N. Murata, H. Sayama, T. Yamashita, H. Oda, T. Kuroi, T. Eimori, Y. Inoue","doi":"10.1109/IEDM.2006.347009","DOIUrl":"https://doi.org/10.1109/IEDM.2006.347009","url":null,"abstract":"High performance LSTP CMISFETs with poly-Si/TiN hybrid gate and high-k dielectric have been studied. Gate depletion is successfully suppressed by in-situ phosphorus doped poly-Si gate for NMIS and by TiN metal gate for PMIS. Vth control for pMIS is accomplished by fluorine implantation into substrate. Optimization of HfSiON formation and TiN removal process is the key to achieve high-reliability. It is demonstrated that this cost-worthy process provides performance which is competitive to reported dual metal CMOS","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134407083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346846
T. Shino, Naoki Kusunoki, T. Higashi, Takashi Ohsawa, K. Fujita, K. Hatsuda, Nobuyuki Ikumi, Fumiyoshi Matsuoka, Yasuyuki Kajitani, Ryo Fukuda, Yoji Watanabe, Yoshihiro Minami, A. Sakamoto, Jun Nishimura, Hiroomi Nakajima, M. Morikado, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama
Technologies and improved performance of the floating body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the floating body cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant
{"title":"Floating Body RAM Technology and its Scalability to 32nm Node and Beyond","authors":"T. Shino, Naoki Kusunoki, T. Higashi, Takashi Ohsawa, K. Fujita, K. Hatsuda, Nobuyuki Ikumi, Fumiyoshi Matsuoka, Yasuyuki Kajitani, Ryo Fukuda, Yoji Watanabe, Yoshihiro Minami, A. Sakamoto, Jun Nishimura, Hiroomi Nakajima, M. Morikado, Kazumi Inoh, Takeshi Hamamoto, Akihiro Nitayama","doi":"10.1109/IEDM.2006.346846","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346846","url":null,"abstract":"Technologies and improved performance of the floating body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the floating body cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124571357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346874
A. Toriumi, K. Kita, H. Irie
Parasitic effects and Matthiessen's rule have been reinvestigated in the inversion layer mobility analysis. It is shown that an advanced split C-V technique newly developed is very useful for characterizing the intrinsic inversion layer mobility in short channel MOSFETs, even with very large parasitic effects. Furthermore, the validity of Matthiessen's rule is experimentally and theoretically investigated through Hall factor analysis
{"title":"Novel Approach to MOS Inversion Layer Mobility Characterization with Advanced Split C-V and Hall Factor Analyses","authors":"A. Toriumi, K. Kita, H. Irie","doi":"10.1109/IEDM.2006.346874","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346874","url":null,"abstract":"Parasitic effects and Matthiessen's rule have been reinvestigated in the inversion layer mobility analysis. It is shown that an advanced split C-V technique newly developed is very useful for characterizing the intrinsic inversion layer mobility in short channel MOSFETs, even with very large parasitic effects. Furthermore, the validity of Matthiessen's rule is experimentally and theoretically investigated through Hall factor analysis","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124703975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.347011
T. Boscke, S. Govindarajan, C. Fachmann, J. Heitmann, A. Avellan, U. Schroder, S. Kudelka, P. Kirsch, C. Krug, P. Hung, S.C. Song, B. Ju, J. Price, G. Pant, B. Gnade, W. Krautschneider, B. Lee, R. Jammy
We show for the first time that control of the crystalline phases of HfO2 by tetravalent (Si) and trivalent (Y,Gd) dopants enables significant improvements in the capacitance equivalent thickness (CET) and leakage current in capacitors targeting deep trench (DT) DRAM applications. By applying these findings, we present a MIM capacitor meeting the requirements of the 40 nm node. A CET < 1.3 nm was achieved at the deep trench DRAM thermal budget of 1000 degC
{"title":"Tetragonal Phase Stabilization by Doping as an Enabler of Thermally Stable HfO2 based MIM and MIS Capacitors for sub 50nm Deep Trench DRAM","authors":"T. Boscke, S. Govindarajan, C. Fachmann, J. Heitmann, A. Avellan, U. Schroder, S. Kudelka, P. Kirsch, C. Krug, P. Hung, S.C. Song, B. Ju, J. Price, G. Pant, B. Gnade, W. Krautschneider, B. Lee, R. Jammy","doi":"10.1109/IEDM.2006.347011","DOIUrl":"https://doi.org/10.1109/IEDM.2006.347011","url":null,"abstract":"We show for the first time that control of the crystalline phases of HfO2 by tetravalent (Si) and trivalent (Y,Gd) dopants enables significant improvements in the capacitance equivalent thickness (CET) and leakage current in capacitors targeting deep trench (DT) DRAM applications. By applying these findings, we present a MIM capacitor meeting the requirements of the 40 nm node. A CET < 1.3 nm was achieved at the deep trench DRAM thermal budget of 1000 degC","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133595418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346795
D. Ielmini, Yuegang Zhang
The conduction mechanisms in chalcogenide materials for phase-change memory (PCM) applications are studied. A trap-limited transport model for sub-threshold conduction in the amorphous chalcogenide is presented, and extended to threshold switching in the amorphous phase and transport in the highly-conductive crystalline phase, providing a fully-comprehensive, analytical model for PCMs. Finally, a PCM self-rectifying cross-point device is studied with the aid of the model, allowing to evaluate the array performance for different temperatures, read scheme and array size
{"title":"Physics-based analytical model of chalcogenide-based memories for array simulation","authors":"D. Ielmini, Yuegang Zhang","doi":"10.1109/IEDM.2006.346795","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346795","url":null,"abstract":"The conduction mechanisms in chalcogenide materials for phase-change memory (PCM) applications are studied. A trap-limited transport model for sub-threshold conduction in the amorphous chalcogenide is presented, and extended to threshold switching in the amorphous phase and transport in the highly-conductive crystalline phase, providing a fully-comprehensive, analytical model for PCMs. Finally, a PCM self-rectifying cross-point device is studied with the aid of the model, allowing to evaluate the array performance for different temperatures, read scheme and array size","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117217065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346798
E. Piner, S. Singhal, P. Rajagopal, R. Therrien, J. Roberts, Tao Li, A. Hanson, J. W. Johnson, I. Kizilyalli, K. Linthicum
AlGaN/GaN HFET devices demonstrate remarkable performance. For commercial acceptance of this technology, long-term device stability must meet stringent industry standards. We review the current status of GaN reliability and contrast it with the requirement for commercial viability. Results analyzing degradation pertaining to buffer leakage and gate diode forward failure is presented
{"title":"Device Degradation Phenomena in GaN HFET Technology: Status, Mechanisms, and Opportunities","authors":"E. Piner, S. Singhal, P. Rajagopal, R. Therrien, J. Roberts, Tao Li, A. Hanson, J. W. Johnson, I. Kizilyalli, K. Linthicum","doi":"10.1109/IEDM.2006.346798","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346798","url":null,"abstract":"AlGaN/GaN HFET devices demonstrate remarkable performance. For commercial acceptance of this technology, long-term device stability must meet stringent industry standards. We review the current status of GaN reliability and contrast it with the requirement for commercial viability. Results analyzing degradation pertaining to buffer leakage and gate diode forward failure is presented","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121132352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346959
Y. Tateshita, J. Wang, K. Nagano, T. Hirano, Y. Miyanami, T. Ikuta, T. Kataoka, Y. Kikuchi, S. Yamaguchi, T. Ando, K. Tai, R. Matsumoto, S. Fujita, C. Yamane, R. Yamamoto, S. Kanda, K. Kugimiya, T. Kimura, T. Ohchi, Y. Yamamoto, Y. Nagahama, Y. Hagimoto, H. Wakabayashi, Y. Tagawa, M. Tsukamoto, H. Iwamoto, M. Saito, S. Kadomura, N. Nagashima
CMOS technologies using metal/high-k damascene gate stacks with uniaxial strained silicon channels were developed. Gate electrodes of HfSix and TiN were applied to nFETs and pFETs, respectively. TiN/HfO2 damascene gate stacks and epitaxial SiGe source/drains were successfully integrated for the first time. As a result, drive currents of 1050 and 710 muA/mum at Vdd=l V, Ioff=100 nA/um and Tinv=1.6 nm were obtained for the nFETs and pFETs. The further integration of pFETs on (110) substrates contributed to a higher drive current of 830 muA/mum. These performances were realized under low gate leakage currents of 0.03 A/cm2 and below
{"title":"High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates","authors":"Y. Tateshita, J. Wang, K. Nagano, T. Hirano, Y. Miyanami, T. Ikuta, T. Kataoka, Y. Kikuchi, S. Yamaguchi, T. Ando, K. Tai, R. Matsumoto, S. Fujita, C. Yamane, R. Yamamoto, S. Kanda, K. Kugimiya, T. Kimura, T. Ohchi, Y. Yamamoto, Y. Nagahama, Y. Hagimoto, H. Wakabayashi, Y. Tagawa, M. Tsukamoto, H. Iwamoto, M. Saito, S. Kadomura, N. Nagashima","doi":"10.1109/IEDM.2006.346959","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346959","url":null,"abstract":"CMOS technologies using metal/high-k damascene gate stacks with uniaxial strained silicon channels were developed. Gate electrodes of HfSix and TiN were applied to nFETs and pFETs, respectively. TiN/HfO2 damascene gate stacks and epitaxial SiGe source/drains were successfully integrated for the first time. As a result, drive currents of 1050 and 710 muA/mum at Vdd=l V, Ioff=100 nA/um and Tinv=1.6 nm were obtained for the nFETs and pFETs. The further integration of pFETs on (110) substrates contributed to a higher drive current of 830 muA/mum. These performances were realized under low gate leakage currents of 0.03 A/cm2 and below","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115919492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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