Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346985
D. Yoo, C.M. Lee, B. Bae, L.S. Kim, J. Heo, D. Im, S. Choi, S.O. Park, H. Kim, U. Chung, J. Moon, B. Ryu, D. Kim, T. Noh
Feasibility of high density probe-based memory with polycrystalline ferroelectric media has been demonstrated for next memory applications beyond sub-10 nm generation. Noble chemical-mechanical-polishing (CMP) method was employed to fabricate a very even surface on polycrystalline MOCVD Pb(Zr,Ti)O3 (PZT) media. On the CMP processed PZT media, domain dot array was able to be written and read even at grain boundary region by PFM technique. Moreover, 15 nm-sized domain dot was successfully demonstrated on 50 nm-thick PZT media. Also for the first time, we successfully demonstrated that the polycrystalline ultra thin 7 nm-thick PZT media has good ferroelectric properties
{"title":"Noble High Density Probe Memory using Ferroelectric Media beyond Sub-10 nm Generation","authors":"D. Yoo, C.M. Lee, B. Bae, L.S. Kim, J. Heo, D. Im, S. Choi, S.O. Park, H. Kim, U. Chung, J. Moon, B. Ryu, D. Kim, T. Noh","doi":"10.1109/IEDM.2006.346985","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346985","url":null,"abstract":"Feasibility of high density probe-based memory with polycrystalline ferroelectric media has been demonstrated for next memory applications beyond sub-10 nm generation. Noble chemical-mechanical-polishing (CMP) method was employed to fabricate a very even surface on polycrystalline MOCVD Pb(Zr,Ti)O3 (PZT) media. On the CMP processed PZT media, domain dot array was able to be written and read even at grain boundary region by PFM technique. Moreover, 15 nm-sized domain dot was successfully demonstrated on 50 nm-thick PZT media. Also for the first time, we successfully demonstrated that the polycrystalline ultra thin 7 nm-thick PZT media has good ferroelectric properties","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128482177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346889
M. Rais-Zadeh, P. Kohl, F. Ayazi
This paper presents high aspect-ratio silver (Ag) micromachining for implementation of very high quality factor (Q) tunable, and fixed passives, and low insertion loss bandpass LC filters. A combination of low-loss substrate and highest conductivity metal is used to achieve record high Q and low insertion loss (IL) at radio frequencies
{"title":"High-Q Micromachined Silver Passives and Filters","authors":"M. Rais-Zadeh, P. Kohl, F. Ayazi","doi":"10.1109/IEDM.2006.346889","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346889","url":null,"abstract":"This paper presents high aspect-ratio silver (Ag) micromachining for implementation of very high quality factor (Q) tunable, and fixed passives, and low insertion loss bandpass LC filters. A combination of low-loss substrate and highest conductivity metal is used to achieve record high Q and low insertion loss (IL) at radio frequencies","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129653829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346759
T. Hoffmann, A. Veloso, A. Lauwers, H. Yu, H. Tigelaar, M. V. van Dal, T. Chiarella, C. Kerner, T. Kauerauf, A. Shickova, R. Mitsuhashi, I. Satoru, M. Niwa, A. Rothschild, B. Froment, J. Ramos, A. Nackaerts, M. Rosmeulen, S. Brus, C. Vrancken, P. Absil, M. Jurczak, S. Biesemans, J. Kittl
This work reports the first comprehensive evaluation of FUSI gates for manufacturability, covering the key aspects of integration, process control, reliability, matching, device design and circuit-level benefit. Thanks to a selective and controlled poly etch-back process, dual work-function Ni-based FUSI CMOS circuits with record ring oscillator performance (high-VT applications) have been achieved (17ps at VDD=1.1V and 20pA/mum Ioff), meeting the ITRS 45nm node requirement for low power CMOS
本文首次对FUSI栅极的可制造性进行了全面评估，涵盖了集成、过程控制、可靠性、匹配、器件设计和电路级效益等关键方面。由于采用选择性和可控的聚反蚀刻工艺，实现了双工作功能镍基FUSI CMOS电路，具有创纪录的环形振荡器性能(高vt应用)(VDD=1.1V和20pA/ ma off时17ps)，满足ITRS 45nm节点对低功耗CMOS的要求
{"title":"Ni-based FUSI gates: CMOS Integration for 45nm node and beyond","authors":"T. Hoffmann, A. Veloso, A. Lauwers, H. Yu, H. Tigelaar, M. V. van Dal, T. Chiarella, C. Kerner, T. Kauerauf, A. Shickova, R. Mitsuhashi, I. Satoru, M. Niwa, A. Rothschild, B. Froment, J. Ramos, A. Nackaerts, M. Rosmeulen, S. Brus, C. Vrancken, P. Absil, M. Jurczak, S. Biesemans, J. Kittl","doi":"10.1109/IEDM.2006.346759","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346759","url":null,"abstract":"This work reports the first comprehensive evaluation of FUSI gates for manufacturability, covering the key aspects of integration, process control, reliability, matching, device design and circuit-level benefit. Thanks to a selective and controlled poly etch-back process, dual work-function Ni-based FUSI CMOS circuits with record ring oscillator performance (high-VT applications) have been achieved (17ps at VDD=1.1V and 20pA/mum Ioff), meeting the ITRS 45nm node requirement for low power CMOS","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127284260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346963
A. Kinoshita, T. Kinoshita, Y. Nishi, K. Uchida, S. Toriyama, R. Hasumi, J. Koga
The carrier transport in dopant-segregated Schottky (DSS) and conventional MOSFETs was thoroughly investigated in terms of carrier injection velocity, vinj. It was found that vinj enhancement associated with the velocity overshoot enhances the current drivability in DSS, in addition to the reduction of parasitic resistance. A physical-based model was newly developed to explain the velocity overshoot behavior and reproduced the experimental data very well. Moreover, a novel type of DSS FinFET to take full advantage of the velocity overshoot was proposed and demonstrated as a primary study
{"title":"Comprehensive Study on Injection Velocity Enhancement in Dopant-Segregated Schottky MOSFETs","authors":"A. Kinoshita, T. Kinoshita, Y. Nishi, K. Uchida, S. Toriyama, R. Hasumi, J. Koga","doi":"10.1109/IEDM.2006.346963","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346963","url":null,"abstract":"The carrier transport in dopant-segregated Schottky (DSS) and conventional MOSFETs was thoroughly investigated in terms of carrier injection velocity, vinj. It was found that vinj enhancement associated with the velocity overshoot enhances the current drivability in DSS, in addition to the reduction of parasitic resistance. A physical-based model was newly developed to explain the velocity overshoot behavior and reproduced the experimental data very well. Moreover, a novel type of DSS FinFET to take full advantage of the velocity overshoot was proposed and demonstrated as a primary study","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127073047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346971
A. Salman, S. Beebe, M. Emam, M. Pelella, D. Ioannou
In this paper the authors present the field effect diode (FED) as a novel device with a new approach for ESD protection in SOI. Device parameters are identified and optimized to achieve optimum ON and OFF behavior. Furthermore, the authors present two ways the FED can be used in an ESD protection scheme: in I/O clamping and in a high-voltage supply clamp
{"title":"Field Effect Diode (FED): A novel device for ESD protection in deep sub-micron SOI technologies","authors":"A. Salman, S. Beebe, M. Emam, M. Pelella, D. Ioannou","doi":"10.1109/IEDM.2006.346971","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346971","url":null,"abstract":"In this paper the authors present the field effect diode (FED) as a novel device with a new approach for ESD protection in SOI. Device parameters are identified and optimized to achieve optimum ON and OFF behavior. Furthermore, the authors present two ways the FED can be used in an ESD protection scheme: in I/O clamping and in a high-voltage supply clamp","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"92 41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128908819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346891
K. Kuwabara, N. Sato, T. Shimamura, H. Morimura, J. Kodate, T. Sakata, S. Shigematsu, K. Kudou, K. Machida, M. Nakanishi, H. Ishii
This paper describes a novel RF CMOS-MEMS switch that integrates RF MEMS switches and CMOS control circuits. A single-pole 8-through RF CMOS-MEMS switch was fabricated and its operation at 3.3 V supply voltage was achieved. The switch was encapsulated with a thin film at wafer level to prevent destruction during packaging. Experimental results confirm that the switch has mechanical reliability for more than 1 billion cycles
{"title":"RF CMOS-MEMS Switch with Low-Voltage Operation for Single-Chip RF LSIs","authors":"K. Kuwabara, N. Sato, T. Shimamura, H. Morimura, J. Kodate, T. Sakata, S. Shigematsu, K. Kudou, K. Machida, M. Nakanishi, H. Ishii","doi":"10.1109/IEDM.2006.346891","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346891","url":null,"abstract":"This paper describes a novel RF CMOS-MEMS switch that integrates RF MEMS switches and CMOS control circuits. A single-pole 8-through RF CMOS-MEMS switch was fabricated and its operation at 3.3 V supply voltage was achieved. The switch was encapsulated with a thin film at wafer level to prevent destruction during packaging. Experimental results confirm that the switch has mechanical reliability for more than 1 billion cycles","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125668016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346837
Gang Chen, C. Dames, A. Henry
Thermoelectric effects enable direct energy conversion between heat and electricity. Various size effects can be explored to increase the thermoelectric performance of nanostructures compared to bulk. Boundary scattering reduces the phonon thermal conductivity, and quantum confinement and interface energy filtering can improve the electronic power factor. Theoretical and experimental results are described for thin films, nanowires, and nanocomposites
{"title":"Thermoelectric Energy Conversion in Nanostructures","authors":"Gang Chen, C. Dames, A. Henry","doi":"10.1109/IEDM.2006.346837","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346837","url":null,"abstract":"Thermoelectric effects enable direct energy conversion between heat and electricity. Various size effects can be explored to increase the thermoelectric performance of nanostructures compared to bulk. Boundary scattering reduces the phonon thermal conductivity, and quantum confinement and interface energy filtering can improve the electronic power factor. Theoretical and experimental results are described for thin films, nanowires, and nanocomposites","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121308209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.347010
J. Buckley, M. Bocquet, G. Molas, M. Gely, P. Brianceau, N. Rochat, E. Martinez, F. Martin, H. Grampeix, J. Colonna, A. Toffoli, V. Vidal, C. Leroux, G. Ghibaudo, G. Pananakakis, C. Bongiorno, D. Corso, S. Lombardo, B. Desalvo, S. Deleonibus
In this paper, different Hf-based oxides (HfO2, HfSiO under several annealing conditions, HfSiON, HfAlO with various compositions) are simultaneously considered as storage layers of charge-trap memories. Based on material characterization analyses, electrical data of memory cells, physical modeling of charge-trap devices, we show that a strict relationship exists between the crystal structure of the storage layer and the memory performances. The obtained results clearly demonstrate the high interest of HfO2 dielectric as possible storage layer of future NROM-like memory devices
{"title":"In-depth Investigation of Hf-based High-k Dielectrics as Storage Layer of Charge-Trap NVMs","authors":"J. Buckley, M. Bocquet, G. Molas, M. Gely, P. Brianceau, N. Rochat, E. Martinez, F. Martin, H. Grampeix, J. Colonna, A. Toffoli, V. Vidal, C. Leroux, G. Ghibaudo, G. Pananakakis, C. Bongiorno, D. Corso, S. Lombardo, B. Desalvo, S. Deleonibus","doi":"10.1109/IEDM.2006.347010","DOIUrl":"https://doi.org/10.1109/IEDM.2006.347010","url":null,"abstract":"In this paper, different Hf-based oxides (HfO2, HfSiO under several annealing conditions, HfSiON, HfAlO with various compositions) are simultaneously considered as storage layers of charge-trap memories. Based on material characterization analyses, electrical data of memory cells, physical modeling of charge-trap devices, we show that a strict relationship exists between the crystal structure of the storage layer and the memory performances. The obtained results clearly demonstrate the high interest of HfO2 dielectric as possible storage layer of future NROM-like memory devices","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115804085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346834
Maarten Vertregt
Nanometer CMOS technology offers the required integration density for advanced products such as home theatre equipment and personal communication devices. The system solutions inside these products demand highly integrated systems-on-silicon, blending high-density digital functions with analog interface circuits. These integrated solutions have to cope with high data-rates, and thus require high speed and high dynamic range circuits, without compromising power consumption. Novel choices on circuit and system level are required to handle the increased number of devices subject to high variability, running at higher intrinsic speeds with a constraint power supply
{"title":"The analog challenge of nanometer CMOS","authors":"Maarten Vertregt","doi":"10.1109/IEDM.2006.346834","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346834","url":null,"abstract":"Nanometer CMOS technology offers the required integration density for advanced products such as home theatre equipment and personal communication devices. The system solutions inside these products demand highly integrated systems-on-silicon, blending high-density digital functions with analog interface circuits. These integrated solutions have to cope with high data-rates, and thus require high speed and high dynamic range circuits, without compromising power consumption. Novel choices on circuit and system level are required to handle the increased number of devices subject to high variability, running at higher intrinsic speeds with a constraint power supply","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125124054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346820
S. Gu, C.W. Li, Tahui Wang, W.P. Lu, K.C. Chen, J. Ku, Chih-Yuan Lu
Program/erase cycling stress induced read current fluctuations arising from random telegraph noise (RTN) in a localized storage, multi-level nitride flash memory (SONOS) is explored. Our study shows that localized charge storage significantly enhances RTN. The amplitude of RTN varies in different program levels of a multi-level cell. The broadening of read current distribution due to RTN is characterized and modeled. Improvement of bottom oxide robustness can reduce the read current fluctuations
{"title":"Read Current Instability Arising from Random Telegraph Noise in Localized Storage, Multi-Level SONOS Flash Memory","authors":"S. Gu, C.W. Li, Tahui Wang, W.P. Lu, K.C. Chen, J. Ku, Chih-Yuan Lu","doi":"10.1109/IEDM.2006.346820","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346820","url":null,"abstract":"Program/erase cycling stress induced read current fluctuations arising from random telegraph noise (RTN) in a localized storage, multi-level nitride flash memory (SONOS) is explored. Our study shows that localized charge storage significantly enhances RTN. The amplitude of RTN varies in different program levels of a multi-level cell. The broadening of read current distribution due to RTN is characterized and modeled. Improvement of bottom oxide robustness can reduce the read current fluctuations","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133588808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：