Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346848
T. Tran, R. Weis, A. Sieck, T. Hecht, G. Aichmayr, M. Goldbach, P.-F. Wang, A. Thies, G. Wedler, J. Nuetzel, D. Wu, C. Eckl, R. Duschl, T.-M. Kuo, Ying-Tse Chiang, W. Mueller
The authors present for the first time the full integration scheme and 512Mb product data for a trench DRAM technology targeting the 58nm node. The key technology enablers such as an extended U-shape cell device (EUD), high performance support devices, trench capacitor with metal-insulator-silicon (MIS)/high-k dielectric and metal-in-collar (MIC), and low-k inter-level dielectric (ILD) are demonstrated
{"title":"A 58nm Trench DRAM Technology","authors":"T. Tran, R. Weis, A. Sieck, T. Hecht, G. Aichmayr, M. Goldbach, P.-F. Wang, A. Thies, G. Wedler, J. Nuetzel, D. Wu, C. Eckl, R. Duschl, T.-M. Kuo, Ying-Tse Chiang, W. Mueller","doi":"10.1109/IEDM.2006.346848","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346848","url":null,"abstract":"The authors present for the first time the full integration scheme and 512Mb product data for a trench DRAM technology targeting the 58nm node. The key technology enablers such as an extended U-shape cell device (EUD), high performance support devices, trench capacitor with metal-insulator-silicon (MIS)/high-k dielectric and metal-in-collar (MIC), and low-k inter-level dielectric (ILD) are demonstrated","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122236133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346783
K. Takeda, R. Yamada, T. Imai, T. Fujiwara, T. Hashimoto, T. Ando
Time-dependent capacitance-density (CD) increase and linearity degradations of HfAlO-MIM capacitors by constant voltage stress were demonstrated for the first time. It was found that extrapolated CD increase after 10 years strongly depends on Al concentration in HfAlO dielectric. Accordingly, Al concentration of more than 14 at.% is required to keep CD increase below 1%. It was also found that the CD increase and linearity degradations (temperature and frequency) originate from the dielectric-loss increase and that the relationships between these parameters quantitatively agree with Gevers' model
{"title":"DC-stress-induced Degradation of Analog Characteristics in HfxAl(1-x)O MIM Capacitors","authors":"K. Takeda, R. Yamada, T. Imai, T. Fujiwara, T. Hashimoto, T. Ando","doi":"10.1109/IEDM.2006.346783","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346783","url":null,"abstract":"Time-dependent capacitance-density (CD) increase and linearity degradations of HfAlO-MIM capacitors by constant voltage stress were demonstrated for the first time. It was found that extrapolated CD increase after 10 years strongly depends on Al concentration in HfAlO dielectric. Accordingly, Al concentration of more than 14 at.% is required to keep CD increase below 1%. It was also found that the CD increase and linearity degradations (temperature and frequency) originate from the dielectric-loss increase and that the relationships between these parameters quantitatively agree with Gevers' model","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126196272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346986
R. Leuschner, U. Klostermann, H. Park, F. Dahmani, R. Dittrich, C. Grigis, K. Hernan, S. Mege, C. Park, M. C. Clech, G. Y. Lee, S. Bournat, L. Altimime, G. Mueller
We report on a novel thermal select (TS) MRAM with multilevel programming capability. Exchange bias pinning of a magnetic free layer (FL) was used to achieve a thermally stable bit and to reduce writing currents. This report shows experimental data for a TS-based magnetic tunnel junction (MTJ) with a size of 50 times90 nm2, the smallest size reported so far. Multilevel capability with 2 bits per 1-transistor and 1-MTJ (1T1MTJ) is also demonstrated on a 70 times 140 nm2 MTJ. With the advanced 2-bit cell concept, a 70% increase in effective bit density can be achieved at 65 nm technology node
{"title":"Thermal Select MRAM with a 2-bit Cell Capability for beyond 65 nm Technology Node","authors":"R. Leuschner, U. Klostermann, H. Park, F. Dahmani, R. Dittrich, C. Grigis, K. Hernan, S. Mege, C. Park, M. C. Clech, G. Y. Lee, S. Bournat, L. Altimime, G. Mueller","doi":"10.1109/IEDM.2006.346986","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346986","url":null,"abstract":"We report on a novel thermal select (TS) MRAM with multilevel programming capability. Exchange bias pinning of a magnetic free layer (FL) was used to achieve a thermally stable bit and to reduce writing currents. This report shows experimental data for a TS-based magnetic tunnel junction (MTJ) with a size of 50 times90 nm2, the smallest size reported so far. Multilevel capability with 2 bits per 1-transistor and 1-MTJ (1T1MTJ) is also demonstrated on a 70 times 140 nm2 MTJ. With the advanced 2-bit cell concept, a 70% increase in effective bit density can be achieved at 65 nm technology node","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126672375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346988
M. Kobayashi, T. Hiramoto
We fabricated [100] and [110] directed nano wire MOSFET (NWFET), which works as NFET and PFET in the same channel. By comparing [100] and [110] direction, significantly small threshold voltage (Vth) fluctuation is experimentally observed in [110] PFET for the first time. This result supports the superiority of [110] NW PFET. Extremely narrow NWFET works as single-electron/single-hole transistors (SET/SHT). By comparing [100] and [110] direction, channel direction dependence of Coulomb blockade (CB) oscillations is experimentally clarified for the first time. We realize the highest performance in [100] SHT
{"title":"Experimental Study on Quantum Structure of Silicon Nano Wire and Its Impact on Nano Wire MOSFET and Single-Electron Transistor","authors":"M. Kobayashi, T. Hiramoto","doi":"10.1109/IEDM.2006.346988","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346988","url":null,"abstract":"We fabricated [100] and [110] directed nano wire MOSFET (NWFET), which works as NFET and PFET in the same channel. By comparing [100] and [110] direction, significantly small threshold voltage (Vth) fluctuation is experimentally observed in [110] PFET for the first time. This result supports the superiority of [110] NW PFET. Extremely narrow NWFET works as single-electron/single-hole transistors (SET/SHT). By comparing [100] and [110] direction, channel direction dependence of Coulomb blockade (CB) oscillations is experimentally clarified for the first time. We realize the highest performance in [100] SHT","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126988830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346920
Y.S. Kim, Y. Shimamune, M. Fukuda, A. Katakami, A. Hatada, K. Kawamura, H. Ohta, T. Sakuma, Y. Hayami, H. Morioka, J. Ogura, T. Minami, N. Tamura, T. Mori, M. Kojima, K. Sukegawa, K. Hashimoto, M. Miyajima, S. Satoh, T. Sugii
The impact of defects on the short channel effects (SCE) and the drivability of a pMOSFET with a SiGe source/drain is described, and useful methods to reduce defect formation are suggested. The influence of defects on device performance is found to become more severe as recess depth increases and/or channel length decreases. By optimizing the epitaxial process, including an in-situ precleaning step, the initial defect density is reduced, and by introducing a cap layer on a SiGe layer, the thermal stability of the SiGe layer is improved. The optimized devices enhance mobility 42% by maximizing the strain effect and provide better SCE characteristics by suppressing boron diffusion
{"title":"Suppression of Defect Formation and Their Impact on Short Channel Effects and Drivability of pMOSFET with SiGe Source/Drain","authors":"Y.S. Kim, Y. Shimamune, M. Fukuda, A. Katakami, A. Hatada, K. Kawamura, H. Ohta, T. Sakuma, Y. Hayami, H. Morioka, J. Ogura, T. Minami, N. Tamura, T. Mori, M. Kojima, K. Sukegawa, K. Hashimoto, M. Miyajima, S. Satoh, T. Sugii","doi":"10.1109/IEDM.2006.346920","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346920","url":null,"abstract":"The impact of defects on the short channel effects (SCE) and the drivability of a pMOSFET with a SiGe source/drain is described, and useful methods to reduce defect formation are suggested. The influence of defects on device performance is found to become more severe as recess depth increases and/or channel length decreases. By optimizing the epitaxial process, including an in-situ precleaning step, the initial defect density is reduced, and by introducing a cap layer on a SiGe layer, the thermal stability of the SiGe layer is improved. The optimized devices enhance mobility 42% by maximizing the strain effect and provide better SCE characteristics by suppressing boron diffusion","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127277732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346903
E. Lai, H. Lue, Y. Hsiao, J. Hsieh, Chi-Pin Lu, Szu-Yu Wang, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, J. Gong, K. Hsieh, Rich Liu, Chih-Yuan Lu
A double-layer TFT NAND-type flash memory is demonstrated, ushering into the era of three-dimensional (3D) flash memory. A TFT device using bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005, Lai et al., 2006) with fully-depleted (FD) poly silicon (60 nm) channel and tri-gate P+-poly gate is integrated into a NAND array. Small devices (L/W=0.2/0.09 mum) with excellent performance and reliability properties are achieved. The bottom layer shows no sign of reliability degradation compared to the top layer, indicating the potential for further multi-layer stacking. The present work illustrates the feasibility of 3D flash memory
{"title":"A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory","authors":"E. Lai, H. Lue, Y. Hsiao, J. Hsieh, Chi-Pin Lu, Szu-Yu Wang, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, J. Gong, K. Hsieh, Rich Liu, Chih-Yuan Lu","doi":"10.1109/IEDM.2006.346903","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346903","url":null,"abstract":"A double-layer TFT NAND-type flash memory is demonstrated, ushering into the era of three-dimensional (3D) flash memory. A TFT device using bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005, Lai et al., 2006) with fully-depleted (FD) poly silicon (60 nm) channel and tri-gate P+-poly gate is integrated into a NAND array. Small devices (L/W=0.2/0.09 mum) with excellent performance and reliability properties are achieved. The bottom layer shows no sign of reliability degradation compared to the top layer, indicating the potential for further multi-layer stacking. The present work illustrates the feasibility of 3D flash memory","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127514827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346840
N. Singh, F. Y. Lim, W. Fang, S. Rustagi, L. Bera, A. Agarwal, C. Tung, K. Hoe, S. R. Omampuliyur, D. Tripathi, A. Adeyeye, G. Lo, N. Balasubramanian, D. Kwong
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well
{"title":"Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance","authors":"N. Singh, F. Y. Lim, W. Fang, S. Rustagi, L. Bera, A. Agarwal, C. Tung, K. Hoe, S. R. Omampuliyur, D. Tripathi, A. Adeyeye, G. Lo, N. Balasubramanian, D. Kwong","doi":"10.1109/IEDM.2006.346840","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346840","url":null,"abstract":"Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122404757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346953
Yongxun Liu, T. Matsukawa, K. Endo, M. Masahara, K. Ishii, S. O'Uchi, H. Yamauchi, J. Tsukada, Y. Ishikawa, E. Suzuki
We have successfully developed the advanced FinFET fabrication processes for materializing FinFET CMOS circuits. Using the developed technologies, we demonstrate the advanced TiN metal gate, fin-height controlled FinFET CMOS inverter with an excellent transfer performance, and the flexible threshold voltage, asymmetric gate insulator thickness four-terminal (4T) FinFET with a greatly improved subthreshold (S) slope, for the first time
{"title":"Advanced FinFET CMOS Technology: TiN-Gate, Fin-Height Control and Asymmetric Gate Insulator Thickness 4T-FinFETs","authors":"Yongxun Liu, T. Matsukawa, K. Endo, M. Masahara, K. Ishii, S. O'Uchi, H. Yamauchi, J. Tsukada, Y. Ishikawa, E. Suzuki","doi":"10.1109/IEDM.2006.346953","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346953","url":null,"abstract":"We have successfully developed the advanced FinFET fabrication processes for materializing FinFET CMOS circuits. Using the developed technologies, we demonstrate the advanced TiN metal gate, fin-height controlled FinFET CMOS inverter with an excellent transfer performance, and the flexible threshold voltage, asymmetric gate insulator thickness four-terminal (4T) FinFET with a greatly improved subthreshold (S) slope, for the first time","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127928263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346865
F. Andrieu, O. Faynot, X. Garros, D. Lafond, C. Buj-Dufournet, L. Tosti, S. Minoret, V. Vidal, J. Barbe, F. Allain, E. Rouchouze, L. Vandroux, V. Cosnier, M. Cassé, V. Delaye, C. Carabasse, M. Burdin, G. Rolland, B. Guillaumot, J. Colonna, P. Besson, L. Brevard, D. Mariolle, P. Holliger, A. Vandooren, C. Fenouillet-Béranger, F. Martin, S. Deleonibus
This paper compares, for the first time, the scalability of physical- and chemical-vapor-deposited (PVD and CVD) TiN on HfO2 as a gate stack for FDSOI cMOSFETs down to 25nm gate length and width. It is shown that not only the intrinsic material properties but also the device architecture strongly influences the final gate stack properties. Reliability issues, stress and gate control in the sub-35nm scale are reported and explained, thanks to material, electric data and mechanical simulations. In spite of its lower performance on large device dimensions, PVD-TiN demonstrates a better overall trade-off, leading to a 17% ion improvement on 25nm short and narrow devices
{"title":"Comparative Scalability of PVD and CVD TiN on HfO2 as a Metal Gate Stack for FDSOI cMOSFETs down to 25nm Gate Length and Width","authors":"F. Andrieu, O. Faynot, X. Garros, D. Lafond, C. Buj-Dufournet, L. Tosti, S. Minoret, V. Vidal, J. Barbe, F. Allain, E. Rouchouze, L. Vandroux, V. Cosnier, M. Cassé, V. Delaye, C. Carabasse, M. Burdin, G. Rolland, B. Guillaumot, J. Colonna, P. Besson, L. Brevard, D. Mariolle, P. Holliger, A. Vandooren, C. Fenouillet-Béranger, F. Martin, S. Deleonibus","doi":"10.1109/IEDM.2006.346865","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346865","url":null,"abstract":"This paper compares, for the first time, the scalability of physical- and chemical-vapor-deposited (PVD and CVD) TiN on HfO2 as a gate stack for FDSOI cMOSFETs down to 25nm gate length and width. It is shown that not only the intrinsic material properties but also the device architecture strongly influences the final gate stack properties. Reliability issues, stress and gate control in the sub-35nm scale are reported and explained, thanks to material, electric data and mechanical simulations. In spite of its lower performance on large device dimensions, PVD-TiN demonstrates a better overall trade-off, leading to a 17% ion improvement on 25nm short and narrow devices","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121244847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346942
S. Eminente, N. Barin, P. Palestri, C. Fiegna, E. Sangiorgi
A state of the art Monte-Carlo simulator is applied to the investigation of the RF performance of bulk MOSFETs designed according to the prescriptions of the 2005 ITRS Roadmap for analog and mixed signal applications, and of a 53 nm ultra-thin-body (UTB) single-gate (SG) SOI MOSFET. We provide an analysis of the signal-delay build-up along the channel and an investigation of the scaling properties of the parameters of the AC equivalent circuit, the transition frequency FT, and the 3dB bandwidth of the voltage gain in common-source configuration. The effects of ballistic transport and their impact on the AC figures of merit are investigated for short UTB double-gate MOSFETs
根据2005年ITRS路线图的规定设计的用于模拟和混合信号应用的块体MOSFET，以及53 nm超薄体(UTB)单门(SG) SOI MOSFET，应用最先进的蒙特卡罗模拟器来研究射频性能。我们分析了沿通道累积的信号延迟，并研究了交流等效电路参数、过渡频率FT和共源配置下电压增益的3dB带宽的缩放特性。研究了短UTB双栅mosfet的弹道输运效应及其对交流性能因数的影响
{"title":"Monte Carlo Simulation of deca-nanometer MOSFETs for Analog/Mixed-signal and RF applications","authors":"S. Eminente, N. Barin, P. Palestri, C. Fiegna, E. Sangiorgi","doi":"10.1109/IEDM.2006.346942","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346942","url":null,"abstract":"A state of the art Monte-Carlo simulator is applied to the investigation of the RF performance of bulk MOSFETs designed according to the prescriptions of the 2005 ITRS Roadmap for analog and mixed signal applications, and of a 53 nm ultra-thin-body (UTB) single-gate (SG) SOI MOSFET. We provide an analysis of the signal-delay build-up along the channel and an investigation of the scaling properties of the parameters of the AC equivalent circuit, the transition frequency FT, and the 3dB bandwidth of the voltage gain in common-source configuration. The effects of ballistic transport and their impact on the AC figures of merit are investigated for short UTB double-gate MOSFETs","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121387290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：