Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346859
C. Wu, B. Hung, A. Chin, S. Wang, W. Chen, X.P. Wang, M. Li, C. Zhu, Y. Jin, H. Tao, S. Chen, M. Liang
The authors report novel 1000degC-stable [Ir3Si-TaN]/HfLaON CMOS for the first time, where the self-aligned and gate-first process are full compatible to current VLSI. Good Phim-eff of 5.08 and 4.24 eV, low Vt of -0.10 and 0.18 V, high mobility of 84 and 217 cm2/Vs at 1.6 nm EOT, and small 85degC BTI <20 mV (10 MV/cm for 1 hr) are measured
{"title":"High Temperature Stable [Ir3Si-TaN]/HfLaON CMOS with Large Work-Function Difference","authors":"C. Wu, B. Hung, A. Chin, S. Wang, W. Chen, X.P. Wang, M. Li, C. Zhu, Y. Jin, H. Tao, S. Chen, M. Liang","doi":"10.1109/IEDM.2006.346859","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346859","url":null,"abstract":"The authors report novel 1000degC-stable [Ir<sub>3</sub>Si-TaN]/HfLaON CMOS for the first time, where the self-aligned and gate-first process are full compatible to current VLSI. Good Phi<sub>m-eff</sub> of 5.08 and 4.24 eV, low V<sub>t</sub> of -0.10 and 0.18 V, high mobility of 84 and 217 cm<sup>2</sup>/Vs at 1.6 nm EOT, and small 85degC BTI <20 mV (10 MV/cm for 1 hr) are measured","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"106 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125987097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346903
E. Lai, H. Lue, Y. Hsiao, J. Hsieh, Chi-Pin Lu, Szu-Yu Wang, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, J. Gong, K. Hsieh, Rich Liu, Chih-Yuan Lu
A double-layer TFT NAND-type flash memory is demonstrated, ushering into the era of three-dimensional (3D) flash memory. A TFT device using bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005, Lai et al., 2006) with fully-depleted (FD) poly silicon (60 nm) channel and tri-gate P+-poly gate is integrated into a NAND array. Small devices (L/W=0.2/0.09 mum) with excellent performance and reliability properties are achieved. The bottom layer shows no sign of reliability degradation compared to the top layer, indicating the potential for further multi-layer stacking. The present work illustrates the feasibility of 3D flash memory
{"title":"A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory","authors":"E. Lai, H. Lue, Y. Hsiao, J. Hsieh, Chi-Pin Lu, Szu-Yu Wang, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, J. Gong, K. Hsieh, Rich Liu, Chih-Yuan Lu","doi":"10.1109/IEDM.2006.346903","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346903","url":null,"abstract":"A double-layer TFT NAND-type flash memory is demonstrated, ushering into the era of three-dimensional (3D) flash memory. A TFT device using bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005, Lai et al., 2006) with fully-depleted (FD) poly silicon (60 nm) channel and tri-gate P+-poly gate is integrated into a NAND array. Small devices (L/W=0.2/0.09 mum) with excellent performance and reliability properties are achieved. The bottom layer shows no sign of reliability degradation compared to the top layer, indicating the potential for further multi-layer stacking. The present work illustrates the feasibility of 3D flash memory","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127514827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346818
B. Govoreanu, D. Wellekens, L. Haspeslagh, J. de Vos, J. van Houdt
We describe the low-field leakage through high-k interpoly dielectric stacks in floating gate nonvolatile memories with an inelastic trap-assisted tunneling model, which accounts for arbitrary trap distributions in both energy and space. A systematic investigation of the impact of trap parameters, stack composition, bias and temperature on the leakage is presented, focusing on Al2O3-based stacks. Room- and high-temperature retention data indicate charge loss/gain due to bulk traps in Al2 O3, with an average depth of 2.2 eV and a spread of plusmn0.3 eV. Scalability of Al2O3 IPD stacks below 6.5 nm EOT may be achieved by reducing the trap density by at least 1 order of magnitude
{"title":"Investigation of the low-field leakage through high-k interpoly dielectric stacks and its impact on nonvolatile memory data retention","authors":"B. Govoreanu, D. Wellekens, L. Haspeslagh, J. de Vos, J. van Houdt","doi":"10.1109/IEDM.2006.346818","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346818","url":null,"abstract":"We describe the low-field leakage through high-k interpoly dielectric stacks in floating gate nonvolatile memories with an inelastic trap-assisted tunneling model, which accounts for arbitrary trap distributions in both energy and space. A systematic investigation of the impact of trap parameters, stack composition, bias and temperature on the leakage is presented, focusing on Al2O3-based stacks. Room- and high-temperature retention data indicate charge loss/gain due to bulk traps in Al2 O3, with an average depth of 2.2 eV and a spread of plusmn0.3 eV. Scalability of Al2O3 IPD stacks below 6.5 nm EOT may be achieved by reducing the trap density by at least 1 order of magnitude","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127457569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.347011
T. Boscke, S. Govindarajan, C. Fachmann, J. Heitmann, A. Avellan, U. Schroder, S. Kudelka, P. Kirsch, C. Krug, P. Hung, S.C. Song, B. Ju, J. Price, G. Pant, B. Gnade, W. Krautschneider, B. Lee, R. Jammy
We show for the first time that control of the crystalline phases of HfO2 by tetravalent (Si) and trivalent (Y,Gd) dopants enables significant improvements in the capacitance equivalent thickness (CET) and leakage current in capacitors targeting deep trench (DT) DRAM applications. By applying these findings, we present a MIM capacitor meeting the requirements of the 40 nm node. A CET < 1.3 nm was achieved at the deep trench DRAM thermal budget of 1000 degC
{"title":"Tetragonal Phase Stabilization by Doping as an Enabler of Thermally Stable HfO2 based MIM and MIS Capacitors for sub 50nm Deep Trench DRAM","authors":"T. Boscke, S. Govindarajan, C. Fachmann, J. Heitmann, A. Avellan, U. Schroder, S. Kudelka, P. Kirsch, C. Krug, P. Hung, S.C. Song, B. Ju, J. Price, G. Pant, B. Gnade, W. Krautschneider, B. Lee, R. Jammy","doi":"10.1109/IEDM.2006.347011","DOIUrl":"https://doi.org/10.1109/IEDM.2006.347011","url":null,"abstract":"We show for the first time that control of the crystalline phases of HfO2 by tetravalent (Si) and trivalent (Y,Gd) dopants enables significant improvements in the capacitance equivalent thickness (CET) and leakage current in capacitors targeting deep trench (DT) DRAM applications. By applying these findings, we present a MIM capacitor meeting the requirements of the 40 nm node. A CET < 1.3 nm was achieved at the deep trench DRAM thermal budget of 1000 degC","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133595418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346848
T. Tran, R. Weis, A. Sieck, T. Hecht, G. Aichmayr, M. Goldbach, P.-F. Wang, A. Thies, G. Wedler, J. Nuetzel, D. Wu, C. Eckl, R. Duschl, T.-M. Kuo, Ying-Tse Chiang, W. Mueller
The authors present for the first time the full integration scheme and 512Mb product data for a trench DRAM technology targeting the 58nm node. The key technology enablers such as an extended U-shape cell device (EUD), high performance support devices, trench capacitor with metal-insulator-silicon (MIS)/high-k dielectric and metal-in-collar (MIC), and low-k inter-level dielectric (ILD) are demonstrated
{"title":"A 58nm Trench DRAM Technology","authors":"T. Tran, R. Weis, A. Sieck, T. Hecht, G. Aichmayr, M. Goldbach, P.-F. Wang, A. Thies, G. Wedler, J. Nuetzel, D. Wu, C. Eckl, R. Duschl, T.-M. Kuo, Ying-Tse Chiang, W. Mueller","doi":"10.1109/IEDM.2006.346848","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346848","url":null,"abstract":"The authors present for the first time the full integration scheme and 512Mb product data for a trench DRAM technology targeting the 58nm node. The key technology enablers such as an extended U-shape cell device (EUD), high performance support devices, trench capacitor with metal-insulator-silicon (MIS)/high-k dielectric and metal-in-collar (MIC), and low-k inter-level dielectric (ILD) are demonstrated","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122236133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346795
D. Ielmini, Yuegang Zhang
The conduction mechanisms in chalcogenide materials for phase-change memory (PCM) applications are studied. A trap-limited transport model for sub-threshold conduction in the amorphous chalcogenide is presented, and extended to threshold switching in the amorphous phase and transport in the highly-conductive crystalline phase, providing a fully-comprehensive, analytical model for PCMs. Finally, a PCM self-rectifying cross-point device is studied with the aid of the model, allowing to evaluate the array performance for different temperatures, read scheme and array size
{"title":"Physics-based analytical model of chalcogenide-based memories for array simulation","authors":"D. Ielmini, Yuegang Zhang","doi":"10.1109/IEDM.2006.346795","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346795","url":null,"abstract":"The conduction mechanisms in chalcogenide materials for phase-change memory (PCM) applications are studied. A trap-limited transport model for sub-threshold conduction in the amorphous chalcogenide is presented, and extended to threshold switching in the amorphous phase and transport in the highly-conductive crystalline phase, providing a fully-comprehensive, analytical model for PCMs. Finally, a PCM self-rectifying cross-point device is studied with the aid of the model, allowing to evaluate the array performance for different temperatures, read scheme and array size","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117217065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346840
N. Singh, F. Y. Lim, W. Fang, S. Rustagi, L. Bera, A. Agarwal, C. Tung, K. Hoe, S. R. Omampuliyur, D. Tripathi, A. Adeyeye, G. Lo, N. Balasubramanian, D. Kwong
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well
{"title":"Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance","authors":"N. Singh, F. Y. Lim, W. Fang, S. Rustagi, L. Bera, A. Agarwal, C. Tung, K. Hoe, S. R. Omampuliyur, D. Tripathi, A. Adeyeye, G. Lo, N. Balasubramanian, D. Kwong","doi":"10.1109/IEDM.2006.346840","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346840","url":null,"abstract":"Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122404757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346953
Yongxun Liu, T. Matsukawa, K. Endo, M. Masahara, K. Ishii, S. O'Uchi, H. Yamauchi, J. Tsukada, Y. Ishikawa, E. Suzuki
We have successfully developed the advanced FinFET fabrication processes for materializing FinFET CMOS circuits. Using the developed technologies, we demonstrate the advanced TiN metal gate, fin-height controlled FinFET CMOS inverter with an excellent transfer performance, and the flexible threshold voltage, asymmetric gate insulator thickness four-terminal (4T) FinFET with a greatly improved subthreshold (S) slope, for the first time
{"title":"Advanced FinFET CMOS Technology: TiN-Gate, Fin-Height Control and Asymmetric Gate Insulator Thickness 4T-FinFETs","authors":"Yongxun Liu, T. Matsukawa, K. Endo, M. Masahara, K. Ishii, S. O'Uchi, H. Yamauchi, J. Tsukada, Y. Ishikawa, E. Suzuki","doi":"10.1109/IEDM.2006.346953","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346953","url":null,"abstract":"We have successfully developed the advanced FinFET fabrication processes for materializing FinFET CMOS circuits. Using the developed technologies, we demonstrate the advanced TiN metal gate, fin-height controlled FinFET CMOS inverter with an excellent transfer performance, and the flexible threshold voltage, asymmetric gate insulator thickness four-terminal (4T) FinFET with a greatly improved subthreshold (S) slope, for the first time","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127928263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346865
F. Andrieu, O. Faynot, X. Garros, D. Lafond, C. Buj-Dufournet, L. Tosti, S. Minoret, V. Vidal, J. Barbe, F. Allain, E. Rouchouze, L. Vandroux, V. Cosnier, M. Cassé, V. Delaye, C. Carabasse, M. Burdin, G. Rolland, B. Guillaumot, J. Colonna, P. Besson, L. Brevard, D. Mariolle, P. Holliger, A. Vandooren, C. Fenouillet-Béranger, F. Martin, S. Deleonibus
This paper compares, for the first time, the scalability of physical- and chemical-vapor-deposited (PVD and CVD) TiN on HfO2 as a gate stack for FDSOI cMOSFETs down to 25nm gate length and width. It is shown that not only the intrinsic material properties but also the device architecture strongly influences the final gate stack properties. Reliability issues, stress and gate control in the sub-35nm scale are reported and explained, thanks to material, electric data and mechanical simulations. In spite of its lower performance on large device dimensions, PVD-TiN demonstrates a better overall trade-off, leading to a 17% ion improvement on 25nm short and narrow devices
{"title":"Comparative Scalability of PVD and CVD TiN on HfO2 as a Metal Gate Stack for FDSOI cMOSFETs down to 25nm Gate Length and Width","authors":"F. Andrieu, O. Faynot, X. Garros, D. Lafond, C. Buj-Dufournet, L. Tosti, S. Minoret, V. Vidal, J. Barbe, F. Allain, E. Rouchouze, L. Vandroux, V. Cosnier, M. Cassé, V. Delaye, C. Carabasse, M. Burdin, G. Rolland, B. Guillaumot, J. Colonna, P. Besson, L. Brevard, D. Mariolle, P. Holliger, A. Vandooren, C. Fenouillet-Béranger, F. Martin, S. Deleonibus","doi":"10.1109/IEDM.2006.346865","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346865","url":null,"abstract":"This paper compares, for the first time, the scalability of physical- and chemical-vapor-deposited (PVD and CVD) TiN on HfO2 as a gate stack for FDSOI cMOSFETs down to 25nm gate length and width. It is shown that not only the intrinsic material properties but also the device architecture strongly influences the final gate stack properties. Reliability issues, stress and gate control in the sub-35nm scale are reported and explained, thanks to material, electric data and mechanical simulations. In spite of its lower performance on large device dimensions, PVD-TiN demonstrates a better overall trade-off, leading to a 17% ion improvement on 25nm short and narrow devices","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121244847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/IEDM.2006.346942
S. Eminente, N. Barin, P. Palestri, C. Fiegna, E. Sangiorgi
A state of the art Monte-Carlo simulator is applied to the investigation of the RF performance of bulk MOSFETs designed according to the prescriptions of the 2005 ITRS Roadmap for analog and mixed signal applications, and of a 53 nm ultra-thin-body (UTB) single-gate (SG) SOI MOSFET. We provide an analysis of the signal-delay build-up along the channel and an investigation of the scaling properties of the parameters of the AC equivalent circuit, the transition frequency FT, and the 3dB bandwidth of the voltage gain in common-source configuration. The effects of ballistic transport and their impact on the AC figures of merit are investigated for short UTB double-gate MOSFETs
根据2005年ITRS路线图的规定设计的用于模拟和混合信号应用的块体MOSFET，以及53 nm超薄体(UTB)单门(SG) SOI MOSFET，应用最先进的蒙特卡罗模拟器来研究射频性能。我们分析了沿通道累积的信号延迟，并研究了交流等效电路参数、过渡频率FT和共源配置下电压增益的3dB带宽的缩放特性。研究了短UTB双栅mosfet的弹道输运效应及其对交流性能因数的影响
{"title":"Monte Carlo Simulation of deca-nanometer MOSFETs for Analog/Mixed-signal and RF applications","authors":"S. Eminente, N. Barin, P. Palestri, C. Fiegna, E. Sangiorgi","doi":"10.1109/IEDM.2006.346942","DOIUrl":"https://doi.org/10.1109/IEDM.2006.346942","url":null,"abstract":"A state of the art Monte-Carlo simulator is applied to the investigation of the RF performance of bulk MOSFETs designed according to the prescriptions of the 2005 ITRS Roadmap for analog and mixed signal applications, and of a 53 nm ultra-thin-body (UTB) single-gate (SG) SOI MOSFET. We provide an analysis of the signal-delay build-up along the channel and an investigation of the scaling properties of the parameters of the AC equivalent circuit, the transition frequency FT, and the 3dB bandwidth of the voltage gain in common-source configuration. The effects of ballistic transport and their impact on the AC figures of merit are investigated for short UTB double-gate MOSFETs","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121387290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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