Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450424
F. Rezaei, S. J. Azhari
This paper presents an ultra low-voltage, rail-to-rail input/output stage Operational Transconductance Amplifier (OTA) which uses quasi floating gate input transistors. This OTA works with ±0.3v and consumes 57µw. It has near zero variation in small/large-signal behavior (i.e. transconductance and slew rate) in whole range of the common mode voltage of input signals. Using source degeneration technique for linearity improvement, make it possible to obtain −42.7 dB, HD3 for 0.6vP-P sine wave input signal with the frequency of 1MHz. The used feedback amplifier in input stage also enhances common mode rejection ratio (CMRR), such that in DC, CMRR is 146 dB. OTA is used for implementation of a wide-tunable third-order elliptic filter with 237 KHz–2.18 MHz cutoff frequencies. Proposed OTA and filter have been simulated in 0.18µm TSMC CMOS technology with Hspice.
{"title":"Ultra low-voltage, rail-to-rail input/output stage Operational Transconductance Amplifier (OTA) with high linearity and its application in a Gm-C filter","authors":"F. Rezaei, S. J. Azhari","doi":"10.1109/ISQED.2010.5450424","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450424","url":null,"abstract":"This paper presents an ultra low-voltage, rail-to-rail input/output stage Operational Transconductance Amplifier (OTA) which uses quasi floating gate input transistors. This OTA works with ±0.3v and consumes 57µw. It has near zero variation in small/large-signal behavior (i.e. transconductance and slew rate) in whole range of the common mode voltage of input signals. Using source degeneration technique for linearity improvement, make it possible to obtain −42.7 dB, HD3 for 0.6vP-P sine wave input signal with the frequency of 1MHz. The used feedback amplifier in input stage also enhances common mode rejection ratio (CMRR), such that in DC, CMRR is 146 dB. OTA is used for implementation of a wide-tunable third-order elliptic filter with 237 KHz–2.18 MHz cutoff frequencies. Proposed OTA and filter have been simulated in 0.18µm TSMC CMOS technology with Hspice.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126038691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450404
M. Kandala, R. Sekar, Chenglong Zhang, Haibo Wang
This paper presents a novel design of low power charge redistribution successive approximation analog to digital converter(CR-SAR ADC). During its conversion, the voltage swing of the capacitor array is reduced to half of the voltage reference without decreasing the ADC dynamic range. The reduced voltage swing results in a significant reduction of ADC power consumption. Also, the proposed design requires only half of the total capacitance that is used in a traditional CR-SAR ADC with the same resolution. MATLAB simulations are performed to compare the power consumption due to charging the capacitor array in the proposed and previous low power CR-SAR ADC'S. The proposed circuit is implemented using a 0.13µ CMOS technology. Post-layout simulation shows that the proposed converter consumes 63% less energy compared to a traditional CR-SAR ADC.
{"title":"A low power charge-redistribution ADC with reduced capacitor array","authors":"M. Kandala, R. Sekar, Chenglong Zhang, Haibo Wang","doi":"10.1109/ISQED.2010.5450404","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450404","url":null,"abstract":"This paper presents a novel design of low power charge redistribution successive approximation analog to digital converter(CR-SAR ADC). During its conversion, the voltage swing of the capacitor array is reduced to half of the voltage reference without decreasing the ADC dynamic range. The reduced voltage swing results in a significant reduction of ADC power consumption. Also, the proposed design requires only half of the total capacitance that is used in a traditional CR-SAR ADC with the same resolution. MATLAB simulations are performed to compare the power consumption due to charging the capacitor array in the proposed and previous low power CR-SAR ADC'S. The proposed circuit is implemented using a 0.13µ CMOS technology. Post-layout simulation shows that the proposed converter consumes 63% less energy compared to a traditional CR-SAR ADC.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122217390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450548
Shengquan Wang, Jian-Jia Chen
As the power density of modern electronic circuits increases dramatically, systems are prone to overheating. High temperatures not only raise packaging costs, degrade system performance, and increase leakage power consumption, but also reduce the system reliability. Due to many limits in single core design including the performance and the power density, the microprocessor industry has switched their attentions to multicore design to enable the scaling of performance. Thermal effects on multicore systems are still prominent issues. One typical thermal effect is the thermal-aware lifetime reliability, which has become a serious concern. In this paper, we address the issue on how to maximize the lifetime of multicore systems while maintaining a given aggregate processor speed. By applying sequential quadratic programming, we present how to derive the ideal speed for each core to maximize the system lifetime. We perform experiments on several multi-core platforms, which show that the proposed method can significantly outperform the existing approaches by minimizing the peak temperature of the system.
{"title":"Thermal-aware lifetime reliability in multicore systems","authors":"Shengquan Wang, Jian-Jia Chen","doi":"10.1109/ISQED.2010.5450548","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450548","url":null,"abstract":"As the power density of modern electronic circuits increases dramatically, systems are prone to overheating. High temperatures not only raise packaging costs, degrade system performance, and increase leakage power consumption, but also reduce the system reliability. Due to many limits in single core design including the performance and the power density, the microprocessor industry has switched their attentions to multicore design to enable the scaling of performance. Thermal effects on multicore systems are still prominent issues. One typical thermal effect is the thermal-aware lifetime reliability, which has become a serious concern. In this paper, we address the issue on how to maximize the lifetime of multicore systems while maintaining a given aggregate processor speed. By applying sequential quadratic programming, we present how to derive the ideal speed for each core to maximize the system lifetime. We perform experiments on several multi-core platforms, which show that the proposed method can significantly outperform the existing approaches by minimizing the peak temperature of the system.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125432433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450398
Minseok Kang, Taewhan Kim
This work addresses the problem of minimizing power/ground noise with an important design parameter, which is the delay variations on the clock tree. Without considering the effect of delay variations on the polarity assignment, the resulting statistical clock skew may lead to a high probability of skew violation, which causes a low yield of design. Given distributions on the delay of each type of buffering elements and the interconnect delay from the clock source to every flip-flop with spatial delay correlations, and the clock skew and yield constraints, we solve the problem of assigning polarity to each sink buffer (i.e., assigning a buffering type) so that the power/ground noise is minimized while satisfying the yield and clock skew constraints. Specifically, we solve the problem in two steps where in step 1, for each pair of sinks a set of feasible combination(s) of polarities to the sinks that do not violate the yield constraint as well as the clock skew constraint is extracted, and in step 2, a stepwise greedy method is applied to determine the polarities to sinks from the feasible sets obtained in step 1 to minimize the power/ground noise. Through experiments with ISCAS89 benchmark circuits, it is shown that our proposed approach is able to improve yield by 6.7% on average even with 4.3% less power and 4.4% less ground noises over the results by the conventional polarity assignment approach which does not consider the delay variations.
{"title":"Clock buffer polarity assignment considering the effect of delay variations","authors":"Minseok Kang, Taewhan Kim","doi":"10.1109/ISQED.2010.5450398","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450398","url":null,"abstract":"This work addresses the problem of minimizing power/ground noise with an important design parameter, which is the delay variations on the clock tree. Without considering the effect of delay variations on the polarity assignment, the resulting statistical clock skew may lead to a high probability of skew violation, which causes a low yield of design. Given distributions on the delay of each type of buffering elements and the interconnect delay from the clock source to every flip-flop with spatial delay correlations, and the clock skew and yield constraints, we solve the problem of assigning polarity to each sink buffer (i.e., assigning a buffering type) so that the power/ground noise is minimized while satisfying the yield and clock skew constraints. Specifically, we solve the problem in two steps where in step 1, for each pair of sinks a set of feasible combination(s) of polarities to the sinks that do not violate the yield constraint as well as the clock skew constraint is extracted, and in step 2, a stepwise greedy method is applied to determine the polarities to sinks from the feasible sets obtained in step 1 to minimize the power/ground noise. Through experiments with ISCAS89 benchmark circuits, it is shown that our proposed approach is able to improve yield by 6.7% on average even with 4.3% less power and 4.4% less ground noises over the results by the conventional polarity assignment approach which does not consider the delay variations.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130200857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450495
A. Aguiar, S. J. Filho, F. Magalhães, Thiago D. Casagrande, Fabiano Hessel
Hellfire framework (HellfireFW) presents a design flow for the design of MPSoC based critical embedded systems. Health-care electronics, security equipment and space aircraft are examples of such systems that, besides presenting typical embedded system's constraints, bring new design challenges as their restrictions are even tighter in terms of area, power consumption and high-performance in distributed computing involving real-time processing requirement. In this paper, we present the Hellfire framework, which offers an integrated tool-flow in which design space exploration (DSE), OS customization and static and dynamic application mapping are highly automated. The designer can develop embedded sequential and parallel applications while evaluating how design decisions impact in overall system behavior, in terms of static and dynamic task mapping, performance, deadline miss ratio, communication traffic and energy consumption. Results show that: i) our solution is suitable for hard real-time critical embedded systems, in terms of real-time scheduling and OS overhead; ii) an accurate analysis of critical embedded applications in terms of deadline miss ratio can be done using HellfireFW; iii) designer can better decide which architecture is more suitable for the application; iv) different HW/SW solutions by configuring both the RTOS and the HW platform can be simulated.
{"title":"Hellfire: A design framework for critical embedded systems' applications","authors":"A. Aguiar, S. J. Filho, F. Magalhães, Thiago D. Casagrande, Fabiano Hessel","doi":"10.1109/ISQED.2010.5450495","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450495","url":null,"abstract":"Hellfire framework (HellfireFW) presents a design flow for the design of MPSoC based critical embedded systems. Health-care electronics, security equipment and space aircraft are examples of such systems that, besides presenting typical embedded system's constraints, bring new design challenges as their restrictions are even tighter in terms of area, power consumption and high-performance in distributed computing involving real-time processing requirement. In this paper, we present the Hellfire framework, which offers an integrated tool-flow in which design space exploration (DSE), OS customization and static and dynamic application mapping are highly automated. The designer can develop embedded sequential and parallel applications while evaluating how design decisions impact in overall system behavior, in terms of static and dynamic task mapping, performance, deadline miss ratio, communication traffic and energy consumption. Results show that: i) our solution is suitable for hard real-time critical embedded systems, in terms of real-time scheduling and OS overhead; ii) an accurate analysis of critical embedded applications in terms of deadline miss ratio can be done using HellfireFW; iii) designer can better decide which architecture is more suitable for the application; iv) different HW/SW solutions by configuring both the RTOS and the HW platform can be simulated.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129685761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450536
F. Moradi, D. Wisland, H. Mahmoodi, Y. Berg, T. Cao
A new SRAM design is proposed. Body biasing improves the static noise margin (SNM) improved by at least 15% compared to the standard cells. Through using this technique, lowering supply voltage is possible. This SRAM cell is working under 0.3V supply voltage offering a SNM improvement of 22% for the read cycle. Write Margin is not affected due to using body biasing technique. 65nm ST models are used for simulations.
{"title":"New SRAM design using body bias technique for ultra low power applications","authors":"F. Moradi, D. Wisland, H. Mahmoodi, Y. Berg, T. Cao","doi":"10.1109/ISQED.2010.5450536","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450536","url":null,"abstract":"A new SRAM design is proposed. Body biasing improves the static noise margin (SNM) improved by at least 15% compared to the standard cells. Through using this technique, lowering supply voltage is possible. This SRAM cell is working under 0.3V supply voltage offering a SNM improvement of 22% for the read cycle. Write Margin is not affected due to using body biasing technique. 65nm ST models are used for simulations.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129214380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450481
Syed M. A. H. Jafri, S. Piestrak, O. Sentieys, S. Pillement
This paper considers the possibility of implementing low-cost hardware techniques which would allow to tolerate temporary faults in the datapaths of coarse-grained reconfigurable architectures (CGRAs). Our goal was to use less hardware overhead than commonly used duplication or triplication methods. The proposed technique relies on concurrent error detection by using residue code modulo 3 and re-execution of the last operation, once an error is detected. We have chosen the DART architecture as a vehicle to study the efficiency of this approach to protect its datapaths. Simulation results have confirmed hardware savings of the proposed approach over duplication.
{"title":"Design of a fault-tolerant coarse-grained","authors":"Syed M. A. H. Jafri, S. Piestrak, O. Sentieys, S. Pillement","doi":"10.1109/ISQED.2010.5450481","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450481","url":null,"abstract":"This paper considers the possibility of implementing low-cost hardware techniques which would allow to tolerate temporary faults in the datapaths of coarse-grained reconfigurable architectures (CGRAs). Our goal was to use less hardware overhead than commonly used duplication or triplication methods. The proposed technique relies on concurrent error detection by using residue code modulo 3 and re-execution of the last operation, once an error is detected. We have chosen the DART architecture as a vehicle to study the efficiency of this approach to protect its datapaths. Simulation results have confirmed hardware savings of the proposed approach over duplication.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115597351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450403
Srikanth V. Devarapalli, P. Zarkesh-Ha, S. Suddarth
To maintain the performance of digital systems, while reducing the energy consumption, implementation of dual edge flip flops has recently become the focus of many researchers. This paper presents a new robust and low power dual edge flip-flop using c-elements. Unlike the existing dual data rate (DDR) flip flops [1–4], the proposed circuit uses the direct clock pulses to latch the data, without a need for additional pulse generator circuitry for the clock signal, which lowers the clock dynamic power consumption by factor of 2x. Moreover, because of its simplicity with very low transistor count, it provides a more robust solution for DDR flip-flops. In comparison with ep-DSFF (explicit-pulsed static hybrid flop) [1] at 45nm CMOS process, the proposed DDR-FF consumes 32% less power, with 12% less C2Q delay. The power-delay product of the proposed DDR-FF is 41% better than its counterpart, ep-DSFF. The proposed DDR-FF uses only 24 transistors and can easily be implemented into the cell libraries for high performance and low power ASIC design flow.
{"title":"A robust and low power dual data rate (DDR) flip-flop using c-elements","authors":"Srikanth V. Devarapalli, P. Zarkesh-Ha, S. Suddarth","doi":"10.1109/ISQED.2010.5450403","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450403","url":null,"abstract":"To maintain the performance of digital systems, while reducing the energy consumption, implementation of dual edge flip flops has recently become the focus of many researchers. This paper presents a new robust and low power dual edge flip-flop using c-elements. Unlike the existing dual data rate (DDR) flip flops [1–4], the proposed circuit uses the direct clock pulses to latch the data, without a need for additional pulse generator circuitry for the clock signal, which lowers the clock dynamic power consumption by factor of 2x. Moreover, because of its simplicity with very low transistor count, it provides a more robust solution for DDR flip-flops. In comparison with ep-DSFF (explicit-pulsed static hybrid flop) [1] at 45nm CMOS process, the proposed DDR-FF consumes 32% less power, with 12% less C2Q delay. The power-delay product of the proposed DDR-FF is 41% better than its counterpart, ep-DSFF. The proposed DDR-FF uses only 24 transistors and can easily be implemented into the cell libraries for high performance and low power ASIC design flow.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"458 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115615510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450528
Siong Kiong Teng, N. Soin
Clock gating technique had become one of the major dynamic power saving approaches in today low power digital circuit design. In this paper, we present a new physical clock gates optimization technique using splitting and merging algorithm that works on both single level and multiple levels clock gating design. The algorithm is built on top of the standard EDA flow by running two passes clock tree synthesis. The first pass is to obtain the clock buffer location for clock gate swapping and the second pass will build the clock tree based on the optimum clock gate location. The merging algorithm will then be used to improve the overall clock tree power. The results on the industrial design show the improvement on overall clock tree power using aforementioned algorithm.
{"title":"Low power clock gates optimization for clock tree distribution","authors":"Siong Kiong Teng, N. Soin","doi":"10.1109/ISQED.2010.5450528","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450528","url":null,"abstract":"Clock gating technique had become one of the major dynamic power saving approaches in today low power digital circuit design. In this paper, we present a new physical clock gates optimization technique using splitting and merging algorithm that works on both single level and multiple levels clock gating design. The algorithm is built on top of the standard EDA flow by running two passes clock tree synthesis. The first pass is to obtain the clock buffer location for clock gate swapping and the second pass will build the clock tree based on the optimum clock gate location. The merging algorithm will then be used to improve the overall clock tree power. The results on the industrial design show the improvement on overall clock tree power using aforementioned algorithm.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114270857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450464
Jae-Young Park, Jong-Kyu Song, Chang-Soo Jang, Young-Sang Son, Dae-Woo Kim
The analysis and the modeling of a Low Voltage Triggered SCR (Silicon Controlled Rectifier) under vf-TLP (very-fast Transmission Line Pulse) measurements are reported. The results measured by vf-TLP system showed that the triggering voltage (Vt1) decreased and the second breakdown current (It2) increased in the comparison with the results measured by a standard 100ns TLP (Transmission Line Pulse) system. A compact model based on the vf-TLP measured characteristics is presented. The measurement result and the simulation data of the behavior approached model indicate a good correlation.
{"title":"Analysis and modeling of a Low Voltage Triggered SCR ESD protection clamp with the very fast Transmission Line Pulse measurement","authors":"Jae-Young Park, Jong-Kyu Song, Chang-Soo Jang, Young-Sang Son, Dae-Woo Kim","doi":"10.1109/ISQED.2010.5450464","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450464","url":null,"abstract":"The analysis and the modeling of a Low Voltage Triggered SCR (Silicon Controlled Rectifier) under vf-TLP (very-fast Transmission Line Pulse) measurements are reported. The results measured by vf-TLP system showed that the triggering voltage (Vt1) decreased and the second breakdown current (It2) increased in the comparison with the results measured by a standard 100ns TLP (Transmission Line Pulse) system. A compact model based on the vf-TLP measured characteristics is presented. The measurement result and the simulation data of the behavior approached model indicate a good correlation.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122779056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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