Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450446
E. Yilmaz
Unreasonably long test time and test cost forces the utilization of test compaction methods in production line. Test compaction methods reduce the test cost at the expense of degrading the test quality. When test compaction is used, it is essential to estimate the resulting test quality. Traditional Monte-Carlo simulation devotes most of the effort sampling the median region of the process parameters. However, defective escapes are generally marginal and accurate estimation of defective parts per million (DPPM) requires extensive simulation, especially when DPPM level is low. In this work, we aim at reducing the number of simulations required to estimate DPPM accurately through a two-step methodology exploiting the layered structure of process variation. In the first step, we generate an essential experiment set using a modified version of Taguchi's design of experiment method. We optimize this experiment set for accuracy in order to get a minimal set of experiments. In the second step, we emulate the low level process variation on the optimized essential experiment set. Instead of using traditional Monte-Carlo sampling method, employing layered sampling of process parameters enable us to achieve an accurate DPPMvalue for a substantially reduced number of simulations.
{"title":"Accurate multi-specification DPPM estimation using layered sampling based simulation","authors":"E. Yilmaz","doi":"10.1109/ISQED.2010.5450446","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450446","url":null,"abstract":"Unreasonably long test time and test cost forces the utilization of test compaction methods in production line. Test compaction methods reduce the test cost at the expense of degrading the test quality. When test compaction is used, it is essential to estimate the resulting test quality. Traditional Monte-Carlo simulation devotes most of the effort sampling the median region of the process parameters. However, defective escapes are generally marginal and accurate estimation of defective parts per million (DPPM) requires extensive simulation, especially when DPPM level is low. In this work, we aim at reducing the number of simulations required to estimate DPPM accurately through a two-step methodology exploiting the layered structure of process variation. In the first step, we generate an essential experiment set using a modified version of Taguchi's design of experiment method. We optimize this experiment set for accuracy in order to get a minimal set of experiments. In the second step, we emulate the low level process variation on the optimized essential experiment set. Instead of using traditional Monte-Carlo sampling method, employing layered sampling of process parameters enable us to achieve an accurate DPPMvalue for a substantially reduced number of simulations.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116200622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450400
Satyanand Nalam, V. Chandra, C. Pietrzyk, R. Aitken, B. Calhoun
This paper describes an asymmetric single-ended 6T SRAM bitcell that improves both Read Static Noise Margin (RSNM) and Write Noise Margin (WNM) for the same bitcell area as a conventional symmetric 6T. This improvement is achieved using a single VDD, without employing assist techniques that require multiple voltages. The improvement in noise margins significantly improves the low-voltage robustness and consequently the minimum operating voltage of the SRAM (VMIN). Single-ended write is accomplished in two phases using dual word-lines. Finally, we propose a differential sensing scheme using a weak reference cell to read the single-ended 6T. A combination of reduced bitline capacitance and increased drive current ensure read delay comparable to conventional differential sensing, for the same bitcell area.
{"title":"Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation","authors":"Satyanand Nalam, V. Chandra, C. Pietrzyk, R. Aitken, B. Calhoun","doi":"10.1109/ISQED.2010.5450400","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450400","url":null,"abstract":"This paper describes an asymmetric single-ended 6T SRAM bitcell that improves both Read Static Noise Margin (RSNM) and Write Noise Margin (WNM) for the same bitcell area as a conventional symmetric 6T. This improvement is achieved using a single VDD, without employing assist techniques that require multiple voltages. The improvement in noise margins significantly improves the low-voltage robustness and consequently the minimum operating voltage of the SRAM (VMIN). Single-ended write is accomplished in two phases using dual word-lines. Finally, we propose a differential sensing scheme using a weak reference cell to read the single-ended 6T. A combination of reduced bitline capacitance and increased drive current ensure read delay comparable to conventional differential sensing, for the same bitcell area.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124872292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450505
Göran Jerke, J. Lienig
Excessive current density within interconnects is a major concern for IC designers, which if not effectively mitigated leads to electromigration and electrical overstress. This is increasingly a problem in modern ICs due to smaller feature sizes and higher currents associated with lower supply voltages. Detailed analysis of all interconnect nets is both time-consuming and cannot be done until physical design is complete, when it is too late for easy fixes. To address these problems, we introduce (i) a powerful terminal current model and (ii) an efficient methodology to determine the worst-case bounds on segment currents of the interconnect. This early-stage calculation enables nets to be separated into critical and non-critical sets; only the set of critical nets, which is typically considerably smaller, requires subsequent special consideration during physical design and layout verification due to current density design limits. The presented algorithms are fast enough to run on every net, and work with known and unknown net topology, leading to several practical uses, such as (i) the pre-layout identification of nets that are potentially troublesome and may need sizing, (ii) as filter to avoid time-consuming detailed current-density analysis of net layouts, and (iii) to evaluate the effect of interconnect temperature and process changes on the number and distribution of current-density-critical nets.
{"title":"Early-stage determination of current-density criticality in interconnects","authors":"Göran Jerke, J. Lienig","doi":"10.1109/ISQED.2010.5450505","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450505","url":null,"abstract":"Excessive current density within interconnects is a major concern for IC designers, which if not effectively mitigated leads to electromigration and electrical overstress. This is increasingly a problem in modern ICs due to smaller feature sizes and higher currents associated with lower supply voltages. Detailed analysis of all interconnect nets is both time-consuming and cannot be done until physical design is complete, when it is too late for easy fixes. To address these problems, we introduce (i) a powerful terminal current model and (ii) an efficient methodology to determine the worst-case bounds on segment currents of the interconnect. This early-stage calculation enables nets to be separated into critical and non-critical sets; only the set of critical nets, which is typically considerably smaller, requires subsequent special consideration during physical design and layout verification due to current density design limits. The presented algorithms are fast enough to run on every net, and work with known and unknown net topology, leading to several practical uses, such as (i) the pre-layout identification of nets that are potentially troublesome and may need sizing, (ii) as filter to avoid time-consuming detailed current-density analysis of net layouts, and (iii) to evaluate the effect of interconnect temperature and process changes on the number and distribution of current-density-critical nets.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122080371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450525
Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee
As the IC fabrication technology gets into the nanometer era, antenna effect plays an important role in determining the yield and reliability of VLSI circuits. This work proposes a discharge-path-based antenna effect detection method. Based on the proposed detection method, two novel jumper insertion and layer assignment algorithms are presented for fixing antenna violations. Additionally, via delay is considered in delay calculation, and wire sizing technique is applied for clock skew compensation. Given an X-architecture clock tree with n clock sinks, layer configuration, and the upper bound for antenna effect, the proposed PADJILA algorithm runs in O(n2) to achieve antenna violation free. Experimental results on benchmarks show that our work significantly outperforms than the existing works.
{"title":"Antenna Violation Avoidance/Fixing for X-clock routing","authors":"Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee","doi":"10.1109/ISQED.2010.5450525","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450525","url":null,"abstract":"As the IC fabrication technology gets into the nanometer era, antenna effect plays an important role in determining the yield and reliability of VLSI circuits. This work proposes a discharge-path-based antenna effect detection method. Based on the proposed detection method, two novel jumper insertion and layer assignment algorithms are presented for fixing antenna violations. Additionally, via delay is considered in delay calculation, and wire sizing technique is applied for clock skew compensation. Given an X-architecture clock tree with n clock sinks, layer configuration, and the upper bound for antenna effect, the proposed PADJILA algorithm runs in O(n2) to achieve antenna violation free. Experimental results on benchmarks show that our work significantly outperforms than the existing works.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122127524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450537
K. Monfaredi, H. F. Baghtash, S. J. Azhari
In this paper a novel high output impedance, low input impedance, wide bandwidth, very simple mirror/source structure with input and output voltage requirements less than that of a simple current mirror is presented. It can be also used as variable negative impedance converter (variable-NIC) by modifying amplifier transistors' aspect ratios. The circuit's principle of operation is discussed and compared to simple and low voltage cascode (LVC) current mirrors. Working with power supplies less than 1volt, the proposed circuit provides output impedance greater than LVC current mirror. Such outstanding features of this current mirror as high output impedance∼25.3M, low input impedance∼44, wide bandwidth∼498MHz, low input voltage ∼ 415mV, low output voltage ∼ 149mV and low current transfer error ∼1.3% (all at 10µA) makes it an outstanding choice for high performance applications. Simulation results in BSIM 0.35µm CMOS technology with Hspice are given in comparison with simple, and LVC current mirrors to verify and validate the performance of the proposed current mirror/NIC.
{"title":"A novel low voltage current compensated high performance current mirror/NIC","authors":"K. Monfaredi, H. F. Baghtash, S. J. Azhari","doi":"10.1109/ISQED.2010.5450537","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450537","url":null,"abstract":"In this paper a novel high output impedance, low input impedance, wide bandwidth, very simple mirror/source structure with input and output voltage requirements less than that of a simple current mirror is presented. It can be also used as variable negative impedance converter (variable-NIC) by modifying amplifier transistors' aspect ratios. The circuit's principle of operation is discussed and compared to simple and low voltage cascode (LVC) current mirrors. Working with power supplies less than 1volt, the proposed circuit provides output impedance greater than LVC current mirror. Such outstanding features of this current mirror as high output impedance∼25.3M, low input impedance∼44, wide bandwidth∼498MHz, low input voltage ∼ 415mV, low output voltage ∼ 149mV and low current transfer error ∼1.3% (all at 10µA) makes it an outstanding choice for high performance applications. Simulation results in BSIM 0.35µm CMOS technology with Hspice are given in comparison with simple, and LVC current mirrors to verify and validate the performance of the proposed current mirror/NIC.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122734371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450547
Shaobo Liu, Jingyi Zhang, Qing Wu, Qinru Qiu
In this paper, we propose a thermal-aware job allocation and scheduling algorithm for three-dimensional (3D) chip multiprocessor (CMP). The proposed algorithm assigns hot jobs to the cores close to the heat sink and cool jobs to the cores far from the heat sink, subject to thermal constraints. The direct effect of the proposed algorithm on a 3D-CMP system is that, the heat from hot jobs is removed off the chip faster than the temperature-aware methods. Therefore we are able to keep the chip cooler and in better thermal condition. Experimental results show that, comparing to the temperature-aware method, our algorithm achieves: 1) less hot spots; 2) better performance; 3) smaller temporal temperature variation; 4) lower peak temperature. The proposed algorithm reduces hot spots by more than 95% when workload contains cool jobs; and by 36% when workload does not contain cool jobs. It also boosts the system performance by 5% on average under various workloads. The temporal temperature variation is reduced by 60% and its standard deviation is decreased by 50%. In addition, the proposed algorithm achieves 1.8°C ∼5°C reduction in peak temperature.
{"title":"Thermal-aware job allocation and scheduling for three dimensional chip multiprocessor","authors":"Shaobo Liu, Jingyi Zhang, Qing Wu, Qinru Qiu","doi":"10.1109/ISQED.2010.5450547","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450547","url":null,"abstract":"In this paper, we propose a thermal-aware job allocation and scheduling algorithm for three-dimensional (3D) chip multiprocessor (CMP). The proposed algorithm assigns hot jobs to the cores close to the heat sink and cool jobs to the cores far from the heat sink, subject to thermal constraints. The direct effect of the proposed algorithm on a 3D-CMP system is that, the heat from hot jobs is removed off the chip faster than the temperature-aware methods. Therefore we are able to keep the chip cooler and in better thermal condition. Experimental results show that, comparing to the temperature-aware method, our algorithm achieves: 1) less hot spots; 2) better performance; 3) smaller temporal temperature variation; 4) lower peak temperature. The proposed algorithm reduces hot spots by more than 95% when workload contains cool jobs; and by 36% when workload does not contain cool jobs. It also boosts the system performance by 5% on average under various workloads. The temporal temperature variation is reduced by 60% and its standard deviation is decreased by 50%. In addition, the proposed algorithm achieves 1.8°C ∼5°C reduction in peak temperature.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123813871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450415
Patrick Gibson, Ziyang Lu, F. Pikus, Sridhar Srinivasan
In this paper, we explain a new EDA tool framework that extends the reach of Electrical DFM analysis across cross-domain applications by providing the ability to do layout analysis and logical analysis of the schematics in context. To demonstrate the effectiveness and the flexibility of the integrated environment this new framework provides, we show several real-time applications of layout verification based on the logic analysis of the circuit, where the logic analysis is performed by applying the correct design rules.
{"title":"A framework for logic-aware layout analysis","authors":"Patrick Gibson, Ziyang Lu, F. Pikus, Sridhar Srinivasan","doi":"10.1109/ISQED.2010.5450415","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450415","url":null,"abstract":"In this paper, we explain a new EDA tool framework that extends the reach of Electrical DFM analysis across cross-domain applications by providing the ability to do layout analysis and logical analysis of the schematics in context. To demonstrate the effectiveness and the flexibility of the integrated environment this new framework provides, we show several real-time applications of layout verification based on the logic analysis of the circuit, where the logic analysis is performed by applying the correct design rules.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124558499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450442
J. Sartori, A. Pant, Rakesh Kumar, Puneet Gupta
Number of cores per multi-core processor die, as well as variation between the maximum operating frequency of individual cores, is rapidly increasing. This makes performance binning of multi-core processors a non-trivial task. In this paper, we study, for the first time, multi-core binning metrics and strategies to evaluate them efficiently. We discuss two multi-core binning metrics with high correlation to processor throughput for different types of workloads and different process variation scenarios. More importantly, we demonstrate the importance of leveraging variation model data in the binning process to significantly reduce the binning overhead with a negligible loss in binning quality. For example, we demonstrate that the performance binning overhead of a 64-core processor can be decreased by 51% and 36% using the proposed variation-aware core clustering and curve fitting strategies respectively. Experiments were performed using a manufacturing variation model based on real 65nm silicon data.
{"title":"Variation-aware speed binning of multi-core processors","authors":"J. Sartori, A. Pant, Rakesh Kumar, Puneet Gupta","doi":"10.1109/ISQED.2010.5450442","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450442","url":null,"abstract":"Number of cores per multi-core processor die, as well as variation between the maximum operating frequency of individual cores, is rapidly increasing. This makes performance binning of multi-core processors a non-trivial task. In this paper, we study, for the first time, multi-core binning metrics and strategies to evaluate them efficiently. We discuss two multi-core binning metrics with high correlation to processor throughput for different types of workloads and different process variation scenarios. More importantly, we demonstrate the importance of leveraging variation model data in the binning process to significantly reduce the binning overhead with a negligible loss in binning quality. For example, we demonstrate that the performance binning overhead of a 64-core processor can be decreased by 51% and 36% using the proposed variation-aware core clustering and curve fitting strategies respectively. Experiments were performed using a manufacturing variation model based on real 65nm silicon data.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131206072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450435
Chris Allsup
With each new process generation, it becomes ever more challenging to maintain high yields of integrated circuits. Progressively lower yields potentially undermine the profits of semiconductor companies across all industry segments. Embedding redundant logic into designs can improve product yields, but is this economically viable for most systems-on-chip? This paper attempts to answer this fundamental question. After describing an example architecture for built-in logic redundancy (BILR), we examine precisely how the BILR design and test parameters affect the area overhead, test execution time and yield of the redundant system. After conveying the cost model, we present analysis results showing that redundancy could be cost-effective, depending on a number of cost infrastructure variables that include the parameters of the BILR system itself.
{"title":"Is built-in logic redundancy ready for prime time?","authors":"Chris Allsup","doi":"10.1109/ISQED.2010.5450435","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450435","url":null,"abstract":"With each new process generation, it becomes ever more challenging to maintain high yields of integrated circuits. Progressively lower yields potentially undermine the profits of semiconductor companies across all industry segments. Embedding redundant logic into designs can improve product yields, but is this economically viable for most systems-on-chip? This paper attempts to answer this fundamental question. After describing an example architecture for built-in logic redundancy (BILR), we examine precisely how the BILR design and test parameters affect the area overhead, test execution time and yield of the redundant system. After conveying the cost model, we present analysis results showing that redundancy could be cost-effective, depending on a number of cost infrastructure variables that include the parameters of the BILR system itself.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"43 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120866846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450418
Kyung Ki Kim, Haiqing Nan, K. Choi
This paper presents the hot-carrier-injection (HCI)-induced delay degradation of the power gating structure as well as the HCI impact on critical issues in the power gating, such as leakage power, wake-up time, and wake-up rush-current. Considering this HCI impact, a novel adaptive HCI-aware power gating structure is proposed to compensate for the performance loss and the increased wake-up time of the power gating structures induced by the HCI effect. The proposed structure consists of variable width footers based on the two-pass power gating and a new HCI monitoring circuit, which is imperative for a good adaptive technique. The simulation results are compared to those of power gating without the adaptive technique and show that both the circuit-delay and wake-up time dependence of the power gating structure on the HCI stress is minimized with only 2% and 3% increase, respectively while keeping small leakage power and rush-current. The proposed technique is evaluated using ISCAS85 benchmark circuits which are designed using 45nm CMOS predictive technology model.
{"title":"Adaptive HCI-aware power gating structure","authors":"Kyung Ki Kim, Haiqing Nan, K. Choi","doi":"10.1109/ISQED.2010.5450418","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450418","url":null,"abstract":"This paper presents the hot-carrier-injection (HCI)-induced delay degradation of the power gating structure as well as the HCI impact on critical issues in the power gating, such as leakage power, wake-up time, and wake-up rush-current. Considering this HCI impact, a novel adaptive HCI-aware power gating structure is proposed to compensate for the performance loss and the increased wake-up time of the power gating structures induced by the HCI effect. The proposed structure consists of variable width footers based on the two-pass power gating and a new HCI monitoring circuit, which is imperative for a good adaptive technique. The simulation results are compared to those of power gating without the adaptive technique and show that both the circuit-delay and wake-up time dependence of the power gating structure on the HCI stress is minimized with only 2% and 3% increase, respectively while keeping small leakage power and rush-current. The proposed technique is evaluated using ISCAS85 benchmark circuits which are designed using 45nm CMOS predictive technology model.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116293647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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