Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450553
Saeroonter Oh, Jeongha Park, S. Wong, H. Wong
A compact model of III–V HFETs is developed for digital logic circuit applications such as a 6T-SRAM cell. We study sub-22nm technology III–V SRAM circuit design via III–V MOSFETs with thin high-k dielectric for low gate tunneling current, and optimized extrinsic structure for minimum parasitic capacitance. We investigate the drawbacks of a weak PMOS device in a SRAM cell and propose a minimum requirement for III–V PMOS strength for SRAM to be viable.
{"title":"Modeling and analysis of III–V logic FETs for devices and circuits: Sub-22nm technology III–V SRAM cell design","authors":"Saeroonter Oh, Jeongha Park, S. Wong, H. Wong","doi":"10.1109/ISQED.2010.5450553","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450553","url":null,"abstract":"A compact model of III–V HFETs is developed for digital logic circuit applications such as a 6T-SRAM cell. We study sub-22nm technology III–V SRAM circuit design via III–V MOSFETs with thin high-k dielectric for low gate tunneling current, and optimized extrinsic structure for minimum parasitic capacitance. We investigate the drawbacks of a weak PMOS device in a SRAM cell and propose a minimum requirement for III–V PMOS strength for SRAM to be viable.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"4 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131436725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450450
Johnny J. W. Kuan, S. Wilton, Tor M. Aamodt
Post-silicon debug comprises a significant and highly variable fraction of the total development time for large chip designs. To accelerate post-silicon debug, BackSpace [1, 2] employs on-chip monitoring circuitry and off-chip formal analysis to provide a trace of states that lead up to a crash state. BackSpace employs repeated runs of the integrated circuit being debugged, which can be time consuming. This paper shows that correlation information characterizing the application running on the hardware up to the crash state can reduce the number of runs of the chip by up to 51%.
{"title":"Accelerating trace computation in post-silicon debug","authors":"Johnny J. W. Kuan, S. Wilton, Tor M. Aamodt","doi":"10.1109/ISQED.2010.5450450","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450450","url":null,"abstract":"Post-silicon debug comprises a significant and highly variable fraction of the total development time for large chip designs. To accelerate post-silicon debug, BackSpace [1, 2] employs on-chip monitoring circuitry and off-chip formal analysis to provide a trace of states that lead up to a crash state. BackSpace employs repeated runs of the integrated circuit being debugged, which can be time consuming. This paper shows that correlation information characterizing the application running on the hardware up to the crash state can reduce the number of runs of the chip by up to 51%.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114384968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450532
N. Srimal
This paper describes methodologies developed to ensure circuit robustness and silicon quality when a high performance microprocessor design is proliferated across process revisions. The paper describes innovative techniques and solutions based on data obtained from post silicon experiments and simulations that can be advantageous to the designers. The paper focuses on the areas of leakage control, noise tolerance, min-delay analysis.
{"title":"Methodology to ensure circuit robustness and exceptional silicon quality while proliferating designs across process revisions with high productivity","authors":"N. Srimal","doi":"10.1109/ISQED.2010.5450532","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450532","url":null,"abstract":"This paper describes methodologies developed to ensure circuit robustness and silicon quality when a high performance microprocessor design is proliferated across process revisions. The paper describes innovative techniques and solutions based on data obtained from post silicon experiments and simulations that can be advantageous to the designers. The paper focuses on the areas of leakage control, noise tolerance, min-delay analysis.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124428984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450496
B. Meyer, Adam S. Hartman, D. E. Thomas
Yield losses due to a combination of random, systematic and parametric defects are rising as manufacturing processes scale to smaller features sizes. In embedded systems-on-chip, yield can be increased using slack—under-utilization in execution and storage resources—so that when components are defective, data and tasks can be re-mapped and re-scheduled. For any given system, the design space of possible slack allocations is both large and complex, consisting of every possible way to replace each component in the initial system with another from the component library. However, based on the observation that useful slack is often quantized, we have developed an approach that effectively and efficiently allocates execution and storage slack to jointly optimize system yield and cost. While exploring less than 1.62% of the slack allocation design space, our approach consistently outperforms alternative slack allocation techniques to find sets of designs within 4.27% of the yield-cost Pareto-optimal front.
{"title":"Slack allocation for yield improvement in NoC-based MPSoCs","authors":"B. Meyer, Adam S. Hartman, D. E. Thomas","doi":"10.1109/ISQED.2010.5450496","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450496","url":null,"abstract":"Yield losses due to a combination of random, systematic and parametric defects are rising as manufacturing processes scale to smaller features sizes. In embedded systems-on-chip, yield can be increased using slack—under-utilization in execution and storage resources—so that when components are defective, data and tasks can be re-mapped and re-scheduled. For any given system, the design space of possible slack allocations is both large and complex, consisting of every possible way to replace each component in the initial system with another from the component library. However, based on the observation that useful slack is often quantized, we have developed an approach that effectively and efficiently allocates execution and storage slack to jointly optimize system yield and cost. While exploring less than 1.62% of the slack allocation design space, our approach consistently outperforms alternative slack allocation techniques to find sets of designs within 4.27% of the yield-cost Pareto-optimal front.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116936517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450520
S. Dasnurkar, J. Abraham
The ideal goal of semiconductor quality assurance is to provide zero defective parts to the customer. In practice this goal is limited by test quality and test cost due to expensive ATE resources. It is typically not feasible to provide zero Defective Parts per Million (DPPM) for majority of applications due to the high costs of testing involved. Comprehensive functional tests to find all detectable faults typically have large test times resulting in a prohibitive cost. Work has been done in the field of digital testing with patterns where statistical tools are used in order to optimize the test cost and DPPM by real-time analysis. Our goal is to propose an Analog to Digital Converter (ADC) Built in Self Test (BiST) scheme which has compatibility with similar dynamic optimization measures. Multiple variants of Very Low Cost (VLC)- ATE have been developed for digital testing which rely on relaxed timing, power or tester channel requirements to lower hard-ware cost. Systems containing mixed-signal/RF components typically can not be tested on such ATE due to limitations/lack of analog/RF stimulus and measurement modules on VLC-ATE. This paper proposes a hybrid BIST scheme for ADCs to enable full production-quality testing as well as reduced coverage testing with VLC-ATE. We cover on-chip stimulus generation for a fully functional at-speed test as well as for a low-cost-reduced-coverage approach. Results for the BIST scheme are presented along with a discussion on implementation feasibility and merits. A vector based approach for observing ADC outputs is discussed which could be used with this scheme on VLC-ATE.
{"title":"Real-time dynamic hybrid BiST solution for Very-Low-Cost ATE production testing of A/D converters with controlled DPPM","authors":"S. Dasnurkar, J. Abraham","doi":"10.1109/ISQED.2010.5450520","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450520","url":null,"abstract":"The ideal goal of semiconductor quality assurance is to provide zero defective parts to the customer. In practice this goal is limited by test quality and test cost due to expensive ATE resources. It is typically not feasible to provide zero Defective Parts per Million (DPPM) for majority of applications due to the high costs of testing involved. Comprehensive functional tests to find all detectable faults typically have large test times resulting in a prohibitive cost. Work has been done in the field of digital testing with patterns where statistical tools are used in order to optimize the test cost and DPPM by real-time analysis. Our goal is to propose an Analog to Digital Converter (ADC) Built in Self Test (BiST) scheme which has compatibility with similar dynamic optimization measures. Multiple variants of Very Low Cost (VLC)- ATE have been developed for digital testing which rely on relaxed timing, power or tester channel requirements to lower hard-ware cost. Systems containing mixed-signal/RF components typically can not be tested on such ATE due to limitations/lack of analog/RF stimulus and measurement modules on VLC-ATE. This paper proposes a hybrid BIST scheme for ADCs to enable full production-quality testing as well as reduced coverage testing with VLC-ATE. We cover on-chip stimulus generation for a fully functional at-speed test as well as for a low-cost-reduced-coverage approach. Results for the BIST scheme are presented along with a discussion on implementation feasibility and merits. A vector based approach for observing ADC outputs is discussed which could be used with this scheme on VLC-ATE.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117266207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450504
Yuji Kunitake, Toshinori Sato, H. Yasuura
Negative Bias Temperature Instability (NBTI) is one of the major reliability problems in advanced technologies. NBTI causes threshold voltage degradation in a PMOS transistor which is biased to negative voltage. In an SRAM cell, due to NBTI, threshold voltage degrades in the load PMOS transistors. The degradation has the impact on Static Noise Margin (SNM), which is a measure of read stability of a 6-T SRAM cell. In this paper, we discuss the relationship between NBTI degradation in an SRAM cell and the signal probability. This is because, it is the key parameter of NBTI degradation. Based on the observations, we propose a novel cell-flipping technique in order to make signal probability close to 50%. The long cell-flipping period leads to threshold voltage degradation as large as the original case where the cell-flipping technique is not applied. Thus, we employ the short flipping period to the cell-flipping technique without any stall of operations. In consequence of applying the cell-flipping technique to a register file, we can relieve threshold voltage degradation by 70% after the SRAM cell is used for 3 years.
{"title":"Signal probability control for relieving NBTI in SRAM cells","authors":"Yuji Kunitake, Toshinori Sato, H. Yasuura","doi":"10.1109/ISQED.2010.5450504","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450504","url":null,"abstract":"Negative Bias Temperature Instability (NBTI) is one of the major reliability problems in advanced technologies. NBTI causes threshold voltage degradation in a PMOS transistor which is biased to negative voltage. In an SRAM cell, due to NBTI, threshold voltage degrades in the load PMOS transistors. The degradation has the impact on Static Noise Margin (SNM), which is a measure of read stability of a 6-T SRAM cell. In this paper, we discuss the relationship between NBTI degradation in an SRAM cell and the signal probability. This is because, it is the key parameter of NBTI degradation. Based on the observations, we propose a novel cell-flipping technique in order to make signal probability close to 50%. The long cell-flipping period leads to threshold voltage degradation as large as the original case where the cell-flipping technique is not applied. Thus, we employ the short flipping period to the cell-flipping technique without any stall of operations. In consequence of applying the cell-flipping technique to a register file, we can relieve threshold voltage degradation by 70% after the SRAM cell is used for 3 years.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122402100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450554
Prateek Mishra, A. Bhoj, N. Jha
In the recent past, FinFETs have been touted as promising alternatives to planar CMOS owing to their superior short-channel characteristics. However, due to lithographic constraints, they are likely to suffer from the effects of process variations, which are manifested as large spreads in leakage current and delay in combinational logic circuits. In this work, we model the leakage probability density function (pdf) in shorted-gate (SG), independent-gate (IG)/low-power (LP), and mixed-terminal (MT) FinFET standard logic cells, and examine the leakage tradeoffs in benchmark circuits synthesized using combinations of SG-, LP-, and MT-mode logic cells under the effect of process variations. Using quasi-Monte Carlo mixed-mode device simulations in Sentaurus TCAD, we develop simple macromodels to capture the physical effects influencing the leakage spread in SG- and IG-mode FinFET devices, and extend it to stacked devices in NAND/NOR gates. We also implement a methodology to obtain the overall leakage current distribution for large circuits (synthesized using SG/LP/MT-mode logic cells) using Latin hypercube sampling, considering spatial correlation on a quad-tree based grid. Results indicate that, starting from a 100% SG-mode circuit, the leakage spread/yield point can be improved considerably by suitably introducing LP-mode and MT-mode gates at iso-delay. We also show that increasing the fraction of LP/MT-mode gates (to reduce the mean and variance in leakage) in an SG-mode circuit, by permitting a delay slack, yields diminishing returns. Mixing LP- and MT-mode gates with SG-mode gates appears to be a promising synthesis strategy that can leverage the leakage tradeoffs offered by FinFET standard cells.
{"title":"Die-level leakage power analysis of FinFET circuits considering process variations","authors":"Prateek Mishra, A. Bhoj, N. Jha","doi":"10.1109/ISQED.2010.5450554","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450554","url":null,"abstract":"In the recent past, FinFETs have been touted as promising alternatives to planar CMOS owing to their superior short-channel characteristics. However, due to lithographic constraints, they are likely to suffer from the effects of process variations, which are manifested as large spreads in leakage current and delay in combinational logic circuits. In this work, we model the leakage probability density function (pdf) in shorted-gate (SG), independent-gate (IG)/low-power (LP), and mixed-terminal (MT) FinFET standard logic cells, and examine the leakage tradeoffs in benchmark circuits synthesized using combinations of SG-, LP-, and MT-mode logic cells under the effect of process variations. Using quasi-Monte Carlo mixed-mode device simulations in Sentaurus TCAD, we develop simple macromodels to capture the physical effects influencing the leakage spread in SG- and IG-mode FinFET devices, and extend it to stacked devices in NAND/NOR gates. We also implement a methodology to obtain the overall leakage current distribution for large circuits (synthesized using SG/LP/MT-mode logic cells) using Latin hypercube sampling, considering spatial correlation on a quad-tree based grid. Results indicate that, starting from a 100% SG-mode circuit, the leakage spread/yield point can be improved considerably by suitably introducing LP-mode and MT-mode gates at iso-delay. We also show that increasing the fraction of LP/MT-mode gates (to reduce the mean and variance in leakage) in an SG-mode circuit, by permitting a delay slack, yields diminishing returns. Mixing LP- and MT-mode gates with SG-mode gates appears to be a promising synthesis strategy that can leverage the leakage tradeoffs offered by FinFET standard cells.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"355 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122800726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450497
M. Momtazpour, E. Sanaei, M. Goudarzi
Delay and leakage power uncertainty caused by process variation has become a challenging problem in deep sub-micron technologies. In recent years, the designers have developed methods to tackle this problem in many design levels such as high level synthesis and system level synthesis. This paper addresses the problem of variation-aware task scheduling and binding for multiprocessor system-on-chip (MPSoC). We consider both delay and leakage power variations during the process of finding the best schedule so that leakier processors are less utilized and can be more frequently put in sleep mode to reduce power. Our algorithm takes advantage of event tables to accelerate the statistical timing and power analysis. We use genetic algorithm to find the best schedule that maximizes power-yield under performance-yield constraint. Experimental results on a wide range of real world and random benchmarks show that our proposed algorithm achieves 47% power-yield improvement on average over deterministic worst-case-based scheduling.
{"title":"Power-yield optimization in MPSoC task scheduling under process variation","authors":"M. Momtazpour, E. Sanaei, M. Goudarzi","doi":"10.1109/ISQED.2010.5450497","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450497","url":null,"abstract":"Delay and leakage power uncertainty caused by process variation has become a challenging problem in deep sub-micron technologies. In recent years, the designers have developed methods to tackle this problem in many design levels such as high level synthesis and system level synthesis. This paper addresses the problem of variation-aware task scheduling and binding for multiprocessor system-on-chip (MPSoC). We consider both delay and leakage power variations during the process of finding the best schedule so that leakier processors are less utilized and can be more frequently put in sleep mode to reduce power. Our algorithm takes advantage of event tables to accelerate the statistical timing and power analysis. We use genetic algorithm to find the best schedule that maximizes power-yield under performance-yield constraint. Experimental results on a wide range of real world and random benchmarks show that our proposed algorithm achieves 47% power-yield improvement on average over deterministic worst-case-based scheduling.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122878453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As VLSI technology scales into sub-65nm realm, the complexity of timing optimization is drastically increased by the consideration of power and variations. Even though designers make great efforts during physical design, they are often faced with still heavy timing violations in deep post-routing stages. For the entire design convergence and timing closure, especially under current multi-corner multi-mode design, some more efficient methods need to be invented. In this work, we propose to address such a kind of issue by exploiting useful clock skew, which can help reduce timing violations rapidly. We also add mode/corner metric balancing measurements to make this method more flexible and applicable especially in such deep stages while the CTS is ready. The results indicate that our method can achieve an average improvements of 33.16% on the worst slack (WS) and 75.56% on the total negative slack (TNS), respectively.
{"title":"Useful clock skew optimization under a multi-corner multi-mode design framework","authors":"Weixiang Shen, Yici Cai, Wei Chen, Yongqiang Lyu, Qiang Zhou, Jiang Hu","doi":"10.1109/ISQED.2010.5450402","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450402","url":null,"abstract":"As VLSI technology scales into sub-65nm realm, the complexity of timing optimization is drastically increased by the consideration of power and variations. Even though designers make great efforts during physical design, they are often faced with still heavy timing violations in deep post-routing stages. For the entire design convergence and timing closure, especially under current multi-corner multi-mode design, some more efficient methods need to be invented. In this work, we propose to address such a kind of issue by exploiting useful clock skew, which can help reduce timing violations rapidly. We also add mode/corner metric balancing measurements to make this method more flexible and applicable especially in such deep stages while the CTS is ready. The results indicate that our method can achieve an average improvements of 33.16% on the worst slack (WS) and 75.56% on the total negative slack (TNS), respectively.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129803611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450479
Hui Li, M. Mansour, Sury Maturi, Li-C. Wang
This paper presents a novel behavioral-level analog circuit performance modeling methodology using kernel based support vector machine (SVM). Behavioral modeling for analog circuits is in high demand for architectural exploration and system prototyping of increasingly complex electronic systems. In this paper, we investigate the effectiveness of applying SVM to model analog circuits. Based on the different perspectives of model accuracy, we develop a model performance optimizer which automatically tunes the learning engine to achieve either the lowest worst-case error or the average error percentage. The modeling performance is compared against SPICE simulation result to validate this approach. We also present its advantages in automation and simulation speed.
{"title":"Analog behavioral modeling flow using statistical learning method","authors":"Hui Li, M. Mansour, Sury Maturi, Li-C. Wang","doi":"10.1109/ISQED.2010.5450479","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450479","url":null,"abstract":"This paper presents a novel behavioral-level analog circuit performance modeling methodology using kernel based support vector machine (SVM). Behavioral modeling for analog circuits is in high demand for architectural exploration and system prototyping of increasingly complex electronic systems. In this paper, we investigate the effectiveness of applying SVM to model analog circuits. Based on the different perspectives of model accuracy, we develop a model performance optimizer which automatically tunes the learning engine to achieve either the lowest worst-case error or the average error percentage. The modeling performance is compared against SPICE simulation result to validate this approach. We also present its advantages in automation and simulation speed.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125330523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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