Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450555
P. Buck, F. Kalk, C. West
Photomasks have evolved from simple replicators of design layout for lithography to become complex translators of design intent for sub-wavelength imaging systems while at the same time maintaining a cost efficiency that exceeds Moore's Law predictions for scalability in the semiconductor industry. The cost performance of photomasks is reviewed in context to design costs. The life cycle of a photomask product node is examined with respect to capital investment costs. Predictions for future photomask cost challenges are considered.
{"title":"Photomasks and the enablement of circuit design complexity","authors":"P. Buck, F. Kalk, C. West","doi":"10.1109/ISQED.2010.5450555","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450555","url":null,"abstract":"Photomasks have evolved from simple replicators of design layout for lithography to become complex translators of design intent for sub-wavelength imaging systems while at the same time maintaining a cost efficiency that exceeds Moore's Law predictions for scalability in the semiconductor industry. The cost performance of photomasks is reviewed in context to design costs. The life cycle of a photomask product node is examined with respect to capital investment costs. Predictions for future photomask cost challenges are considered.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117174401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450396
Ming-Ta Yang, Yang Du, C. Teng, Tony Chang, E. Worley, K. Liao, Y. Yau, G. Yeap
POLY gate defined lateral ESD diodes were fabricated, characterized and modeled using Foundry standard 65nm CMOS technology. Compare to conventional STI diode, the lateral diode demonstrated superior Q-factor and TLP IT2 due to the reduced transport distance and RC constant. Aided by BSIM4 MOS transistor model, a physically based scalable lateral diode model was developed and presented here for the first time. The accuracy of the diode model was validated with RF characterization data over a broad device geometrical range. The model was successfully used in LNA and ESD CDM protection co-design. A good match of LNA RF performance between Si-data and model prediction was achieved. Experimental results showed that LNA with Lateral Diode protection passed +/−500V ESD CDM zap voltage, while LNA with STI diode started to fail at only −250V.
{"title":"BSIM4-based lateral diode model for LNA co-designed with ESD protection circuit","authors":"Ming-Ta Yang, Yang Du, C. Teng, Tony Chang, E. Worley, K. Liao, Y. Yau, G. Yeap","doi":"10.1109/ISQED.2010.5450396","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450396","url":null,"abstract":"POLY gate defined lateral ESD diodes were fabricated, characterized and modeled using Foundry standard 65nm CMOS technology. Compare to conventional STI diode, the lateral diode demonstrated superior Q-factor and TLP IT2 due to the reduced transport distance and RC constant. Aided by BSIM4 MOS transistor model, a physically based scalable lateral diode model was developed and presented here for the first time. The accuracy of the diode model was validated with RF characterization data over a broad device geometrical range. The model was successfully used in LNA and ESD CDM protection co-design. A good match of LNA RF performance between Si-data and model prediction was achieved. Experimental results showed that LNA with Lateral Diode protection passed +/−500V ESD CDM zap voltage, while LNA with STI diode started to fail at only −250V.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130566682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450540
Long Fei, L. Mize, Cho Moon, Bill Mullen, Sonia Singhal
Timing constraints are used by implementation tools in all design stages in modern design flows. With the growing complexity of designs and constraints, it is increasingly challenging to identify, diagnose, and fix constraint problems. In this paper, we present the technology of an interactive constraint debugger that automatically checks constraint problems, and provides context-sensitive diagnosis and fix suggestions. Our extensive user feedback shows that the tool significantly improves designer productivity.
{"title":"Constraint analysis and debugging for multi-million instance SoC designs","authors":"Long Fei, L. Mize, Cho Moon, Bill Mullen, Sonia Singhal","doi":"10.1109/ISQED.2010.5450540","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450540","url":null,"abstract":"Timing constraints are used by implementation tools in all design stages in modern design flows. With the growing complexity of designs and constraints, it is increasingly challenging to identify, diagnose, and fix constraint problems. In this paper, we present the technology of an interactive constraint debugger that automatically checks constraint problems, and provides context-sensitive diagnosis and fix suggestions. Our extensive user feedback shows that the tool significantly improves designer productivity.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134109832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450556
K. Lata, H. S. Jamadagni
In this paper, we present a case study of formal verification of analog and mixed signal designs using SPICE circuit simulation traces. We consider verifying safety properties of Full Wave Rectifier (FWR) using SPICE circuit simulation traces. We follow the formal verification approach of [1] where authors have used the SPICE circuit simulation traces for doing the formal analysis of the Analog and Mixed Signal circuits. We have used the Checkmate tool from CMU [2], which is a public domain formal verification tool for hybrid systems. Checkmate is built on the top of the Simulink/Stateflow Framework (SSF) from MATLAB from Math Works. Due to restriction imposed by Checkmate it necessitates to make the changes in the Checkmate implementation to implement the complex and non-linear systems. FWR has been implemented by using Checkmate custom blocks and Simulink blocks from MATLAB. The FWR model has been implemented in LTSPICE. The formal verification has been done for both the implementation i.e. Simulink implementation as well as LTSPICE implementation. We are able to efficiently verify the safety properties of the full wave rectifier using simulation traces from Simulink model and LTSPICE simulation.
{"title":"Formal verification of Full-Wave Rectifier using SPICE circuit simulation traces","authors":"K. Lata, H. S. Jamadagni","doi":"10.1109/ISQED.2010.5450556","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450556","url":null,"abstract":"In this paper, we present a case study of formal verification of analog and mixed signal designs using SPICE circuit simulation traces. We consider verifying safety properties of Full Wave Rectifier (FWR) using SPICE circuit simulation traces. We follow the formal verification approach of [1] where authors have used the SPICE circuit simulation traces for doing the formal analysis of the Analog and Mixed Signal circuits. We have used the Checkmate tool from CMU [2], which is a public domain formal verification tool for hybrid systems. Checkmate is built on the top of the Simulink/Stateflow Framework (SSF) from MATLAB from Math Works. Due to restriction imposed by Checkmate it necessitates to make the changes in the Checkmate implementation to implement the complex and non-linear systems. FWR has been implemented by using Checkmate custom blocks and Simulink blocks from MATLAB. The FWR model has been implemented in LTSPICE. The formal verification has been done for both the implementation i.e. Simulink implementation as well as LTSPICE implementation. We are able to efficiently verify the safety properties of the full wave rectifier using simulation traces from Simulink model and LTSPICE simulation.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130275821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450399
Shiho Hagiwara, K. Yamanaga, Ryo Takahashi, K. Masu, Takashi Sato
A fast calculation tool for state-dependent capacitance of power distribution network is proposed. The proposed method achieves linear time-complexity, which can be more than four orders magnitude faster than a conventional SPICE-based capacitance calculation. Large circuits that have been unanalyzable with the conventional method become analyzable for more comprehensive exploration of capacitance variation. The capacitance obtained with the proposed method agrees SPICE-based method completely (up to 5 digits), and time-linearity is confirmed through numerical experiments on various circuits. The proposed tool facilitates to study capacitance variation, which is necessary to build an accurate macro model of an LSI.
{"title":"Linear time calculation of state-dependent power distribution network capacitance","authors":"Shiho Hagiwara, K. Yamanaga, Ryo Takahashi, K. Masu, Takashi Sato","doi":"10.1109/ISQED.2010.5450399","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450399","url":null,"abstract":"A fast calculation tool for state-dependent capacitance of power distribution network is proposed. The proposed method achieves linear time-complexity, which can be more than four orders magnitude faster than a conventional SPICE-based capacitance calculation. Large circuits that have been unanalyzable with the conventional method become analyzable for more comprehensive exploration of capacitance variation. The capacitance obtained with the proposed method agrees SPICE-based method completely (up to 5 digits), and time-linearity is confirmed through numerical experiments on various circuits. The proposed tool facilitates to study capacitance variation, which is necessary to build an accurate macro model of an LSI.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133177984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450489
Rung-Bin Lin, I.-W. Lee, Wen-Hao Chen
In this paper, we propose a clock routing algorithm for structured ASICs using predefined yet via-configurable metal wires. Our algorithm has many distinct features implemented to address the specific problems encountered by the tasks of creating tapping points and performing wire snaking. We also present an approach to merging two subtrees without exacerbating the skew of a merged tree. Experimental data show that a delay-balanced clock tree can be constructed using via-configurable routing fabric, with an average skew of 8.1% of clock latency for some benchmark circuits. Such a result is comparable to what can be achieved by a commercial clock tree synthesizer.
{"title":"Clock routing for structured ASICs with via-configurable fabrics","authors":"Rung-Bin Lin, I.-W. Lee, Wen-Hao Chen","doi":"10.1109/ISQED.2010.5450489","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450489","url":null,"abstract":"In this paper, we propose a clock routing algorithm for structured ASICs using predefined yet via-configurable metal wires. Our algorithm has many distinct features implemented to address the specific problems encountered by the tasks of creating tapping points and performing wire snaking. We also present an approach to merging two subtrees without exacerbating the skew of a merged tree. Experimental data show that a delay-balanced clock tree can be constructed using via-configurable routing fabric, with an average skew of 8.1% of clock latency for some benchmark circuits. Such a result is comparable to what can be achieved by a commercial clock tree synthesizer.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130770268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450395
Venkata Naresh Mudhireddy, Saravanan Ramamoorthy, Haibo Wang
This paper presents a methodology and experiments on implementing self-healing analog circuits on a hardware platform that consists of microcontroller, flash memory, and a switched-capacitor based field programmable analog array (FPAA) device. By taking advantage of FPAA programmability and the availability of redundant resources, the microcontroller programs the FPAA circuit into different circuit configurations to perform online testing. The microcontroller also monitors the online testing data to determine if circuit faults occur. Once a circuit fault is detected, the FPAA circuit will be reconfigured to replace the faulty circuit block by a redundant resource to achieve self-healing. Experiments results are presented to show the effectiveness of the fault detection method and demonstrate the feasibility of self-healing operations.
{"title":"Implementing self-testing and self-repairable analog circuits on field programmable analog array platforms","authors":"Venkata Naresh Mudhireddy, Saravanan Ramamoorthy, Haibo Wang","doi":"10.1109/ISQED.2010.5450395","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450395","url":null,"abstract":"This paper presents a methodology and experiments on implementing self-healing analog circuits on a hardware platform that consists of microcontroller, flash memory, and a switched-capacitor based field programmable analog array (FPAA) device. By taking advantage of FPAA programmability and the availability of redundant resources, the microcontroller programs the FPAA circuit into different circuit configurations to perform online testing. The microcontroller also monitors the online testing data to determine if circuit faults occur. Once a circuit fault is detected, the FPAA circuit will be reconfigured to replace the faulty circuit block by a redundant resource to achieve self-healing. Experiments results are presented to show the effectiveness of the fault detection method and demonstrate the feasibility of self-healing operations.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121765459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450482
David Li, P. Chuang, M. Sachdev
In this paper, we analyze and characterize the metastability of 11 previously proposed high-performance flip-flops, reduced clock-swing flip-flops, and level-converting flip-flops. From extensive simulation results in 65nm CMOS technology, the main metastability parameters of τ and T0 are extracted and analyzed at both nominal and reduced supply voltage. Our simulation results indicate that these flip-flops exhibit a wide range (up to few orders of magnitudes) of metastability windows. In particular, flip-flops with differential and positive feedback configuration such as the sense-amplifier based flip-flops demonstrate the most optimal metastability. Based on this finding, a novel pre-discharge flip-flop (PDFF) with positive feedback configuration is proposed. Extensive simulation results reveal that PDFF achieves better metastability than the previous proposed flip-flops at both nominal voltage supply and nominal voltage supply with reduced clock-swing.
{"title":"Comparative analysis and study of metastability on high-performance flip-flops","authors":"David Li, P. Chuang, M. Sachdev","doi":"10.1109/ISQED.2010.5450482","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450482","url":null,"abstract":"In this paper, we analyze and characterize the metastability of 11 previously proposed high-performance flip-flops, reduced clock-swing flip-flops, and level-converting flip-flops. From extensive simulation results in 65nm CMOS technology, the main metastability parameters of τ and T0 are extracted and analyzed at both nominal and reduced supply voltage. Our simulation results indicate that these flip-flops exhibit a wide range (up to few orders of magnitudes) of metastability windows. In particular, flip-flops with differential and positive feedback configuration such as the sense-amplifier based flip-flops demonstrate the most optimal metastability. Based on this finding, a novel pre-discharge flip-flop (PDFF) with positive feedback configuration is proposed. Extensive simulation results reveal that PDFF achieves better metastability than the previous proposed flip-flops at both nominal voltage supply and nominal voltage supply with reduced clock-swing.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127539241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450391
Y. Ben, L. Ghaoui, K. Poolla, C. Spanos
Circuit design under process variation can be formulated mathematically as a robust optimization problem with a yield constraint. Existing methods force designers to either resort to overly simplified circuit performance model, or rely on simplistic variability assumptions. On the other hand, accurate yield estimation must incorporate a sophisticated variability model that recognizes both systematic and random components at various levels of hierarchy. Unfortunately, such models are not compatible with existing optimization solutions. To solve the problem, we propose the sequential geometric programming method, which consists of iterative usage of geometric programming and importance sampling, and is capable of handling an arbitrary variability model. The proposed method is shown to be able to achieve the desired yield without overdesign, and solve circuits with thousands of gates within reasonable amount of time.
{"title":"Yield-constrained digital circuit sizing via sequential geometric programming","authors":"Y. Ben, L. Ghaoui, K. Poolla, C. Spanos","doi":"10.1109/ISQED.2010.5450391","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450391","url":null,"abstract":"Circuit design under process variation can be formulated mathematically as a robust optimization problem with a yield constraint. Existing methods force designers to either resort to overly simplified circuit performance model, or rely on simplistic variability assumptions. On the other hand, accurate yield estimation must incorporate a sophisticated variability model that recognizes both systematic and random components at various levels of hierarchy. Unfortunately, such models are not compatible with existing optimization solutions. To solve the problem, we propose the sequential geometric programming method, which consists of iterative usage of geometric programming and importance sampling, and is capable of handling an arbitrary variability model. The proposed method is shown to be able to achieve the desired yield without overdesign, and solve circuits with thousands of gates within reasonable amount of time.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116797808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450534
E. Nigussie, J. Plosila, J. Isoaho
We present a process variation tolerance technique for current sensing on-chip links. Process variation affects the signal integrity of a current sensing receiver. As the amount of worst-case current variation is increasing in sub-100nm technologies, the conventional worst-case process variation assumption has a high power consumption cost. We propose adjusting currents at every power start-up of the system through receiver and driver reconfiguration when an error is detected. This makes the link adaptive to the effect of variations enabling continuous and reliable operation of the link. It also results in lower power consumption than the worst-case approach. An error detection scheme as well as a reconfiguration algorithm and methodology are developed. Furthermore, reconfiguration control and communication circuits are designed and simulated for a multilevel current sensing link. Depending on the detected error(s), the time it takes to adjust the currents and start the normal data transmission phase ranges from 2.66ns to 5.72ns. The proposed technique is area efficient for relatively wider links. For a 64-bits link the overhead is 4.67% silicon area and 2.63% wiring area. The circuits are designed and simulated in Cadence Analog Spectre using 65nm CMOS technology from STMicroelectronics.
我们提出了一种电流传感片上链路的工艺变化容限技术。过程变化会影响电流传感接收器的信号完整性。随着亚100nm技术中最坏情况电流变化量的增加，传统的最坏情况工艺变化假设具有较高的功耗成本。我们建议在检测到错误时，通过重新配置接收器和驱动器来调整系统每次电源启动时的电流。这使得连杆能够适应变化的影响，从而使连杆能够连续可靠地运行。与最坏情况的方法相比，它的功耗也更低。提出了一种错误检测方案、重构算法和方法。在此基础上，设计并仿真了多电平电流传感链路的重构控制电路和通信电路。根据检测到的误差(s)，调整电流并启动正常数据传输相位所需的时间范围为2.66ns至5.72ns。所提出的技术是面积效率相对较宽的链接。对于64位链路，开销是4.67%的硅面积和2.63%的布线面积。电路采用意法半导体的65nm CMOS技术在Cadence Analog Spectre中设计和仿真。
{"title":"Process variation tolerant on-chip communication using receiver and driver reconfiguration","authors":"E. Nigussie, J. Plosila, J. Isoaho","doi":"10.1109/ISQED.2010.5450534","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450534","url":null,"abstract":"We present a process variation tolerance technique for current sensing on-chip links. Process variation affects the signal integrity of a current sensing receiver. As the amount of worst-case current variation is increasing in sub-100nm technologies, the conventional worst-case process variation assumption has a high power consumption cost. We propose adjusting currents at every power start-up of the system through receiver and driver reconfiguration when an error is detected. This makes the link adaptive to the effect of variations enabling continuous and reliable operation of the link. It also results in lower power consumption than the worst-case approach. An error detection scheme as well as a reconfiguration algorithm and methodology are developed. Furthermore, reconfiguration control and communication circuits are designed and simulated for a multilevel current sensing link. Depending on the detected error(s), the time it takes to adjust the currents and start the normal data transmission phase ranges from 2.66ns to 5.72ns. The proposed technique is area efficient for relatively wider links. For a 64-bits link the overhead is 4.67% silicon area and 2.63% wiring area. The circuits are designed and simulated in Cadence Analog Spectre using 65nm CMOS technology from STMicroelectronics.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115571746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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