Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450399
Shiho Hagiwara, K. Yamanaga, Ryo Takahashi, K. Masu, Takashi Sato
A fast calculation tool for state-dependent capacitance of power distribution network is proposed. The proposed method achieves linear time-complexity, which can be more than four orders magnitude faster than a conventional SPICE-based capacitance calculation. Large circuits that have been unanalyzable with the conventional method become analyzable for more comprehensive exploration of capacitance variation. The capacitance obtained with the proposed method agrees SPICE-based method completely (up to 5 digits), and time-linearity is confirmed through numerical experiments on various circuits. The proposed tool facilitates to study capacitance variation, which is necessary to build an accurate macro model of an LSI.
{"title":"Linear time calculation of state-dependent power distribution network capacitance","authors":"Shiho Hagiwara, K. Yamanaga, Ryo Takahashi, K. Masu, Takashi Sato","doi":"10.1109/ISQED.2010.5450399","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450399","url":null,"abstract":"A fast calculation tool for state-dependent capacitance of power distribution network is proposed. The proposed method achieves linear time-complexity, which can be more than four orders magnitude faster than a conventional SPICE-based capacitance calculation. Large circuits that have been unanalyzable with the conventional method become analyzable for more comprehensive exploration of capacitance variation. The capacitance obtained with the proposed method agrees SPICE-based method completely (up to 5 digits), and time-linearity is confirmed through numerical experiments on various circuits. The proposed tool facilitates to study capacitance variation, which is necessary to build an accurate macro model of an LSI.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133177984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450556
K. Lata, H. S. Jamadagni
In this paper, we present a case study of formal verification of analog and mixed signal designs using SPICE circuit simulation traces. We consider verifying safety properties of Full Wave Rectifier (FWR) using SPICE circuit simulation traces. We follow the formal verification approach of [1] where authors have used the SPICE circuit simulation traces for doing the formal analysis of the Analog and Mixed Signal circuits. We have used the Checkmate tool from CMU [2], which is a public domain formal verification tool for hybrid systems. Checkmate is built on the top of the Simulink/Stateflow Framework (SSF) from MATLAB from Math Works. Due to restriction imposed by Checkmate it necessitates to make the changes in the Checkmate implementation to implement the complex and non-linear systems. FWR has been implemented by using Checkmate custom blocks and Simulink blocks from MATLAB. The FWR model has been implemented in LTSPICE. The formal verification has been done for both the implementation i.e. Simulink implementation as well as LTSPICE implementation. We are able to efficiently verify the safety properties of the full wave rectifier using simulation traces from Simulink model and LTSPICE simulation.
{"title":"Formal verification of Full-Wave Rectifier using SPICE circuit simulation traces","authors":"K. Lata, H. S. Jamadagni","doi":"10.1109/ISQED.2010.5450556","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450556","url":null,"abstract":"In this paper, we present a case study of formal verification of analog and mixed signal designs using SPICE circuit simulation traces. We consider verifying safety properties of Full Wave Rectifier (FWR) using SPICE circuit simulation traces. We follow the formal verification approach of [1] where authors have used the SPICE circuit simulation traces for doing the formal analysis of the Analog and Mixed Signal circuits. We have used the Checkmate tool from CMU [2], which is a public domain formal verification tool for hybrid systems. Checkmate is built on the top of the Simulink/Stateflow Framework (SSF) from MATLAB from Math Works. Due to restriction imposed by Checkmate it necessitates to make the changes in the Checkmate implementation to implement the complex and non-linear systems. FWR has been implemented by using Checkmate custom blocks and Simulink blocks from MATLAB. The FWR model has been implemented in LTSPICE. The formal verification has been done for both the implementation i.e. Simulink implementation as well as LTSPICE implementation. We are able to efficiently verify the safety properties of the full wave rectifier using simulation traces from Simulink model and LTSPICE simulation.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130275821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450396
Ming-Ta Yang, Yang Du, C. Teng, Tony Chang, E. Worley, K. Liao, Y. Yau, G. Yeap
POLY gate defined lateral ESD diodes were fabricated, characterized and modeled using Foundry standard 65nm CMOS technology. Compare to conventional STI diode, the lateral diode demonstrated superior Q-factor and TLP IT2 due to the reduced transport distance and RC constant. Aided by BSIM4 MOS transistor model, a physically based scalable lateral diode model was developed and presented here for the first time. The accuracy of the diode model was validated with RF characterization data over a broad device geometrical range. The model was successfully used in LNA and ESD CDM protection co-design. A good match of LNA RF performance between Si-data and model prediction was achieved. Experimental results showed that LNA with Lateral Diode protection passed +/−500V ESD CDM zap voltage, while LNA with STI diode started to fail at only −250V.
{"title":"BSIM4-based lateral diode model for LNA co-designed with ESD protection circuit","authors":"Ming-Ta Yang, Yang Du, C. Teng, Tony Chang, E. Worley, K. Liao, Y. Yau, G. Yeap","doi":"10.1109/ISQED.2010.5450396","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450396","url":null,"abstract":"POLY gate defined lateral ESD diodes were fabricated, characterized and modeled using Foundry standard 65nm CMOS technology. Compare to conventional STI diode, the lateral diode demonstrated superior Q-factor and TLP IT2 due to the reduced transport distance and RC constant. Aided by BSIM4 MOS transistor model, a physically based scalable lateral diode model was developed and presented here for the first time. The accuracy of the diode model was validated with RF characterization data over a broad device geometrical range. The model was successfully used in LNA and ESD CDM protection co-design. A good match of LNA RF performance between Si-data and model prediction was achieved. Experimental results showed that LNA with Lateral Diode protection passed +/−500V ESD CDM zap voltage, while LNA with STI diode started to fail at only −250V.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130566682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450513
Rajeev K. Nain, Shantesh Pinge, M. Chrzanowska-Jeske
Through signal vias (TSVs) in 3D ICs suffer from thermo-mechanical stress, and may fail or attain plasticity resulting in significant yield loss. We present a novel set of strategies for yield improvement in the presence of defects in through signal vias in heterogeneous 3D system-on-chip. Monte-Carlo simulation results show that our strategy can improve the yield of 3D ICs significantly. Furthermore, we estimate the parametric yield and present a quantitative analysis of the impact of our approach on chip area, power, performance and chip revenue that can improve profitability. Our results suggest that the proposed strategies can be very useful in yield-aware 3D design.
{"title":"Yield improvement of 3D ICs in the presence of defects in through signal vias","authors":"Rajeev K. Nain, Shantesh Pinge, M. Chrzanowska-Jeske","doi":"10.1109/ISQED.2010.5450513","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450513","url":null,"abstract":"Through signal vias (TSVs) in 3D ICs suffer from thermo-mechanical stress, and may fail or attain plasticity resulting in significant yield loss. We present a novel set of strategies for yield improvement in the presence of defects in through signal vias in heterogeneous 3D system-on-chip. Monte-Carlo simulation results show that our strategy can improve the yield of 3D ICs significantly. Furthermore, we estimate the parametric yield and present a quantitative analysis of the impact of our approach on chip area, power, performance and chip revenue that can improve profitability. Our results suggest that the proposed strategies can be very useful in yield-aware 3D design.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128328192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450489
Rung-Bin Lin, I.-W. Lee, Wen-Hao Chen
In this paper, we propose a clock routing algorithm for structured ASICs using predefined yet via-configurable metal wires. Our algorithm has many distinct features implemented to address the specific problems encountered by the tasks of creating tapping points and performing wire snaking. We also present an approach to merging two subtrees without exacerbating the skew of a merged tree. Experimental data show that a delay-balanced clock tree can be constructed using via-configurable routing fabric, with an average skew of 8.1% of clock latency for some benchmark circuits. Such a result is comparable to what can be achieved by a commercial clock tree synthesizer.
{"title":"Clock routing for structured ASICs with via-configurable fabrics","authors":"Rung-Bin Lin, I.-W. Lee, Wen-Hao Chen","doi":"10.1109/ISQED.2010.5450489","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450489","url":null,"abstract":"In this paper, we propose a clock routing algorithm for structured ASICs using predefined yet via-configurable metal wires. Our algorithm has many distinct features implemented to address the specific problems encountered by the tasks of creating tapping points and performing wire snaking. We also present an approach to merging two subtrees without exacerbating the skew of a merged tree. Experimental data show that a delay-balanced clock tree can be constructed using via-configurable routing fabric, with an average skew of 8.1% of clock latency for some benchmark circuits. Such a result is comparable to what can be achieved by a commercial clock tree synthesizer.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130770268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450540
Long Fei, L. Mize, Cho Moon, Bill Mullen, Sonia Singhal
Timing constraints are used by implementation tools in all design stages in modern design flows. With the growing complexity of designs and constraints, it is increasingly challenging to identify, diagnose, and fix constraint problems. In this paper, we present the technology of an interactive constraint debugger that automatically checks constraint problems, and provides context-sensitive diagnosis and fix suggestions. Our extensive user feedback shows that the tool significantly improves designer productivity.
{"title":"Constraint analysis and debugging for multi-million instance SoC designs","authors":"Long Fei, L. Mize, Cho Moon, Bill Mullen, Sonia Singhal","doi":"10.1109/ISQED.2010.5450540","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450540","url":null,"abstract":"Timing constraints are used by implementation tools in all design stages in modern design flows. With the growing complexity of designs and constraints, it is increasingly challenging to identify, diagnose, and fix constraint problems. In this paper, we present the technology of an interactive constraint debugger that automatically checks constraint problems, and provides context-sensitive diagnosis and fix suggestions. Our extensive user feedback shows that the tool significantly improves designer productivity.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134109832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450390
Yao Peng, Jinyu Zhang, Yan Wang, Zhiping Yu
Recently, source and mask optimization (SMO) has been proposed as an effective solution to help extending the life time of conventional 193nm lithography. However, SMO is very computationally intensive. To mitigate this issue, we propose a highly effective and efficient method for source optimization in this paper. Based on the gray-level pixel based source representation, the gradient of the cost function is calculated to guide optimization to improve the wafer image fidelity and depth of focus (DOF). This method is demonstrated using two mask patterns with critical dimension of 45nm, including a periodic array of contact holes and an asymmetric mask pattern from an SRAM layout. Comparing with two recently proposed methods, our method can provide greater improvements in image quality and over 10X running speed enhancement. The robustness of our method is verified using several different initial source patterns. Results show that similar final optimized source patterns and image quality have been achieved.
{"title":"High performance source optimization using a gradient-based method in optical lithography","authors":"Yao Peng, Jinyu Zhang, Yan Wang, Zhiping Yu","doi":"10.1109/ISQED.2010.5450390","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450390","url":null,"abstract":"Recently, source and mask optimization (SMO) has been proposed as an effective solution to help extending the life time of conventional 193nm lithography. However, SMO is very computationally intensive. To mitigate this issue, we propose a highly effective and efficient method for source optimization in this paper. Based on the gray-level pixel based source representation, the gradient of the cost function is calculated to guide optimization to improve the wafer image fidelity and depth of focus (DOF). This method is demonstrated using two mask patterns with critical dimension of 45nm, including a periodic array of contact holes and an asymmetric mask pattern from an SRAM layout. Comparing with two recently proposed methods, our method can provide greater improvements in image quality and over 10X running speed enhancement. The robustness of our method is verified using several different initial source patterns. Results show that similar final optimized source patterns and image quality have been achieved.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123895534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450488
E. Hwang, Wook Kim, Young Hwan Kim
The process variation of the ultra-deep submicron technology causes significant variation in the timing characteristics of flip-flops, and it can drop functional yield seriously, affecting system timing. This paper has two objectives. First, this paper investigates the sensitivities to process variation of four representative flip-flop architectures that are popularly used in digital circuit designs in respect of their functional robustness. Secondly, this paper proposes simple but effective methods to improve the process variation tolerability of those flip-flops. Experimental results on four benchmark flip-flops, which were optimized for minimum power-delay product, show that their variability of data-to-q delay reaches to 33.02% ∼ 46.13% and functional yield reaches to 79.93% ∼ 99.86%. Also, the experimental results clearly show that the proposed approaches improve the variability of data-to-q delay by 11.53% ∼ 44.78% and functional yield by 0.11% ∼ 24.41%.
{"title":"Improving the process variation tolerability of flip-flops for UDSM circuit design","authors":"E. Hwang, Wook Kim, Young Hwan Kim","doi":"10.1109/ISQED.2010.5450488","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450488","url":null,"abstract":"The process variation of the ultra-deep submicron technology causes significant variation in the timing characteristics of flip-flops, and it can drop functional yield seriously, affecting system timing. This paper has two objectives. First, this paper investigates the sensitivities to process variation of four representative flip-flop architectures that are popularly used in digital circuit designs in respect of their functional robustness. Secondly, this paper proposes simple but effective methods to improve the process variation tolerability of those flip-flops. Experimental results on four benchmark flip-flops, which were optimized for minimum power-delay product, show that their variability of data-to-q delay reaches to 33.02% ∼ 46.13% and functional yield reaches to 79.93% ∼ 99.86%. Also, the experimental results clearly show that the proposed approaches improve the variability of data-to-q delay by 11.53% ∼ 44.78% and functional yield by 0.11% ∼ 24.41%.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124318684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450516
M. Baby, V. Sarathi
Peak power consumption during test for the low power devices is a major concern [2, 3, 4]. Excessive peak power may result in test failures of functionally good devices. Huge peaks in the instantaneous power consumption will result in high rates of change of current (di/dt) causing adverse noise effects like VDD-drop and ground-bounce [1, 2, 3, 4]. Also, a high frequency of occurrence of high di/dt may cause severe decrease in the reliability of the circuit [1]. Hence the process of testing low power devices must be peak power aware. This paper provides a method to minimize the peak power during speed capture phase by partitioning the nodes into two zones based on their timing slacks. One of the zones contains the timing-critical nodes, while the other contains the non timing-critical ones. Each zone may be split into multiple bins. Test patterns are generated independently for each bin, targeting the nodes belonging to that bin alone, thus reducing the size of the target set. It is very important that the peak power consumed by the test patterns for each bin in the timing-critical zone is well within the tolerable limit. The bins in the non timing-critical zone may be allowed to have peak power consumptions very close to the limit or even marginally higher because the large positive slacks on these nodes will make up for the extra delay through the cells caused by VDD-drop/ground-bounce. This approach allows the designer to have a better control over each pattern and also helps to minimize the effects of high peak power and high di/dt.
{"title":"Slack-based approach for peak power reduction during transition fault testing","authors":"M. Baby, V. Sarathi","doi":"10.1109/ISQED.2010.5450516","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450516","url":null,"abstract":"Peak power consumption during test for the low power devices is a major concern [2, 3, 4]. Excessive peak power may result in test failures of functionally good devices. Huge peaks in the instantaneous power consumption will result in high rates of change of current (di/dt) causing adverse noise effects like VDD-drop and ground-bounce [1, 2, 3, 4]. Also, a high frequency of occurrence of high di/dt may cause severe decrease in the reliability of the circuit [1]. Hence the process of testing low power devices must be peak power aware. This paper provides a method to minimize the peak power during speed capture phase by partitioning the nodes into two zones based on their timing slacks. One of the zones contains the timing-critical nodes, while the other contains the non timing-critical ones. Each zone may be split into multiple bins. Test patterns are generated independently for each bin, targeting the nodes belonging to that bin alone, thus reducing the size of the target set. It is very important that the peak power consumed by the test patterns for each bin in the timing-critical zone is well within the tolerable limit. The bins in the non timing-critical zone may be allowed to have peak power consumptions very close to the limit or even marginally higher because the large positive slacks on these nodes will make up for the extra delay through the cells caused by VDD-drop/ground-bounce. This approach allows the designer to have a better control over each pattern and also helps to minimize the effects of high peak power and high di/dt.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124387795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450391
Y. Ben, L. Ghaoui, K. Poolla, C. Spanos
Circuit design under process variation can be formulated mathematically as a robust optimization problem with a yield constraint. Existing methods force designers to either resort to overly simplified circuit performance model, or rely on simplistic variability assumptions. On the other hand, accurate yield estimation must incorporate a sophisticated variability model that recognizes both systematic and random components at various levels of hierarchy. Unfortunately, such models are not compatible with existing optimization solutions. To solve the problem, we propose the sequential geometric programming method, which consists of iterative usage of geometric programming and importance sampling, and is capable of handling an arbitrary variability model. The proposed method is shown to be able to achieve the desired yield without overdesign, and solve circuits with thousands of gates within reasonable amount of time.
{"title":"Yield-constrained digital circuit sizing via sequential geometric programming","authors":"Y. Ben, L. Ghaoui, K. Poolla, C. Spanos","doi":"10.1109/ISQED.2010.5450391","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450391","url":null,"abstract":"Circuit design under process variation can be formulated mathematically as a robust optimization problem with a yield constraint. Existing methods force designers to either resort to overly simplified circuit performance model, or rely on simplistic variability assumptions. On the other hand, accurate yield estimation must incorporate a sophisticated variability model that recognizes both systematic and random components at various levels of hierarchy. Unfortunately, such models are not compatible with existing optimization solutions. To solve the problem, we propose the sequential geometric programming method, which consists of iterative usage of geometric programming and importance sampling, and is capable of handling an arbitrary variability model. The proposed method is shown to be able to achieve the desired yield without overdesign, and solve circuits with thousands of gates within reasonable amount of time.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116797808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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