Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450507
Jian-wei Fang, S. Sapatnekar
In this paper we first develop an analytic closed-form model for the failure probability (FP) of a large digital circuit due to gate oxide breakdown. Our approach accounts for the fact that not every breakdown leads to circuit failure, and shows a 6–11× relaxation of the predicted lifetime with respect to the ultra-pessimistic area-scaling method. Next, we develop a posynomial-based optimization approach to perform gate sizing for oxide reliability in addition to timing and area.
{"title":"Scalable methods for the analysis and optimization of gate oxide breakdown","authors":"Jian-wei Fang, S. Sapatnekar","doi":"10.1109/ISQED.2010.5450507","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450507","url":null,"abstract":"In this paper we first develop an analytic closed-form model for the failure probability (FP) of a large digital circuit due to gate oxide breakdown. Our approach accounts for the fact that not every breakdown leads to circuit failure, and shows a 6–11× relaxation of the predicted lifetime with respect to the ultra-pessimistic area-scaling method. Next, we develop a posynomial-based optimization approach to perform gate sizing for oxide reliability in addition to timing and area.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128775440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450508
Hiroaki Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye
NBTI degradation proceeds while a negative bias is applied to the gate of PMOS, whereas it recovers while a positive bias is applied. Therefore, PMOS stress (ON) probability has a strong impact on circuit timing degradation due to NBTI effect. This paper evaluates how the granularity of stress probability calculation affects NBTI prediction using the state-of-the-art long term prediction model. Experimental results show that the prediction accuracy of timing degradation due to NBTI effect is heavily dependent on granularity of stress probability consideration in timing analysis.
{"title":"Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration","authors":"Hiroaki Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye","doi":"10.1109/ISQED.2010.5450508","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450508","url":null,"abstract":"NBTI degradation proceeds while a negative bias is applied to the gate of PMOS, whereas it recovers while a positive bias is applied. Therefore, PMOS stress (ON) probability has a strong impact on circuit timing degradation due to NBTI effect. This paper evaluates how the granularity of stress probability calculation affects NBTI prediction using the state-of-the-art long term prediction model. Experimental results show that the prediction accuracy of timing degradation due to NBTI effect is heavily dependent on granularity of stress probability consideration in timing analysis.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125436918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450524
Tongquan Wei, Yonghe Guo, Xiaodao Chen, Shiyan Hu
This paper proposes an adaptive energy efficient task allocation scheme for a multiprocessor system-on-a-chip (SoC) in real-time energy harvesting systems. The proposed scheme generates an energy efficient offline task schedule for a multiprocessor SoC energy harvesting system by balancing application workload among multiple processing elements and pushing real-time application towards their deadlines. The off-line task schedule is dynamically extended to adapt to the energy availability in the runtime to improve the probability of a task to be feasibly scheduled. Simulation experiments show that the proposed scheme achieves energy savings of up to 24%, and reduces task deadline miss ratio of up to 10%.
{"title":"Adaptive task allocation for multiprocessor SoCs","authors":"Tongquan Wei, Yonghe Guo, Xiaodao Chen, Shiyan Hu","doi":"10.1109/ISQED.2010.5450524","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450524","url":null,"abstract":"This paper proposes an adaptive energy efficient task allocation scheme for a multiprocessor system-on-a-chip (SoC) in real-time energy harvesting systems. The proposed scheme generates an energy efficient offline task schedule for a multiprocessor SoC energy harvesting system by balancing application workload among multiple processing elements and pushing real-time application towards their deadlines. The off-line task schedule is dynamically extended to adapt to the energy availability in the runtime to improve the probability of a task to be feasibly scheduled. Simulation experiments show that the proposed scheme achieves energy savings of up to 24%, and reduces task deadline miss ratio of up to 10%.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114197058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450474
Avinash Lakshminarayana, Sumit Ahuja, S. Shukla
Hardware/software co-design has been an area of research for a few decades. Currently co-design is utilized to create hardware coprocessors for compute intensive tasks of a system (which otherwise, performed in software, will not meet the performance goals). Design of correct hardware coprocessors with area, timing and power constraints is a time consuming task. In this paper, we present a methodology to alleviate this problem up to a certain extent. First, we show how to adopt a high-level synthesis tool in design space exploration to converge towards efficient hardware coprocessors. Second, we show, through a series of case studies that, a system-level approach, keeping platform specific optimizations in mind, can help in doing such an exploration efficiently.
{"title":"Coprocessor design space exploration using high level synthesis","authors":"Avinash Lakshminarayana, Sumit Ahuja, S. Shukla","doi":"10.1109/ISQED.2010.5450474","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450474","url":null,"abstract":"Hardware/software co-design has been an area of research for a few decades. Currently co-design is utilized to create hardware coprocessors for compute intensive tasks of a system (which otherwise, performed in software, will not meet the performance goals). Design of correct hardware coprocessors with area, timing and power constraints is a time consuming task. In this paper, we present a methodology to alleviate this problem up to a certain extent. First, we show how to adopt a high-level synthesis tool in design space exploration to converge towards efficient hardware coprocessors. Second, we show, through a series of case studies that, a system-level approach, keeping platform specific optimizations in mind, can help in doing such an exploration efficiently.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"21 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120928338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450427
P. Petrashin, G. Peretti, E. Romero
In this work, we explore the ability of OBT for testing OTA-C filters with a more complex OTA configuration than in previously reported one. Adopting a second-order structure as a case study, we use a non-linear block in the feedback loop in order to force the oscillations. The evaluation of the test quality is made by fault simulation. The simulation results show that the filter present very good fault coverage values.
{"title":"OBT implementation on an OTA-C band-pass filter","authors":"P. Petrashin, G. Peretti, E. Romero","doi":"10.1109/ISQED.2010.5450427","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450427","url":null,"abstract":"In this work, we explore the ability of OBT for testing OTA-C filters with a more complex OTA configuration than in previously reported one. Adopting a second-order structure as a case study, we use a non-linear block in the feedback loop in order to force the oscillations. The evaluation of the test quality is made by fault simulation. The simulation results show that the filter present very good fault coverage values.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116071107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450487
Sanghamitra Roy, Koushik Chakraborty
Three dimensional integrated circuits present an intriguing challenge for both circuit and system engineers due to their diverse cooling efficiency among the stacked dies. Several recent proposals advocate multiple techniques for thermal management of 3D ICs at different levels of the design, while operating within the confines of thermal heterogeneity. In this paper, we analyze for the first time, the role of thermal heterogeneity on the energy efficiency of the system by incorporating temperature dependent leakage power.We develop a novel convex optimization framework to optimize the energy efficiency in 3D ICs incorporating: (a) leakage aware thermal provisioning using temperature dependent full-chip leakage model, (b) heat flow in vertically stacked systems using a grid based compact thermal model, and (c) a concrete application for workload provisioning in 3D multicore systems. Detailed simulation based experiments with our proposed optimization framework shows 3–15% improvement in the energy efficiency of a typical multicore system organized as 3D stacked dies.
{"title":"A convex optimization framework for leakage aware thermal provisioning in 3D multicore architectures","authors":"Sanghamitra Roy, Koushik Chakraborty","doi":"10.1109/ISQED.2010.5450487","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450487","url":null,"abstract":"Three dimensional integrated circuits present an intriguing challenge for both circuit and system engineers due to their diverse cooling efficiency among the stacked dies. Several recent proposals advocate multiple techniques for thermal management of 3D ICs at different levels of the design, while operating within the confines of thermal heterogeneity. In this paper, we analyze for the first time, the role of thermal heterogeneity on the energy efficiency of the system by incorporating temperature dependent leakage power.We develop a novel convex optimization framework to optimize the energy efficiency in 3D ICs incorporating: (a) leakage aware thermal provisioning using temperature dependent full-chip leakage model, (b) heat flow in vertically stacked systems using a grid based compact thermal model, and (c) a concrete application for workload provisioning in 3D multicore systems. Detailed simulation based experiments with our proposed optimization framework shows 3–15% improvement in the energy efficiency of a typical multicore system organized as 3D stacked dies.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121170943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450551
Yang Liu, Jibang Liu, Tong Zhang
This paper concerns the design of low power digital signal processing integrated circuits in the presence of significant process variations. The basic idea is to leave smaller-than-worst-case timing margin for improving energy efficiency during the design phase and selectively reduce the finite word-length of circuit datapaths in post-silicon to eliminate all the timing faults during the run time. This simple idea can be intuitively justified by the fact that process variations may render only a few post-silicon datapaths to timing faults, while reducing the finite word-length of a few datapaths in signal processing systems may not necessarily make the overall algorithm-level performance unacceptable in run time. We present a design flow to implement this method and propose a dual finite word-length configuration strategy to simplify its real-life realization. Using linear low-pass filter and Turbo code decoder design at 45nm node as case studies, we quantitatively demonstrate that this adaptive finite word-length configuration design strategy may effectively relax the timing margin and accordingly reduce the power consumption by over 18% over conventional worst-case design approach.
{"title":"Design of low-power variation tolerant signal processing systems with adaptive finite word-length configuration","authors":"Yang Liu, Jibang Liu, Tong Zhang","doi":"10.1109/ISQED.2010.5450551","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450551","url":null,"abstract":"This paper concerns the design of low power digital signal processing integrated circuits in the presence of significant process variations. The basic idea is to leave smaller-than-worst-case timing margin for improving energy efficiency during the design phase and selectively reduce the finite word-length of circuit datapaths in post-silicon to eliminate all the timing faults during the run time. This simple idea can be intuitively justified by the fact that process variations may render only a few post-silicon datapaths to timing faults, while reducing the finite word-length of a few datapaths in signal processing systems may not necessarily make the overall algorithm-level performance unacceptable in run time. We present a design flow to implement this method and propose a dual finite word-length configuration strategy to simplify its real-life realization. Using linear low-pass filter and Turbo code decoder design at 45nm node as case studies, we quantitatively demonstrate that this adaptive finite word-length configuration design strategy may effectively relax the timing margin and accordingly reduce the power consumption by over 18% over conventional worst-case design approach.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131251132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450407
K. Usami, T. Hashida, S. Koyama, Tatsuya Yamamoto, D. Ikebuchi, H. Amano, M. Namiki, Masaaki Kondo, Hiroshi Nakamura
This paper describes adaptive fine-grain control to power gate function units based on temperature dependent break-even time (BET). An analytical model to express the temperature dependent BET is introduced and the accuracy of the model was examined. Results demonstrated that the model well represents the exponential decrease in BET with the temperature. Meanwhile, it was found that the accuracy gets worse at higher temperature and the cause is energy dissipation due to transient glitch at the wakeup. We propose four power-gating policies employing time-based or history-based approaches. Effectiveness in energy savings was evaluated using real design data of four function units in a microprocessor implemented in a 65nm technology. Results showed that introducing adaptive control to make use of temperature-dependent BET enhances energy savings by up to 21% in the time-based approach and by up to 18% in the history-based approach. The adaptive history-based policy with a limiter outperforms the adaptive time-based policy in energy savings and reduces the total energy of four function units to 11.8% at 100°C as compared to the non-power-gating case.
{"title":"Adaptive power gating for function units in a microprocessor","authors":"K. Usami, T. Hashida, S. Koyama, Tatsuya Yamamoto, D. Ikebuchi, H. Amano, M. Namiki, Masaaki Kondo, Hiroshi Nakamura","doi":"10.1109/ISQED.2010.5450407","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450407","url":null,"abstract":"This paper describes adaptive fine-grain control to power gate function units based on temperature dependent break-even time (BET). An analytical model to express the temperature dependent BET is introduced and the accuracy of the model was examined. Results demonstrated that the model well represents the exponential decrease in BET with the temperature. Meanwhile, it was found that the accuracy gets worse at higher temperature and the cause is energy dissipation due to transient glitch at the wakeup. We propose four power-gating policies employing time-based or history-based approaches. Effectiveness in energy savings was evaluated using real design data of four function units in a microprocessor implemented in a 65nm technology. Results showed that introducing adaptive control to make use of temperature-dependent BET enhances energy savings by up to 21% in the time-based approach and by up to 18% in the history-based approach. The adaptive history-based policy with a limiter outperforms the adaptive time-based policy in energy savings and reduces the total energy of four function units to 11.8% at 100°C as compared to the non-power-gating case.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133373393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450421
Fan Wang, V. Agrawal
We analyze the neutron induced soft error rate (SER) by modeling induced error pulse using two parameters, occurrence frequency and probability density function for the pulse width. We extend the analysis to sequential logic and latches and calculate the failures in time (FIT) rate. The analysis is developed for the available background neutron flux data, which is experimentally determined. This, along with the device characteristics, gives the induced pulse parameters. A gate-level algorithm propagates the pulse parameters through logic gates. This algorithm correctly models the logic masking of error pulses. We introduce the concept of latching window that accurately models the temporal masking by sequential elements and present an algorithm for SER analysis of sequential logic.
{"title":"Soft error rate determination for nanoscale sequential logic","authors":"Fan Wang, V. Agrawal","doi":"10.1109/ISQED.2010.5450421","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450421","url":null,"abstract":"We analyze the neutron induced soft error rate (SER) by modeling induced error pulse using two parameters, occurrence frequency and probability density function for the pulse width. We extend the analysis to sequential logic and latches and calculate the failures in time (FIT) rate. The analysis is developed for the available background neutron flux data, which is experimentally determined. This, along with the device characteristics, gives the induced pulse parameters. A gate-level algorithm propagates the pulse parameters through logic gates. This algorithm correctly models the logic masking of error pulses. We introduce the concept of latching window that accurately models the temporal masking by sequential elements and present an algorithm for SER analysis of sequential logic.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115782917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450533
Y. Hu, Yin Lin Chung, Mely Chen Chi
In this paper, we propose a multilevel multilayer partitioning algorithm for 3D ICs application. The algorithm is based on the multilevel framework to coarsen the netlist successively. A multilayer partitioning procedure is applied on each level of partition during the un-coarsening process. The objective is to minimize the total number of Through Silicon Via (TSV) while observing the area constraint for each layer. The area of each layer is the summation of circuit area and TSV area. The partitioning algorithm is customized for the structure of 3D ICs. We utilize a FM-like data structure and identify eight critical net distributions such that after a cell move, the program can update gains very effectively. The experimental results show that the proposed algorithm can effectively produce good results with small numbers of TSV, area overhead, and area coefficient of variation for the tested industrial cases. The average area overhead is only 1.84% that shows the average white space is very small. The average area coefficient of variation is only 2.61% that shows area distribution of all layers is very uniform. The results also achieve the best average value for both number of TSVs and chip area, compared to all participating teams in “Design Partition for 3D ICs” problem in the IC/CAD 2009 contest in Taiwan.
{"title":"A multilevel multilayer partitioning algorithm for three dimensional integrated circuits","authors":"Y. Hu, Yin Lin Chung, Mely Chen Chi","doi":"10.1109/ISQED.2010.5450533","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450533","url":null,"abstract":"In this paper, we propose a multilevel multilayer partitioning algorithm for 3D ICs application. The algorithm is based on the multilevel framework to coarsen the netlist successively. A multilayer partitioning procedure is applied on each level of partition during the un-coarsening process. The objective is to minimize the total number of Through Silicon Via (TSV) while observing the area constraint for each layer. The area of each layer is the summation of circuit area and TSV area. The partitioning algorithm is customized for the structure of 3D ICs. We utilize a FM-like data structure and identify eight critical net distributions such that after a cell move, the program can update gains very effectively. The experimental results show that the proposed algorithm can effectively produce good results with small numbers of TSV, area overhead, and area coefficient of variation for the tested industrial cases. The average area overhead is only 1.84% that shows the average white space is very small. The average area coefficient of variation is only 2.61% that shows area distribution of all layers is very uniform. The results also achieve the best average value for both number of TSVs and chip area, compared to all participating teams in “Design Partition for 3D ICs” problem in the IC/CAD 2009 contest in Taiwan.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134216587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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