Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229106
H. Chou, P. Su, J. Ng, P. L. Wang, H. T. Lu, C. J. Lee, W. Syue, S. Y. Yang, Y. Tseng, C. C. Cheng, C. Yao, R. Liou, Y. Jong, J. Tsai, J. Cai, H. Tuan, Chih-Fang Huang, J. Gong
This paper presents a single BCD technology platform with high performance power devices at a wide range of operating voltages. The platform offers 6 V to 70 V LDMOS devices. All devices offer best-in-class specific on-resistance of 20 to 40 % lower than that of the state-of-the-art IC-based LDMOS devices and robustness better than the square SOA (safe-operating-area). Fully isolated LDMOS devices, in which independent bias is capable for circuit flexibility, demonstrate superior specific on-resistance (e.g. 11.9 mΩ-mm2 for breakdown voltage of 39 V). Moreover, the unusual sudden current enhancement appeared in the ID-VD saturation region of most of the high voltage LDMOS devices is significantly suppressed.
{"title":"0.18 µm BCD technology platform with best-in-class 6 V to 70 V power MOSFETs","authors":"H. Chou, P. Su, J. Ng, P. L. Wang, H. T. Lu, C. J. Lee, W. Syue, S. Y. Yang, Y. Tseng, C. C. Cheng, C. Yao, R. Liou, Y. Jong, J. Tsai, J. Cai, H. Tuan, Chih-Fang Huang, J. Gong","doi":"10.1109/ISPSD.2012.6229106","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229106","url":null,"abstract":"This paper presents a single BCD technology platform with high performance power devices at a wide range of operating voltages. The platform offers 6 V to 70 V LDMOS devices. All devices offer best-in-class specific on-resistance of 20 to 40 % lower than that of the state-of-the-art IC-based LDMOS devices and robustness better than the square SOA (safe-operating-area). Fully isolated LDMOS devices, in which independent bias is capable for circuit flexibility, demonstrate superior specific on-resistance (e.g. 11.9 mΩ-mm2 for breakdown voltage of 39 V). Moreover, the unusual sudden current enhancement appeared in the ID-VD saturation region of most of the high voltage LDMOS devices is significantly suppressed.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130462424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229094
A. Haertl, G. Soelkner, F. Pfirsch, W. Brekel, T. Duetemeyer
For the first time, experiments and simulations for testing the influence of dynamic switching on the robustness of power devices against cosmic radiation are presented. Irradiation experiments of switching high power modules are performed, using pulsed proton or neutron beams. Thereby, the switching frequency of the power modules is synchronized to the extraction frequency of particle beam pulses from the synchrotron. With this new experimental approach both 6.5kV IGBTs and free-wheeling diodes are studied under various switching conditions. Employing these experiments and also simulations based on semi-empirical models, we find a non-negligible contribution of these dynamic effects on the failure rate of high power devices induced by high-energy nucleon irradiation.
{"title":"Influence of dynamic switching on the robustness of power devices against cosmic radiation","authors":"A. Haertl, G. Soelkner, F. Pfirsch, W. Brekel, T. Duetemeyer","doi":"10.1109/ISPSD.2012.6229094","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229094","url":null,"abstract":"For the first time, experiments and simulations for testing the influence of dynamic switching on the robustness of power devices against cosmic radiation are presented. Irradiation experiments of switching high power modules are performed, using pulsed proton or neutron beams. Thereby, the switching frequency of the power modules is synchronized to the extraction frequency of particle beam pulses from the synchrotron. With this new experimental approach both 6.5kV IGBTs and free-wheeling diodes are studied under various switching conditions. Employing these experiments and also simulations based on semi-empirical models, we find a non-negligible contribution of these dynamic effects on the failure rate of high power devices induced by high-energy nucleon irradiation.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130665614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229110
P. Steeneken, O. Wunnicke
Advances in semiconductor technology have brought the performance of power transistors near the physical limit. Substantial performance enhancement of power switches will therefore require either new materials, or new devices that obey fundamentally different limits. One of the new power devices that might offer an alternative to the transistor is the microelectromechanical (MEMS) switch. Here we analyze the potential of metal-contact MEMS switches for power electronics by exploring their physical performance limits and by benchmarking them against transistors. Based on a semi-empirical model we show that MEMS switches could outperform Si transistors for actuation voltages Vact>;30 V and could even beat GaN for Vact>;1000 V. Therefore we conclude that MEMS switch technology potentially offers an interesting alternative route towards high performance power devices, although switching time and safe operating area remain points of concern.
{"title":"Performance limits of MEMS switches for power electronics","authors":"P. Steeneken, O. Wunnicke","doi":"10.1109/ISPSD.2012.6229110","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229110","url":null,"abstract":"Advances in semiconductor technology have brought the performance of power transistors near the physical limit. Substantial performance enhancement of power switches will therefore require either new materials, or new devices that obey fundamentally different limits. One of the new power devices that might offer an alternative to the transistor is the microelectromechanical (MEMS) switch. Here we analyze the potential of metal-contact MEMS switches for power electronics by exploring their physical performance limits and by benchmarking them against transistors. Based on a semi-empirical model we show that MEMS switches could outperform Si transistors for actuation voltages Vact>;30 V and could even beat GaN for Vact>;1000 V. Therefore we conclude that MEMS switch technology potentially offers an interesting alternative route towards high performance power devices, although switching time and safe operating area remain points of concern.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"46 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134226432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229091
R. Reiner, P. Waltereit, F. Benkhelifa, S. Muller, S. Müller, H. Walcher, S. Wagner, R. Quay, M. Schlechtweg, O. Ambacher
This work introduces a new design approach for the use of fractal structures for low-resistance large area transistors structures. Aspects of layout with adapted current density and high-area utilization are considered. Furthermore the work presents a realization of fractal structures in AlGaN/GaN technology. Both static and dynamic behaviors are characterized. The fabricated devices achieve a breakdown voltage of VBR >; 700V and on-state currents of ID = 40A at VGS = 1V.
{"title":"Fractal structures for low-resistance large area AlGaN/GaN power transistors","authors":"R. Reiner, P. Waltereit, F. Benkhelifa, S. Muller, S. Müller, H. Walcher, S. Wagner, R. Quay, M. Schlechtweg, O. Ambacher","doi":"10.1109/ISPSD.2012.6229091","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229091","url":null,"abstract":"This work introduces a new design approach for the use of fractal structures for low-resistance large area transistors structures. Aspects of layout with adapted current density and high-area utilization are considered. Furthermore the work presents a realization of fractal structures in AlGaN/GaN technology. Both static and dynamic behaviors are characterized. The fabricated devices achieve a breakdown voltage of VBR >; 700V and on-state currents of ID = 40A at VGS = 1V.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132640376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229097
R. Baburske, F. Niedernostheide, E. Falck, J. Lutz, H. Schulze, J. Bauer
Simulation results show how cathode-side filaments may trigger a thermal runaway at the end of a reverse-recovery period of diodes turned off with extremely high current rates. The mechanism is not essentially affected by the edge termination if an appropriate design is chosen. While multiple avalanche-induced filaments may appear during the reverse-recovery period, at the end of the turn-off phase a single “winning” filament carries the total current. This can result in a local melting of the diode. The appearance of a cathode-side filament by itself does not necessarily lead to the diode destruction. However, a high thermal carrier generation rate can result in an uncontrollable increase of the current density in a single filament connecting the anode and the cathode contact. It is shown t hat the reverse-recovery charge as a function of the dc-link voltage shows a characteristic super-linear increase below the critical value dc-link voltage at which the diode current increases uncontrollably.
{"title":"Destruction behavior of power diodes beyond the SOA limit","authors":"R. Baburske, F. Niedernostheide, E. Falck, J. Lutz, H. Schulze, J. Bauer","doi":"10.1109/ISPSD.2012.6229097","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229097","url":null,"abstract":"Simulation results show how cathode-side filaments may trigger a thermal runaway at the end of a reverse-recovery period of diodes turned off with extremely high current rates. The mechanism is not essentially affected by the edge termination if an appropriate design is chosen. While multiple avalanche-induced filaments may appear during the reverse-recovery period, at the end of the turn-off phase a single “winning” filament carries the total current. This can result in a local melting of the diode. The appearance of a cathode-side filament by itself does not necessarily lead to the diode destruction. However, a high thermal carrier generation rate can result in an uncontrollable increase of the current density in a single filament connecting the anode and the cathode contact. It is shown t hat the reverse-recovery charge as a function of the dc-link voltage shows a characteristic super-linear increase below the critical value dc-link voltage at which the diode current increases uncontrollably.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114405132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229105
M. Venturato, G. Cantone, F. Ronchi, F. Toia
Here is presented the development of the new BCD800 platform which conjugates 3.3V CMOS logic, 5/25/30V power devices and a 800V nLDMOS in a 0.35μm technology node. LV components can be placed into a floating pocket which can be referred up to 650V, furthermore this process features an innovative lateral junction isolation module obtained by a boron-doped poly-filled deep trench with great advantages in terms of performances and area saving. The process industrialization has been demonstrated and a fully functional test vehicle is available in the form of a single-chip High Voltage Smart Gate Driver for half bridges.
{"title":"A novel 0.35µm 800V BCD technology platform for offline applications","authors":"M. Venturato, G. Cantone, F. Ronchi, F. Toia","doi":"10.1109/ISPSD.2012.6229105","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229105","url":null,"abstract":"Here is presented the development of the new BCD800 platform which conjugates 3.3V CMOS logic, 5/25/30V power devices and a 800V nLDMOS in a 0.35μm technology node. LV components can be placed into a floating pocket which can be referred up to 650V, furthermore this process features an innovative lateral junction isolation module obtained by a boron-doped poly-filled deep trench with great advantages in terms of performances and area saving. The process industrialization has been demonstrated and a fully functional test vehicle is available in the form of a single-chip High Voltage Smart Gate Driver for half bridges.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123765749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229099
F. Masuoka, K. Nakamura, A. Nishii, T. Terashima
In the fast recovery operation of Free-wheeling Diode (FWD), to reduce voltage surge “snap-off”, we propose the Relaxed Field of Cathode (RFC)-planar anode diode in the range of 600 V to 1700 V. RFC effect is described by the parallel connection of pin diode and pnp transistor in as a single chip solution. Its structure is realized by our thin wafer process technology utilizing the backside lithography to make p/n alternating pattern after thining the wafer. As the result, our RFC diode up to 1700 V has the following three advantages comparing with the conventional one: (a) 40% lower recovery loss (EREC), 30% lower forward voltage drop (VF), (b) a large recovery Safe Operating Area (SOA) with the high peak power density of 1.4W/cm2 and (c) easiness to adjust a lower crosspoint below rated current density in the output I-V. Therefore, the proposed RFC diode has a great potential as the next generation Si FWD in the all voltage range.
{"title":"Great impact of RFC technology on fast recovery diode towards 600 V for low loss and high dynamic ruggedness","authors":"F. Masuoka, K. Nakamura, A. Nishii, T. Terashima","doi":"10.1109/ISPSD.2012.6229099","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229099","url":null,"abstract":"In the fast recovery operation of Free-wheeling Diode (FWD), to reduce voltage surge “snap-off”, we propose the Relaxed Field of Cathode (RFC)-planar anode diode in the range of 600 V to 1700 V. RFC effect is described by the parallel connection of pin diode and pnp transistor in as a single chip solution. Its structure is realized by our thin wafer process technology utilizing the backside lithography to make p/n alternating pattern after thining the wafer. As the result, our RFC diode up to 1700 V has the following three advantages comparing with the conventional one: (a) 40% lower recovery loss (EREC), 30% lower forward voltage drop (VF), (b) a large recovery Safe Operating Area (SOA) with the high peak power density of 1.4W/cm2 and (c) easiness to adjust a lower crosspoint below rated current density in the output I-V. Therefore, the proposed RFC diode has a great potential as the next generation Si FWD in the all voltage range.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130533944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229020
B. de Jaeger, M. Van Hove, D. Wellekens, X. Kang, H. Liang, G. Mannaert, K. Geens, S. Decoutere
Au-free CMOS-compatible AlGaN/GaN HEMT devices have been processed on 200 mm Si substrates u sing a typical CMOS tool set. This paper addresses the challenges with respect to the AlGaN/GaN epitaxy, the processing of thick and bowed 200 mm GaN-on-Si wafers, the impact of Ga contamination on the tools, etc.. An enhancement mode AlGaN/GaN MISHEMT process based on barrier recess is used as demonstrator, and yielded fully functional power devices.
使用典型的CMOS工具集，在200 mm Si衬底上加工了无金CMOS兼容的AlGaN/GaN HEMT器件。本文讨论了AlGaN/GaN外延、厚度和弯曲200mm GaN-on- si晶圆的加工、Ga污染对工具的影响等方面的挑战。以一种基于势垒凹槽的增强模式AlGaN/GaN MISHEMT工艺为演示，生产出功能齐全的功率器件。
{"title":"Au-free CMOS-compatible AlGaN/GaN HEMT processing on 200 mm Si substrates","authors":"B. de Jaeger, M. Van Hove, D. Wellekens, X. Kang, H. Liang, G. Mannaert, K. Geens, S. Decoutere","doi":"10.1109/ISPSD.2012.6229020","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229020","url":null,"abstract":"Au-free CMOS-compatible AlGaN/GaN HEMT devices have been processed on 200 mm Si substrates u sing a typical CMOS tool set. This paper addresses the challenges with respect to the AlGaN/GaN epitaxy, the processing of thick and bowed 200 mm GaN-on-Si wafers, the impact of Ga contamination on the tools, etc.. An enhancement mode AlGaN/GaN MISHEMT process based on barrier recess is used as demonstrator, and yielded fully functional power devices.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132150228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229055
J. M. Park, M. Knaipp, H. Enichlmair, R. Minixhofer, Yun Shi, N. Feilchenfeld
This work reports the hot-carrier (HC) behavior and specific on-resistance (Ron,sp) optimization of 20~60 V p-channel LDMOS transistors implemented in a 180 nm HV-CMOS technology. By precise control the implant dose and energy of a p-drift region, which is surrounded by n-type isolation well, one can efficiently optimize the on-resistance and breakdown voltage (BV) trade-off while keeping very low HC degradation. Both of the TCAD simulations and measurements are described to explain the proposed technology and the transistor behaviour. Reported p-channel LDMOS transistor (pLDMOS) shows a very low HC-induced degradation - percent change of linear region of drain current (Idlin) below 3 % till 1×105 sec stress), and it shows an excellent Ron,sp-BV trade-off (pLDMOS with 20V GOX: BV = -85 V and Ron,sp = 1.64 mΩ-cm2).
{"title":"Hot-carrier behaviour and ron-BV trade-off optimization for p-channel LDMOS transistors in a 180 nm HV-CMOS technology","authors":"J. M. Park, M. Knaipp, H. Enichlmair, R. Minixhofer, Yun Shi, N. Feilchenfeld","doi":"10.1109/ISPSD.2012.6229055","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229055","url":null,"abstract":"This work reports the hot-carrier (HC) behavior and specific on-resistance (Ron,sp) optimization of 20~60 V p-channel LDMOS transistors implemented in a 180 nm HV-CMOS technology. By precise control the implant dose and energy of a p-drift region, which is surrounded by n-type isolation well, one can efficiently optimize the on-resistance and breakdown voltage (BV) trade-off while keeping very low HC degradation. Both of the TCAD simulations and measurements are described to explain the proposed technology and the transistor behaviour. Reported p-channel LDMOS transistor (pLDMOS) shows a very low HC-induced degradation - percent change of linear region of drain current (Idlin) below 3 % till 1×105 sec stress), and it shows an excellent Ron,sp-BV trade-off (pLDMOS with 20V GOX: BV = -85 V and Ron,sp = 1.64 mΩ-cm2).","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125921219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229010
H. Ohashi
It is confirmed that more electric society is right direction toward sustainable growth achievement. Electronics including power electronics which enables efficient energy usage is important key technology for the society. Nega-watt cost concept, as an index of development, is proposed to promote efficiency improvement and prevalence of the next generation power electronics (PEs). Improvement of power density and watt cost are key factors for nega-watt cost down. Seed technologies are discussed from system integration point of view. In terms of manufacturability, the importance of high quality wafer supply is mentioned. Finally strategies of Japan for the PEs are referred.
{"title":"Power devices now and future, strategy of Japan","authors":"H. Ohashi","doi":"10.1109/ISPSD.2012.6229010","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229010","url":null,"abstract":"It is confirmed that more electric society is right direction toward sustainable growth achievement. Electronics including power electronics which enables efficient energy usage is important key technology for the society. Nega-watt cost concept, as an index of development, is proposed to promote efficiency improvement and prevalence of the next generation power electronics (PEs). Improvement of power density and watt cost are key factors for nega-watt cost down. Seed technologies are discussed from system integration point of view. In terms of manufacturability, the importance of high quality wafer supply is mentioned. Finally strategies of Japan for the PEs are referred.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124693215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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