Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229061
N. Sakurai, K. Takami, S. Yukutake, Y. Kouno, J. Sakano
A 4.5-kV voltage level-shift circuit with a multi-chip structure composed of upper and lower arm driver ICs and dedicated discrete IGBTs was developed. It was experimentally confirmed that this level-shift circuit could drive a 3.3-kV/1200-A IGBT module.
{"title":"4.5-kV multi-chip level-shift circuit using dedicated discrete IGBTs for driving high-power IGBTs","authors":"N. Sakurai, K. Takami, S. Yukutake, Y. Kouno, J. Sakano","doi":"10.1109/ISPSD.2012.6229061","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229061","url":null,"abstract":"A 4.5-kV voltage level-shift circuit with a multi-chip structure composed of upper and lower arm driver ICs and dedicated discrete IGBTs was developed. It was experimentally confirmed that this level-shift circuit could drive a 3.3-kV/1200-A IGBT module.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126123144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229058
M. Qiao, Yitao He, Heng-juan Wen, Xin Zhou, Lingli Jiang, Huaping Jiang, X. Luo, Zhaoji Li, Bo Zhang, Zhengcai Chen, Yuxuan Su, Zhiqiang Xiao, Cheng Wang
A novel HV thin layer SOI technology based on 1.5-μm-thick silicon layer for negative HV power supply has been first proposed. HV field nLDMOS with thick gate oxide, HV pLDMOS with thin gate oxide and LV CMOS are compatible with shallow trench isolation. Gate and source field plates are adopted to improve the breakdown characteristics of HV field nLDMOS since it doesn't meet SOI RESURF criterion. N-field with shallow junction depth is introduced to eliminate channel discontinuity around the “beak” region at the source side of HV field nLDMOS and avoid punch-through breakdown induced by BG effect of HV field nLDMOS. The influences of key parameters on breakdown mechanism are discussed and optimal parameters are obtained to achieve well characteristics of HV field nLDMOS for negative HV power supply. A negative HV switching IC using the proposed thin layer SOI technology shows that both the rise and fall times of the output stages are less than 50 ns under the negative supply voltage of -100 V and the load capacitance of 5000 pF.
{"title":"High-voltage thin layer SOI technology for negative power supply","authors":"M. Qiao, Yitao He, Heng-juan Wen, Xin Zhou, Lingli Jiang, Huaping Jiang, X. Luo, Zhaoji Li, Bo Zhang, Zhengcai Chen, Yuxuan Su, Zhiqiang Xiao, Cheng Wang","doi":"10.1109/ISPSD.2012.6229058","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229058","url":null,"abstract":"A novel HV thin layer SOI technology based on 1.5-μm-thick silicon layer for negative HV power supply has been first proposed. HV field nLDMOS with thick gate oxide, HV pLDMOS with thin gate oxide and LV CMOS are compatible with shallow trench isolation. Gate and source field plates are adopted to improve the breakdown characteristics of HV field nLDMOS since it doesn't meet SOI RESURF criterion. N-field with shallow junction depth is introduced to eliminate channel discontinuity around the “beak” region at the source side of HV field nLDMOS and avoid punch-through breakdown induced by BG effect of HV field nLDMOS. The influences of key parameters on breakdown mechanism are discussed and optimal parameters are obtained to achieve well characteristics of HV field nLDMOS for negative HV power supply. A negative HV switching IC using the proposed thin layer SOI technology shows that both the rise and fall times of the output stages are less than 50 ns under the negative supply voltage of -100 V and the load capacitance of 5000 pF.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130059447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229047
L. Storasta, S. Matthias, A. Kopta, Munaf T. A. Rahimo
In this paper we present the detailed investigation of the influence of the internal bipolar PNP transistor gain on the thermal stability of high voltage IGBTs and BiGTs. The bipolar gain is controlled by means of anode and buffer design and by the introduction of anode shorts. The influence of the different buffer and anode doping profiles and the different layouts in the case of anode-shorted designs are analyzed. Temperature dependent leakage current measurements confirm that the lowering of the leakage current and its subsequent weak temperature dependency can be achieved by buffer and anode engineering albeit with certain design trade-off restrictions. Nevertheless, another effective approach for suppressing the leakage current and its dependency on temperature is achieved by the introduction of anode shorts as demonstrated in reverse conducting IGBT or BiGT structures. Such designs eliminate to a large extent the internal bipolar transistor action in the BiGT anode shorted designs while allowing different anode and buffer doping profiles for the design trade-offs. Despite the fact that the lifetime control in the BiGT drift region causes the leakage current to increase, the temperature coefficient remains unchanged, hence, making the hard switched BiGT suitable for high temperature operation.
{"title":"Bipolar transistor gain influence on the high temperature thermal stability of HV-BiGTs","authors":"L. Storasta, S. Matthias, A. Kopta, Munaf T. A. Rahimo","doi":"10.1109/ISPSD.2012.6229047","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229047","url":null,"abstract":"In this paper we present the detailed investigation of the influence of the internal bipolar PNP transistor gain on the thermal stability of high voltage IGBTs and BiGTs. The bipolar gain is controlled by means of anode and buffer design and by the introduction of anode shorts. The influence of the different buffer and anode doping profiles and the different layouts in the case of anode-shorted designs are analyzed. Temperature dependent leakage current measurements confirm that the lowering of the leakage current and its subsequent weak temperature dependency can be achieved by buffer and anode engineering albeit with certain design trade-off restrictions. Nevertheless, another effective approach for suppressing the leakage current and its dependency on temperature is achieved by the introduction of anode shorts as demonstrated in reverse conducting IGBT or BiGT structures. Such designs eliminate to a large extent the internal bipolar transistor action in the BiGT anode shorted designs while allowing different anode and buffer doping profiles for the design trade-offs. Despite the fact that the lifetime control in the BiGT drift region causes the leakage current to increase, the temperature coefficient remains unchanged, hence, making the hard switched BiGT suitable for high temperature operation.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124083263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229078
T. Erlbacher, H. Schwarzmann, A. Bauer, S. Berberich, J. vom Dorp, L. Frey
Monolithic integration of RC snubbers in power electronic applications offers great opportunities. The presented devices provide tight tolerances and enable high integration densities. Especially, the incorporation into power modules enables reduction of electromagnetic interferences in accordance with reliable lifetime predictions.
{"title":"Improving module performance and reliability in power electronic applications by monolithic integration of RC-snubbers","authors":"T. Erlbacher, H. Schwarzmann, A. Bauer, S. Berberich, J. vom Dorp, L. Frey","doi":"10.1109/ISPSD.2012.6229078","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229078","url":null,"abstract":"Monolithic integration of RC snubbers in power electronic applications offers great opportunities. The presented devices provide tight tolerances and enable high integration densities. Especially, the incorporation into power modules enables reduction of electromagnetic interferences in accordance with reliable lifetime predictions.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124293637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229012
M. Sumitomo, J. Asai, H. Sakane, K. Arakawa, Y. Higuchi, M. Matsui
A PNM (Partially Narrow Mesa) -IGBT with a fundamentally new surface is proposed for the first time. The unique gate shape looks like a “vase” and generates an extreme injection enhancement. Its performance approaches the limits of Si-IGBT. Therefore, PNM-IGBT is able to contribute to the saturation voltage reduction and the improvement of Vce(sat)-Eoff trade off. Furthermore, it can be adapted to actual conditions because of its sufficiently rugged structure.
{"title":"Low loss IGBT with Partially Narrow Mesa Structure (PNM-IGBT)","authors":"M. Sumitomo, J. Asai, H. Sakane, K. Arakawa, Y. Higuchi, M. Matsui","doi":"10.1109/ISPSD.2012.6229012","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229012","url":null,"abstract":"A PNM (Partially Narrow Mesa) -IGBT with a fundamentally new surface is proposed for the first time. The unique gate shape looks like a “vase” and generates an extreme injection enhancement. Its performance approaches the limits of Si-IGBT. Therefore, PNM-IGBT is able to contribute to the saturation voltage reduction and the improvement of Vce(sat)-Eoff trade off. Furthermore, it can be adapted to actual conditions because of its sufficiently rugged structure.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"270 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132228811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229009
L. Casey, L. Zubieta, J. Mossoba, B. Borowy, B. Semenov
Power electronic interfaces are vital to advanced, smarter, distributed grids and micro-grids and the capabilities and limitations of power devices are integral to this. This paper discusses existing and emerging applications of grid connected electronic interfaces that are enabled by Power Semiconductor Devices. The application focus will be on: (1) inverters, which are a key element of modern distributed and renewable energy systems; (2) solid-state transformers which hold great promise to reduce size and weight, while enhancing performance, compared to existing Grid transformers; (3) MV static transfer switches, which facilitate redundant power at the medium voltage level. Capabilities and tradeoffs between Power circuit topologies, available devices, and circuit techniques are presented. Existing and projected market opportunities are also presented, and motivation for future device development is outlined. Emerging transformative research using wide band gap devices in silicon-dominated power device applications, along with hybrid power switch configurations, will also be highlighted. The compelling requirement of advanced grids for both fast fault current limiting, fast voltage control, and possibly increased overload capability to enable the much heralded advances, are also shown to be completely dependent on devices, along with their cost effective application.
{"title":"Power devices for grid connections","authors":"L. Casey, L. Zubieta, J. Mossoba, B. Borowy, B. Semenov","doi":"10.1109/ISPSD.2012.6229009","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229009","url":null,"abstract":"Power electronic interfaces are vital to advanced, smarter, distributed grids and micro-grids and the capabilities and limitations of power devices are integral to this. This paper discusses existing and emerging applications of grid connected electronic interfaces that are enabled by Power Semiconductor Devices. The application focus will be on: (1) inverters, which are a key element of modern distributed and renewable energy systems; (2) solid-state transformers which hold great promise to reduce size and weight, while enhancing performance, compared to existing Grid transformers; (3) MV static transfer switches, which facilitate redundant power at the medium voltage level. Capabilities and tradeoffs between Power circuit topologies, available devices, and circuit techniques are presented. Existing and projected market opportunities are also presented, and motivation for future device development is outlined. Emerging transformative research using wide band gap devices in silicon-dominated power device applications, along with hybrid power switch configurations, will also be highlighted. The compelling requirement of advanced grids for both fast fault current limiting, fast voltage control, and possibly increased overload capability to enable the much heralded advances, are also shown to be completely dependent on devices, along with their cost effective application.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133602762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229051
Huaping Jiang, Bo Zhang, Wanjun Chen, Zhaoji Li, Congzhi Zheng, Chuang Liu, Z. Rao, B. Dong
A simple method to design the single-mask multi-zone junction termination extension (MZJTE) (SM-MZJTE) for high-voltage insulated-gate bipolar transistor (IGBT) is presented and experimentally demonstrated. By assuming that the p-type SM-MZJTE region is completely depleted and the equipotential lines are circular arcs for simplicity, an analytical model of the selective function is derived from the charge balance and the geometrical relations. As the blocking capability is sensitive to the implantation dose, the Boron segregation at Si-SiO2 interface has also been taken into consideration in this model. According to the analytical model, high-voltage IGBTs and test devices with edge termination of SM-MZJTE are fabricated. IGBTs with edge termination implantation dose of 3×1012 cm-2 show highest average breakdown voltage of 3.79 kV (about 92% of the parallel plane breakdown voltage).
{"title":"A simple method to design the single-mask multi-zone junction termination extension for high-voltage IGBT","authors":"Huaping Jiang, Bo Zhang, Wanjun Chen, Zhaoji Li, Congzhi Zheng, Chuang Liu, Z. Rao, B. Dong","doi":"10.1109/ISPSD.2012.6229051","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229051","url":null,"abstract":"A simple method to design the single-mask multi-zone junction termination extension (MZJTE) (SM-MZJTE) for high-voltage insulated-gate bipolar transistor (IGBT) is presented and experimentally demonstrated. By assuming that the p-type SM-MZJTE region is completely depleted and the equipotential lines are circular arcs for simplicity, an analytical model of the selective function is derived from the charge balance and the geometrical relations. As the blocking capability is sensitive to the implantation dose, the Boron segregation at Si-SiO2 interface has also been taken into consideration in this model. According to the analytical model, high-voltage IGBTs and test devices with edge termination of SM-MZJTE are fabricated. IGBTs with edge termination implantation dose of 3×1012 cm-2 show highest average breakdown voltage of 3.79 kV (about 92% of the parallel plane breakdown voltage).","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121202068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229075
O. Seok, W. Ahn, Young-shil Kim, M. Han, M. Ha
AlGaN/GaN metal insulator semiconductor high electron mobility transistors (MIS-HEMTs) employing rf sputtered Ga2O3 have been proposed and fabricated. A very high breakdown voltage exceeding 3200 V and a low drain leakage current of 230 nA/mm at gate-drain distance (LGD) of 40 μm was achieved without any sacrificing DC output characteristics while those of the unpassivated HEMT were 350 V and 134 μA/mm. The breakdown voltage of the Ga2O3 passivated HEMT was increased with increase of LGD because the injected electrons into the deep traps in Ga2O3 effectively extended the depletion region between the gate and the drain. And the injected electrons into deep traps have high activation energy for de-trapping so that the reverse blocking characteristics of the Ga2O3 passivated HEMT were considerable improved.
{"title":"3.2 kV AlGaN/GaN MIS-HEMTs employing RF sputtered Ga2O3 films","authors":"O. Seok, W. Ahn, Young-shil Kim, M. Han, M. Ha","doi":"10.1109/ISPSD.2012.6229075","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229075","url":null,"abstract":"AlGaN/GaN metal insulator semiconductor high electron mobility transistors (MIS-HEMTs) employing rf sputtered Ga<sub>2</sub>O<sub>3</sub> have been proposed and fabricated. A very high breakdown voltage exceeding 3200 V and a low drain leakage current of 230 nA/mm at gate-drain distance (L<sub>GD</sub>) of 40 μm was achieved without any sacrificing DC output characteristics while those of the unpassivated HEMT were 350 V and 134 μA/mm. The breakdown voltage of the Ga<sub>2</sub>O<sub>3</sub> passivated HEMT was increased with increase of L<sub>GD</sub> because the injected electrons into the deep traps in Ga<sub>2</sub>O<sub>3</sub> effectively extended the depletion region between the gate and the drain. And the injected electrons into deep traps have high activation energy for de-trapping so that the reverse blocking characteristics of the Ga<sub>2</sub>O<sub>3</sub> passivated HEMT were considerable improved.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117162551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229060
T. Karino, O. Sasaki, M. Yamaji, H. Sumida
We have established the 700V-class PIC technology based on 0.35μm design to provide power management ICs with higher performances and lower chip cost for the first time. And a 700V PWM-IC based on 0.35μm design, whose chip size can be reduced to 50% that of the IC based on 1.0μm design, is realized. This paper will report our developed 700V PIC technology with a PWM-IC product designed by this technology.
{"title":"700V PIC technology based on 0.35µm design for AC-DC power units","authors":"T. Karino, O. Sasaki, M. Yamaji, H. Sumida","doi":"10.1109/ISPSD.2012.6229060","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229060","url":null,"abstract":"We have established the 700V-class PIC technology based on 0.35μm design to provide power management ICs with higher performances and lower chip cost for the first time. And a 700V PWM-IC based on 0.35μm design, whose chip size can be reduced to 50% that of the IC based on 1.0μm design, is realized. This paper will report our developed 700V PIC technology with a PWM-IC product designed by this technology.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125649342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229037
Chen-Liang Chu, C. M. Hu, C. F. Huang, Y. Chen, F. Y. Chen, K. Thei, C. Hsu, C. Yao, R. Liou, H. Tuan
In this study, a reduction in the saturation current caused by self-heating effect at high VGS is observed in a 35-V rated asymmetric DEMOSFET. The high VGS -induced the large current and raises up the device surface temperature. The Kirk-effect takes places at sufficiently high current levels (high VGS values) leading to the movement of the maximum temperature point from the gate-overlapped DE (drain-extended) region to the drain-side contact region. The drift-region resistance strongly correlates to the self-heating effect and the VK voltage is proportional to the doping concentration in the drift region. As a result, the reduced surface heating (RESURH) can be realized by the optimization of doping concentration in the drift region.
{"title":"Investigation of voltage-dependent thermal property in high-voltage drain-extended MOSFETs","authors":"Chen-Liang Chu, C. M. Hu, C. F. Huang, Y. Chen, F. Y. Chen, K. Thei, C. Hsu, C. Yao, R. Liou, H. Tuan","doi":"10.1109/ISPSD.2012.6229037","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229037","url":null,"abstract":"In this study, a reduction in the saturation current caused by self-heating effect at high VGS is observed in a 35-V rated asymmetric DEMOSFET. The high VGS -induced the large current and raises up the device surface temperature. The Kirk-effect takes places at sufficiently high current levels (high VGS values) leading to the movement of the maximum temperature point from the gate-overlapped DE (drain-extended) region to the drain-side contact region. The drift-region resistance strongly correlates to the self-heating effect and the VK voltage is proportional to the doping concentration in the drift region. As a result, the reduced surface heating (RESURH) can be realized by the optimization of doping concentration in the drift region.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131275115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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