Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229102
D. Sheridan, K. Chatty, V. Bondarenko, J. Casady
1200V SiC vertical trench JFETs have been evaluated for their reverse conduction properties. Absent of a traditional body diode, the SiC trench JFET is shown to be able to operate effectively in reverse mode when used with or without an antiparallel diode in applications requiring reverse commutation. Device characteristics and experimental results are given for both traditional half-bridge and cascode topologies.
{"title":"Reverse conduction properties of vertical SiC trench JFETs","authors":"D. Sheridan, K. Chatty, V. Bondarenko, J. Casady","doi":"10.1109/ISPSD.2012.6229102","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229102","url":null,"abstract":"1200V SiC vertical trench JFETs have been evaluated for their reverse conduction properties. Absent of a traditional body diode, the SiC trench JFET is shown to be able to operate effectively in reverse mode when used with or without an antiparallel diode in applications requiring reverse commutation. Device characteristics and experimental results are given for both traditional half-bridge and cascode topologies.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127445689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229016
B. Lu, E. Matioli, T. Palacios
A new tri-gate normally-off GaN metal-insulator-semiconductor field effect transistor (MISFET) is presented in this paper. By using a three-dimensional gate structure with combination of a sub-micron gate recess, the new device achieves a very low off-state drain leakage current of 0.6 μA/mm at a breakdown voltage of 565 V while maintains a low on-resistance of 2.1 mΩ·cm2. The new device has an on/off current ratio of more than 8 orders of magnitude and a sub-threshold slope of 86±9 mV/decade. The threshold voltage of the new device is 0.80±0.06 V with a maximum drain current of 530 mA/mm. These results confirm the great potential of the tri-gate normally-off GaN-on-Si MISFETs for the next generation of power electronics.
{"title":"Low leakage normally-off tri-gate GaN MISFET","authors":"B. Lu, E. Matioli, T. Palacios","doi":"10.1109/ISPSD.2012.6229016","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229016","url":null,"abstract":"A new tri-gate normally-off GaN metal-insulator-semiconductor field effect transistor (MISFET) is presented in this paper. By using a three-dimensional gate structure with combination of a sub-micron gate recess, the new device achieves a very low off-state drain leakage current of 0.6 μA/mm at a breakdown voltage of 565 V while maintains a low on-resistance of 2.1 mΩ·cm2. The new device has an on/off current ratio of more than 8 orders of magnitude and a sub-threshold slope of 86±9 mV/decade. The threshold voltage of the new device is 0.80±0.06 V with a maximum drain current of 530 mA/mm. These results confirm the great potential of the tri-gate normally-off GaN-on-Si MISFETs for the next generation of power electronics.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126123518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229045
S. Honda, Y. Haraguchi, A. Narazaki, T. Terashima, Y. Terasaki
In this paper, we present the characteristics of a fabricated 600V CSTBT™ as the next generation IGBT. The techniques applied this novel device include about half-size shrinkage of the transistor unit cell with a fine pattern process and an LPT (Light Punch Through) structure utilizing an advanced thin wafer process technology. As a result, these techniques brought a significant reduction of the Vce(sat) and the Eoff. The Vce(sat)-Eoff trade-off relationship of the proposed CSTBT has been improved by approximately 20% compared to the conventional one possessing wide SOA (Safe Operating Area) enough to device applications.
{"title":"Next generation 600V CSTBT™ with an advanced fine pattern and a thin wafer process technologies","authors":"S. Honda, Y. Haraguchi, A. Narazaki, T. Terashima, Y. Terasaki","doi":"10.1109/ISPSD.2012.6229045","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229045","url":null,"abstract":"In this paper, we present the characteristics of a fabricated 600V CSTBT™ as the next generation IGBT. The techniques applied this novel device include about half-size shrinkage of the transistor unit cell with a fine pattern process and an LPT (Light Punch Through) structure utilizing an advanced thin wafer process technology. As a result, these techniques brought a significant reduction of the Vce(sat) and the Eoff. The Vce(sat)-Eoff trade-off relationship of the proposed CSTBT has been improved by approximately 20% compared to the conventional one possessing wide SOA (Safe Operating Area) enough to device applications.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116762386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229023
A. P. Hsieh, F. Udrea, Wei-Chieh Lin
An advanced 700V Smart Trench IGBT with monolithically integrated over-voltage and over-current protecting circuits is presented in this paper. The proposed Smart IGBT comprises a sense IGBT, a low voltage lateral n-channel MOSFET (M1), an avalanche diode (Dav), and poly-crystalline Zener diodes (ZD) and resistor (Rpoly). Mix-mode transient simulations with MEDICI have proven the functionalities of the protecting circuits when the device is operating under abnormal conditions, such as Unclamped Inductive Switching (UIS) and Short Circuit (SC) condition. A Trench IGBT process is used to fabricate this device with total 11 masks including one metal mask only. The characterizations of the fabricated device exhibit the clamping capability of the avalanche diode and voltage pull-down ability of the MOSFET.
{"title":"700V Smart Trench IGBT with monolithic over-voltage and over-current protecting functions","authors":"A. P. Hsieh, F. Udrea, Wei-Chieh Lin","doi":"10.1109/ISPSD.2012.6229023","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229023","url":null,"abstract":"An advanced 700V Smart Trench IGBT with monolithically integrated over-voltage and over-current protecting circuits is presented in this paper. The proposed Smart IGBT comprises a sense IGBT, a low voltage lateral n-channel MOSFET (M1), an avalanche diode (Dav), and poly-crystalline Zener diodes (ZD) and resistor (Rpoly). Mix-mode transient simulations with MEDICI have proven the functionalities of the protecting circuits when the device is operating under abnormal conditions, such as Unclamped Inductive Switching (UIS) and Short Circuit (SC) condition. A Trench IGBT process is used to fabricate this device with total 11 masks including one metal mask only. The characterizations of the fabricated device exhibit the clamping capability of the avalanche diode and voltage pull-down ability of the MOSFET.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116033423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229057
Hao Hu, Zhi Lin, Xingbi Chen
A novel high voltage start-up current source to provide start-up current for integrated circuits in a switched mode power supply (SMPS) is presented. The current source contains a VDMOS transistor to sustain high voltage. The gate of the VDMOS transistor is biased at a certain voltage by a floating p-island, to provide start-up current. A NMOS transistor is used to turn on and off the current source. Experimental results indicate the high voltage start-up current source is able to start and restart as designed. The current source draws no current from the line after turned off. The proposed structure is believed to be more energy saving and cost-effective compared with other solutions.
{"title":"A novel high voltage start-up current source for SMPS","authors":"Hao Hu, Zhi Lin, Xingbi Chen","doi":"10.1109/ISPSD.2012.6229057","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229057","url":null,"abstract":"A novel high voltage start-up current source to provide start-up current for integrated circuits in a switched mode power supply (SMPS) is presented. The current source contains a VDMOS transistor to sustain high voltage. The gate of the VDMOS transistor is biased at a certain voltage by a floating p-island, to provide start-up current. A NMOS transistor is used to turn on and off the current source. Experimental results indicate the high voltage start-up current source is able to start and restart as designed. The current source draws no current from the line after turned off. The proposed structure is believed to be more energy saving and cost-effective compared with other solutions.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116268885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229080
J. Roig, S. Mouhoubi, F. De Pestel, N. Martens, F. Bauwens, H. Massie, L. Golonka, G. Loechelt
The power losses in System-in-Package (SiP) 12V-input DC/DC buck converters with advanced 30V Shield-Plate FETs (SP-FETs) are assessed by experiment and simulation with special interest in the body-diode contribution. Unlike previous work, rise/fall times and on/off deadtimes are in the nanosecond range to provide high efficiency at high frequency operation (1-4MHz).
{"title":"Body-diode related losses in Shield-Plate FETs for SiP 12V-input DC/DC buck converters operating at high-frequency (4MHz)","authors":"J. Roig, S. Mouhoubi, F. De Pestel, N. Martens, F. Bauwens, H. Massie, L. Golonka, G. Loechelt","doi":"10.1109/ISPSD.2012.6229080","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229080","url":null,"abstract":"The power losses in System-in-Package (SiP) 12V-input DC/DC buck converters with advanced 30V Shield-Plate FETs (SP-FETs) are assessed by experiment and simulation with special interest in the body-diode contribution. Unlike previous work, rise/fall times and on/off deadtimes are in the nanosecond range to provide high efficiency at high frequency operation (1-4MHz).","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116624750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229050
A. Balachandran, M. Sweet, L. Ngwendson, E. M. S. Narayanan, Shona Ray, Henrique Quaresma, J. Bruce
In this paper, we report the experimental results of a 3.3kV rated CIGBT (Clustered Insulated Gate Bipolar Transistor) with planar gates in non-punch through technology (NPT) with RTA anode. Previously it was reported that for identical turn-off losses the on-state voltage of the 3.3kV NPT-CIGBT is less than 0.7V as compared to that of a commercially available FS-IGBT. Herein we show that due to the low saturation current density, the CIGBT has a rugged short circuit performance, as measured to be of more than 100μs at 25°C which is much higher than any MOS controlled bipolar device ever reported. Furthermore, results also show that the use of the RTA anode compared to the diffused anode helps in reducing the turn-off losses by about 50% without affecting the Vce(sat) of the device.
{"title":"Enhanced short-circuit performance of 3.3kV Clustered Insulated Gate Bipolar Transistor (CIGBT) in NPT technology with RTA Anode.","authors":"A. Balachandran, M. Sweet, L. Ngwendson, E. M. S. Narayanan, Shona Ray, Henrique Quaresma, J. Bruce","doi":"10.1109/ISPSD.2012.6229050","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229050","url":null,"abstract":"In this paper, we report the experimental results of a 3.3kV rated CIGBT (Clustered Insulated Gate Bipolar Transistor) with planar gates in non-punch through technology (NPT) with RTA anode. Previously it was reported that for identical turn-off losses the on-state voltage of the 3.3kV NPT-CIGBT is less than 0.7V as compared to that of a commercially available FS-IGBT. Herein we show that due to the low saturation current density, the CIGBT has a rugged short circuit performance, as measured to be of more than 100μs at 25°C which is much higher than any MOS controlled bipolar device ever reported. Furthermore, results also show that the use of the RTA anode compared to the diffused anode helps in reducing the turn-off losses by about 50% without affecting the Vce(sat) of the device.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134603325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229078
T. Erlbacher, H. Schwarzmann, A. Bauer, S. Berberich, J. vom Dorp, L. Frey
Monolithic integration of RC snubbers in power electronic applications offers great opportunities. The presented devices provide tight tolerances and enable high integration densities. Especially, the incorporation into power modules enables reduction of electromagnetic interferences in accordance with reliable lifetime predictions.
{"title":"Improving module performance and reliability in power electronic applications by monolithic integration of RC-snubbers","authors":"T. Erlbacher, H. Schwarzmann, A. Bauer, S. Berberich, J. vom Dorp, L. Frey","doi":"10.1109/ISPSD.2012.6229078","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229078","url":null,"abstract":"Monolithic integration of RC snubbers in power electronic applications offers great opportunities. The presented devices provide tight tolerances and enable high integration densities. Especially, the incorporation into power modules enables reduction of electromagnetic interferences in accordance with reliable lifetime predictions.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124293637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229103
A. Bolotnikov, P. Losee, K. Matocha, J. Glaser, J. Nasadoski, Lei Wang, A. Elasser, S. Arthur, Z. Stum, P. Sandvik, Y. Sui, T. Johnson, J. Sabate, L. Stevanovic
This paper discusses the latest developments in the optimization and fabrication of 3.3kV SiC vertical DMOSFETs. The devices show superior on-state and switching losses compared to the even the latest generation of 3.3kV fast Si IGBTs and promise to extend the upper switching frequency of high-voltage power conversion systems beyond several tens of kHz without the need to increase part count with 3-level converter stacks of faster 1.7kV IGBTs.
{"title":"3.3kV SiC MOSFETs designed for low on-resistance and fast switching","authors":"A. Bolotnikov, P. Losee, K. Matocha, J. Glaser, J. Nasadoski, Lei Wang, A. Elasser, S. Arthur, Z. Stum, P. Sandvik, Y. Sui, T. Johnson, J. Sabate, L. Stevanovic","doi":"10.1109/ISPSD.2012.6229103","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229103","url":null,"abstract":"This paper discusses the latest developments in the optimization and fabrication of 3.3kV SiC vertical DMOSFETs. The devices show superior on-state and switching losses compared to the even the latest generation of 3.3kV fast Si IGBTs and promise to extend the upper switching frequency of high-voltage power conversion systems beyond several tens of kHz without the need to increase part count with 3-level converter stacks of faster 1.7kV IGBTs.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121216642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229038
Boyi Yang, Shuming Xu, J. Korec, J. Shen
In this paper, a monolithically integrated gate voltage pull-down circuitry is presented to avoid the unintentional C·dV/dt induced turn-on. The concept of a low threshold voltage MOSFET with this integrated gate voltage pull-down circuitry is introduced as a contributing factor to the next generation high frequency DC-DC converter efficiency improvement. Design considerations on this new device and influences of critical design parameters on device/circuit performance will be fully discussed. In synchronous buck application, this integrated power module achieves more than 2% efficiency improvement over reference solution at high operation frequency (1MHz) under 19V input and 1.3V output condition.
{"title":"Design considerations on low voltage synchronous power MOSFETs with monolithically integrated gate voltage pull-down circuitry","authors":"Boyi Yang, Shuming Xu, J. Korec, J. Shen","doi":"10.1109/ISPSD.2012.6229038","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229038","url":null,"abstract":"In this paper, a monolithically integrated gate voltage pull-down circuitry is presented to avoid the unintentional C·dV/dt induced turn-on. The concept of a low threshold voltage MOSFET with this integrated gate voltage pull-down circuitry is introduced as a contributing factor to the next generation high frequency DC-DC converter efficiency improvement. Design considerations on this new device and influences of critical design parameters on device/circuit performance will be fully discussed. In synchronous buck application, this integrated power module achieves more than 2% efficiency improvement over reference solution at high operation frequency (1MHz) under 19V input and 1.3V output condition.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127233638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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