Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229028
M. Horio, Y. Iizuka, Y. Ikeda, E. Mochizuki, Y. Takahashi
Aluminium wirebond-less power module structure was investigated and presented in ISPSD 2011 [1]. The features of this structure are high-density packaging with Copper pins connection and power circuit board, low thermal resistance with thick Copper block on Silicon Nitride ceramic substrate and high reliability with epoxy resin moulding. This paper introduces Silicon Carbide MOSFET power module with this developed structure. High temperature operating capability up to 200°C is achieved with newly developed epoxy resin and Silver sintering technology. Low internal inductance is designed by laminating current paths to take an advantage of developed structure. SiC MOSFET 100A/1200V module was designed. Loss evaluation with this SiC module shows superior performance with SiC devices and also with developed structure.
{"title":"Ultra compact and high reliable SiC MOSFET power module with 200°C operating capability","authors":"M. Horio, Y. Iizuka, Y. Ikeda, E. Mochizuki, Y. Takahashi","doi":"10.1109/ISPSD.2012.6229028","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229028","url":null,"abstract":"Aluminium wirebond-less power module structure was investigated and presented in ISPSD 2011 [1]. The features of this structure are high-density packaging with Copper pins connection and power circuit board, low thermal resistance with thick Copper block on Silicon Nitride ceramic substrate and high reliability with epoxy resin moulding. This paper introduces Silicon Carbide MOSFET power module with this developed structure. High temperature operating capability up to 200°C is achieved with newly developed epoxy resin and Silver sintering technology. Low internal inductance is designed by laminating current paths to take an advantage of developed structure. SiC MOSFET 100A/1200V module was designed. Loss evaluation with this SiC module shows superior performance with SiC devices and also with developed structure.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122500494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229016
B. Lu, E. Matioli, T. Palacios
A new tri-gate normally-off GaN metal-insulator-semiconductor field effect transistor (MISFET) is presented in this paper. By using a three-dimensional gate structure with combination of a sub-micron gate recess, the new device achieves a very low off-state drain leakage current of 0.6 μA/mm at a breakdown voltage of 565 V while maintains a low on-resistance of 2.1 mΩ·cm2. The new device has an on/off current ratio of more than 8 orders of magnitude and a sub-threshold slope of 86±9 mV/decade. The threshold voltage of the new device is 0.80±0.06 V with a maximum drain current of 530 mA/mm. These results confirm the great potential of the tri-gate normally-off GaN-on-Si MISFETs for the next generation of power electronics.
{"title":"Low leakage normally-off tri-gate GaN MISFET","authors":"B. Lu, E. Matioli, T. Palacios","doi":"10.1109/ISPSD.2012.6229016","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229016","url":null,"abstract":"A new tri-gate normally-off GaN metal-insulator-semiconductor field effect transistor (MISFET) is presented in this paper. By using a three-dimensional gate structure with combination of a sub-micron gate recess, the new device achieves a very low off-state drain leakage current of 0.6 μA/mm at a breakdown voltage of 565 V while maintains a low on-resistance of 2.1 mΩ·cm2. The new device has an on/off current ratio of more than 8 orders of magnitude and a sub-threshold slope of 86±9 mV/decade. The threshold voltage of the new device is 0.80±0.06 V with a maximum drain current of 530 mA/mm. These results confirm the great potential of the tri-gate normally-off GaN-on-Si MISFETs for the next generation of power electronics.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126123518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229102
D. Sheridan, K. Chatty, V. Bondarenko, J. Casady
1200V SiC vertical trench JFETs have been evaluated for their reverse conduction properties. Absent of a traditional body diode, the SiC trench JFET is shown to be able to operate effectively in reverse mode when used with or without an antiparallel diode in applications requiring reverse commutation. Device characteristics and experimental results are given for both traditional half-bridge and cascode topologies.
{"title":"Reverse conduction properties of vertical SiC trench JFETs","authors":"D. Sheridan, K. Chatty, V. Bondarenko, J. Casady","doi":"10.1109/ISPSD.2012.6229102","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229102","url":null,"abstract":"1200V SiC vertical trench JFETs have been evaluated for their reverse conduction properties. Absent of a traditional body diode, the SiC trench JFET is shown to be able to operate effectively in reverse mode when used with or without an antiparallel diode in applications requiring reverse commutation. Device characteristics and experimental results are given for both traditional half-bridge and cascode topologies.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127445689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229045
S. Honda, Y. Haraguchi, A. Narazaki, T. Terashima, Y. Terasaki
In this paper, we present the characteristics of a fabricated 600V CSTBT™ as the next generation IGBT. The techniques applied this novel device include about half-size shrinkage of the transistor unit cell with a fine pattern process and an LPT (Light Punch Through) structure utilizing an advanced thin wafer process technology. As a result, these techniques brought a significant reduction of the Vce(sat) and the Eoff. The Vce(sat)-Eoff trade-off relationship of the proposed CSTBT has been improved by approximately 20% compared to the conventional one possessing wide SOA (Safe Operating Area) enough to device applications.
{"title":"Next generation 600V CSTBT™ with an advanced fine pattern and a thin wafer process technologies","authors":"S. Honda, Y. Haraguchi, A. Narazaki, T. Terashima, Y. Terasaki","doi":"10.1109/ISPSD.2012.6229045","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229045","url":null,"abstract":"In this paper, we present the characteristics of a fabricated 600V CSTBT™ as the next generation IGBT. The techniques applied this novel device include about half-size shrinkage of the transistor unit cell with a fine pattern process and an LPT (Light Punch Through) structure utilizing an advanced thin wafer process technology. As a result, these techniques brought a significant reduction of the Vce(sat) and the Eoff. The Vce(sat)-Eoff trade-off relationship of the proposed CSTBT has been improved by approximately 20% compared to the conventional one possessing wide SOA (Safe Operating Area) enough to device applications.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116762386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229030
M. Antoniou, F. Udrea, E. Tee, S. Pilkington, D. K. Pal, A. Hoelke
This paper demonstrates and discusses novel “three dimensional” silicon based junction isolation/termination solutions suitable for high density ultra-low-resistance Lateral Super-Junction structures. The proposed designs are both compact and effective in safely distributing the electrostatic potential away from the active device area. The designs are based on the utilization of existing layers in the device fabrication line, hence resulting in no extra complexity or cost increase. The study/demonstration is done through extensive experimental measurements and numerical simulations.
{"title":"Compact three-dimensional silicon termination solutions for high voltage SOI SuperJunction","authors":"M. Antoniou, F. Udrea, E. Tee, S. Pilkington, D. K. Pal, A. Hoelke","doi":"10.1109/ISPSD.2012.6229030","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229030","url":null,"abstract":"This paper demonstrates and discusses novel “three dimensional” silicon based junction isolation/termination solutions suitable for high density ultra-low-resistance Lateral Super-Junction structures. The proposed designs are both compact and effective in safely distributing the electrostatic potential away from the active device area. The designs are based on the utilization of existing layers in the device fabrication line, hence resulting in no extra complexity or cost increase. The study/demonstration is done through extensive experimental measurements and numerical simulations.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121886748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229027
L. Benaissa, N. Rouger, J. Widiez, J. Crebier, J. Dafonseca, D. Lafond, V. Gaude, K. Vladimirova
The paper presents current technological achievements and associated characterizations of the mechanical, thermal and electrical properties of the assembly at wafer level of vertical power devices matrices. Based on direct bonding technology, metallic substrates are bonded to the Silicon active layer at wafer level to ensure back-side common electrode electrical interconnections while offering outstanding electrical and thermal behavior. In addition, the characteristics of the power device can be optimized independently from mechanical requirements on Silicon thicknesses. The technological integration is described and analyzed. The paper focuses afterwards on the electrical characterizations of these new components. The interest of this partial packaging technique is related to the ease of implementation of numerous power devices used for example in interleaved converter topologies where up to ten to fourteen inverter arms can be connected in parallel to significantly reduce the needed filtering elements.
{"title":"A vertical power device conductive assembly at wafer level using direct bonding technology","authors":"L. Benaissa, N. Rouger, J. Widiez, J. Crebier, J. Dafonseca, D. Lafond, V. Gaude, K. Vladimirova","doi":"10.1109/ISPSD.2012.6229027","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229027","url":null,"abstract":"The paper presents current technological achievements and associated characterizations of the mechanical, thermal and electrical properties of the assembly at wafer level of vertical power devices matrices. Based on direct bonding technology, metallic substrates are bonded to the Silicon active layer at wafer level to ensure back-side common electrode electrical interconnections while offering outstanding electrical and thermal behavior. In addition, the characteristics of the power device can be optimized independently from mechanical requirements on Silicon thicknesses. The technological integration is described and analyzed. The paper focuses afterwards on the electrical characterizations of these new components. The interest of this partial packaging technique is related to the ease of implementation of numerous power devices used for example in interleaved converter topologies where up to ten to fourteen inverter arms can be connected in parallel to significantly reduce the needed filtering elements.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125632558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229050
A. Balachandran, M. Sweet, L. Ngwendson, E. M. S. Narayanan, Shona Ray, Henrique Quaresma, J. Bruce
In this paper, we report the experimental results of a 3.3kV rated CIGBT (Clustered Insulated Gate Bipolar Transistor) with planar gates in non-punch through technology (NPT) with RTA anode. Previously it was reported that for identical turn-off losses the on-state voltage of the 3.3kV NPT-CIGBT is less than 0.7V as compared to that of a commercially available FS-IGBT. Herein we show that due to the low saturation current density, the CIGBT has a rugged short circuit performance, as measured to be of more than 100μs at 25°C which is much higher than any MOS controlled bipolar device ever reported. Furthermore, results also show that the use of the RTA anode compared to the diffused anode helps in reducing the turn-off losses by about 50% without affecting the Vce(sat) of the device.
{"title":"Enhanced short-circuit performance of 3.3kV Clustered Insulated Gate Bipolar Transistor (CIGBT) in NPT technology with RTA Anode.","authors":"A. Balachandran, M. Sweet, L. Ngwendson, E. M. S. Narayanan, Shona Ray, Henrique Quaresma, J. Bruce","doi":"10.1109/ISPSD.2012.6229050","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229050","url":null,"abstract":"In this paper, we report the experimental results of a 3.3kV rated CIGBT (Clustered Insulated Gate Bipolar Transistor) with planar gates in non-punch through technology (NPT) with RTA anode. Previously it was reported that for identical turn-off losses the on-state voltage of the 3.3kV NPT-CIGBT is less than 0.7V as compared to that of a commercially available FS-IGBT. Herein we show that due to the low saturation current density, the CIGBT has a rugged short circuit performance, as measured to be of more than 100μs at 25°C which is much higher than any MOS controlled bipolar device ever reported. Furthermore, results also show that the use of the RTA anode compared to the diffused anode helps in reducing the turn-off losses by about 50% without affecting the Vce(sat) of the device.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134603325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229095
P. Vanmeerbeek, J. Roig, F. Bogman, P. Moens, A. Villamor-Baliarda, D. Flores
A planar multiple floating field-limiting ring structure, designed for above 600V blocking capability, is analyzed in this work. We have proven by simulation and experiment that adding a well designed buffer layer in the epi-substrate region counteracts on the drop in electric field which is due to the space charge limited current and as such the buffer enhances the robustness towards reverse voltage biasing.
{"title":"Enhancing the robustness of a multiple floating field-limiting ring termination by introducing a buffer layer","authors":"P. Vanmeerbeek, J. Roig, F. Bogman, P. Moens, A. Villamor-Baliarda, D. Flores","doi":"10.1109/ISPSD.2012.6229095","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229095","url":null,"abstract":"A planar multiple floating field-limiting ring structure, designed for above 600V blocking capability, is analyzed in this work. We have proven by simulation and experiment that adding a well designed buffer layer in the epi-substrate region counteracts on the drop in electric field which is due to the space charge limited current and as such the buffer enhances the robustness towards reverse voltage biasing.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125221484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229038
Boyi Yang, Shuming Xu, J. Korec, J. Shen
In this paper, a monolithically integrated gate voltage pull-down circuitry is presented to avoid the unintentional C·dV/dt induced turn-on. The concept of a low threshold voltage MOSFET with this integrated gate voltage pull-down circuitry is introduced as a contributing factor to the next generation high frequency DC-DC converter efficiency improvement. Design considerations on this new device and influences of critical design parameters on device/circuit performance will be fully discussed. In synchronous buck application, this integrated power module achieves more than 2% efficiency improvement over reference solution at high operation frequency (1MHz) under 19V input and 1.3V output condition.
{"title":"Design considerations on low voltage synchronous power MOSFETs with monolithically integrated gate voltage pull-down circuitry","authors":"Boyi Yang, Shuming Xu, J. Korec, J. Shen","doi":"10.1109/ISPSD.2012.6229038","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229038","url":null,"abstract":"In this paper, a monolithically integrated gate voltage pull-down circuitry is presented to avoid the unintentional C·dV/dt induced turn-on. The concept of a low threshold voltage MOSFET with this integrated gate voltage pull-down circuitry is introduced as a contributing factor to the next generation high frequency DC-DC converter efficiency improvement. Design considerations on this new device and influences of critical design parameters on device/circuit performance will be fully discussed. In synchronous buck application, this integrated power module achieves more than 2% efficiency improvement over reference solution at high operation frequency (1MHz) under 19V input and 1.3V output condition.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127233638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229103
A. Bolotnikov, P. Losee, K. Matocha, J. Glaser, J. Nasadoski, Lei Wang, A. Elasser, S. Arthur, Z. Stum, P. Sandvik, Y. Sui, T. Johnson, J. Sabate, L. Stevanovic
This paper discusses the latest developments in the optimization and fabrication of 3.3kV SiC vertical DMOSFETs. The devices show superior on-state and switching losses compared to the even the latest generation of 3.3kV fast Si IGBTs and promise to extend the upper switching frequency of high-voltage power conversion systems beyond several tens of kHz without the need to increase part count with 3-level converter stacks of faster 1.7kV IGBTs.
{"title":"3.3kV SiC MOSFETs designed for low on-resistance and fast switching","authors":"A. Bolotnikov, P. Losee, K. Matocha, J. Glaser, J. Nasadoski, Lei Wang, A. Elasser, S. Arthur, Z. Stum, P. Sandvik, Y. Sui, T. Johnson, J. Sabate, L. Stevanovic","doi":"10.1109/ISPSD.2012.6229103","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229103","url":null,"abstract":"This paper discusses the latest developments in the optimization and fabrication of 3.3kV SiC vertical DMOSFETs. The devices show superior on-state and switching losses compared to the even the latest generation of 3.3kV fast Si IGBTs and promise to extend the upper switching frequency of high-voltage power conversion systems beyond several tens of kHz without the need to increase part count with 3-level converter stacks of faster 1.7kV IGBTs.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121216642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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