Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229011
B. Hellenthal
Power electronic semiconductors from the viewpoint of an automotive OEM. Improving efficiency, especially in the “hidden” utilization of power electronic semiconductors, defines the next level of automotive electrification. AUDI breaks new ground in the semiconductor industry by strongly influencing the future of power electronics. Next to new products and functions, new forms of collaboration, networks and partnerships are needed.
{"title":"Power electronics - key to the next level of automotive electrification","authors":"B. Hellenthal","doi":"10.1109/ISPSD.2012.6229011","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229011","url":null,"abstract":"Power electronic semiconductors from the viewpoint of an automotive OEM. Improving efficiency, especially in the “hidden” utilization of power electronic semiconductors, defines the next level of automotive electrification. AUDI breaks new ground in the semiconductor industry by strongly influencing the future of power electronics. Next to new products and functions, new forms of collaboration, networks and partnerships are needed.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117323579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229073
M. Ueno, M. Miyake, M. Miura-Mattausch
Switching behavior of a 4H-SiC IGBT is discussed considering the punch-through effect of the base layer. The switching behavior is investigated with a mixed-mode simulation of a 2D-numerical device simulator, where extremely abrupt switching characteristics are observed at voltage ratings of 6.5kV and 13kV. The origin is explained by the carrier dynamics under the punch-through condition. As a proof of this explanation, the switching behaviors are reproduced by circuit simulation with the compact IGBT model HiSIM-IGBT, where the punch-through behavior is considered.
{"title":"Specific features of SiC-IGBT with 13kV switching","authors":"M. Ueno, M. Miyake, M. Miura-Mattausch","doi":"10.1109/ISPSD.2012.6229073","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229073","url":null,"abstract":"Switching behavior of a 4H-SiC IGBT is discussed considering the punch-through effect of the base layer. The switching behavior is investigated with a mixed-mode simulation of a 2D-numerical device simulator, where extremely abrupt switching characteristics are observed at voltage ratings of 6.5kV and 13kV. The origin is explained by the carrier dynamics under the punch-through condition. As a proof of this explanation, the switching behaviors are reproduced by circuit simulation with the compact IGBT model HiSIM-IGBT, where the punch-through behavior is considered.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132408618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229056
Weifeng Sun, Jing Zhu, Qinsong Qian, Bo Hou, Wei Su, Sen Zhang
A novel double-well (DW) divided RESURF isolation structure featuring two slender N-Well regions at N--Well, aiming at improving the off-state breakdown voltage for high voltage IC (HVIC) is proposed in this paper. The N-Well regions in the presented structure efficiently prevent N--Well which used for the drift region of the Lateral Double Diffused MOSFET (LDMOS) from depleting with P-Well, so as to maintain the RESURF condition. The experiment results show that the proposed structure exhibits the breakdown voltage of 760V which has an improvement of 15% compared with the conventional structure.
{"title":"A novel double-well isolation structure for high voltage ICs","authors":"Weifeng Sun, Jing Zhu, Qinsong Qian, Bo Hou, Wei Su, Sen Zhang","doi":"10.1109/ISPSD.2012.6229056","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229056","url":null,"abstract":"A novel double-well (DW) divided RESURF isolation structure featuring two slender N-Well regions at N--Well, aiming at improving the off-state breakdown voltage for high voltage IC (HVIC) is proposed in this paper. The N-Well regions in the presented structure efficiently prevent N--Well which used for the drift region of the Lateral Double Diffused MOSFET (LDMOS) from depleting with P-Well, so as to maintain the RESURF condition. The experiment results show that the proposed structure exhibits the breakdown voltage of 760V which has an improvement of 15% compared with the conventional structure.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130924448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229029
G. Loechelt, G. Grivna, L. Golonka, C. Hoggatt, H. Massie, F. De Pestel, N. Martens, S. Mouhoubi, J. Roig, T. Colpaert, P. Coppens, F. Bauwens, E. De Backer
A novel silicon device architecture for DC-DC power conversion is reported. Efficient switching at high frequencies (1-5 MHz) is achieved by simultaneously reducing gate charge, reverse capacitance, and gate resistance while still maintaining good on-state resistance and off-state breakdown voltage. Power efficiencies in excess of 88% were realized in a synchronous buck converter running at 1.3 MHz.
{"title":"A high-speed silicon FET for efficient DC-DC power conversion","authors":"G. Loechelt, G. Grivna, L. Golonka, C. Hoggatt, H. Massie, F. De Pestel, N. Martens, S. Mouhoubi, J. Roig, T. Colpaert, P. Coppens, F. Bauwens, E. De Backer","doi":"10.1109/ISPSD.2012.6229029","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229029","url":null,"abstract":"A novel silicon device architecture for DC-DC power conversion is reported. Efficient switching at high frequencies (1-5 MHz) is achieved by simultaneously reducing gate charge, reverse capacitance, and gate resistance while still maintaining good on-state resistance and off-state breakdown voltage. Power efficiencies in excess of 88% were realized in a synchronous buck converter running at 1.3 MHz.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131200851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229069
Chunhua Zhou, Q. Jiang, Sen Huang, K. J. Chen
In this paper, we studied the vertical leakage/breakdown mechanisms in AlGaN/GaN structures grown on low resistivity p-type (111) Si substrate by temperature-dependent current-voltage measurements. We suggested that the top-to-substrate vertical leakage/breakdown is dominated by the space-charge-limited current (SCLC) conduction mechanism involving both acceptor and donor traps in buffer/transition layer. Based on temperature-dependent transient backgating measurements, the acceptor level and donor level were determined to be at EV+543 meV and EC-616 meV, respectively.
{"title":"Vertical leakage/breakdown mechanisms in AlGaN/GaN-on-Si structures","authors":"Chunhua Zhou, Q. Jiang, Sen Huang, K. J. Chen","doi":"10.1109/ISPSD.2012.6229069","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229069","url":null,"abstract":"In this paper, we studied the vertical leakage/breakdown mechanisms in AlGaN/GaN structures grown on low resistivity p-type (111) Si substrate by temperature-dependent current-voltage measurements. We suggested that the top-to-substrate vertical leakage/breakdown is dominated by the space-charge-limited current (SCLC) conduction mechanism involving both acceptor and donor traps in buffer/transition layer. Based on temperature-dependent transient backgating measurements, the acceptor level and donor level were determined to be at EV+543 meV and EC-616 meV, respectively.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"6 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114019717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229100
W. Hsu, F. Udrea, Win-Pin Chang, Max Chen
The Tandem PiN Schottky (TPS) rectifier features lowly-doped p-layers in both active and termination regions, and is applied in 600-V rating for the first time. In the active region, the Schottky contact is in series connection with a transparent p-layer, leading to a superior forward performance than the conventional diodes. In addition, due to the benefit of moderate hole injection from the p-layer, the TPS offers a better trade-off between the on-state voltage and the switching speed. The active p-layer also helps to stabilise the Schottky contact, and hence the electrical data distributions are more concentrated. Regarding the floating p-layer in the termination region, its purpose is to reduce the peak electric fields, and the TPS demonstrates a high breakdown voltage with a compact termination width, less than 70% of the state-of-the-art devices on the market. Experimental results have shown that the 600-V TPS rectifier has an ultra-low on-state voltage of 0.98 V at 250 A/cm2, a fast turn-off time of 75 ns by the standard RG1 test (IF=0.5A, IR=1A, and IRR=0.25A) and a breakdown voltage over 720 V. It is noteworthy that the p-layers in the active and termination regions can be formed at no extra cost for the use of self-alignment process.
串联引脚肖特基(TPS)整流器在有源区和终端区均具有低掺杂p层，并首次应用于600 v额定值。在有源区，肖特基触点与透明p层串联，使其具有比传统二极管更好的正向性能。此外，由于p层的适度空穴注入的好处，TPS在导通电压和开关速度之间提供了更好的权衡。有源p层也有助于稳定肖特基接触，因此电数据分布更集中。对于终端区域的浮动p层，其目的是降低峰值电场，并且TPS具有高击穿电压和紧凑的终端宽度，不到市场上最先进器件的70%。实验结果表明，600 V TPS整流器在250 A/cm2时具有0.98 V的超低导通电压，通过标准RG1测试(IF=0.5A, IR=1A, IRR=0.25A)，快速关断时间为75 ns，击穿电压超过720 V。值得注意的是，使用自对准过程可以在没有额外成本的情况下形成有源区和终止区的p层。
{"title":"A fast 600-V Tandem PiN Schottky (TPS) rectifier with ultra-low on-state voltage","authors":"W. Hsu, F. Udrea, Win-Pin Chang, Max Chen","doi":"10.1109/ISPSD.2012.6229100","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229100","url":null,"abstract":"The Tandem PiN Schottky (TPS) rectifier features lowly-doped p-layers in both active and termination regions, and is applied in 600-V rating for the first time. In the active region, the Schottky contact is in series connection with a transparent p-layer, leading to a superior forward performance than the conventional diodes. In addition, due to the benefit of moderate hole injection from the p-layer, the TPS offers a better trade-off between the on-state voltage and the switching speed. The active p-layer also helps to stabilise the Schottky contact, and hence the electrical data distributions are more concentrated. Regarding the floating p-layer in the termination region, its purpose is to reduce the peak electric fields, and the TPS demonstrates a high breakdown voltage with a compact termination width, less than 70% of the state-of-the-art devices on the market. Experimental results have shown that the 600-V TPS rectifier has an ultra-low on-state voltage of 0.98 V at 250 A/cm2, a fast turn-off time of 75 ns by the standard RG1 test (IF=0.5A, IR=1A, and IRR=0.25A) and a breakdown voltage over 720 V. It is noteworthy that the p-layers in the active and termination regions can be formed at no extra cost for the use of self-alignment process.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123847429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229053
M. Tsukuda, Keiichiro Kawakami, Ichiro Omura
Electromagnetic interference (EMI) noise by avalanche oscillations is the major barrier to improve power device performance. Especially the oscillations of three-terminal devices are more complex than two-terminal devices in point of the mutual relationship between devices and external circuit. Scattering parameter (S-parameter) under avalanche condition is obtained to establish stable-unstable criterion with stability factor (K-factor). The stable-unstable criterion clearly indicates the unstable frequency range with each change in MOSFET design. In addition the oscillation mechanism on power MOSFET is modeled with junction capacitance, which is the same as that of diode. For EMI suppression, resonant frequency of external circuit has to be different from unstable frequency of MOSFETs.
{"title":"Scattering parameter approach to power MOSFET design for EMI","authors":"M. Tsukuda, Keiichiro Kawakami, Ichiro Omura","doi":"10.1109/ISPSD.2012.6229053","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229053","url":null,"abstract":"Electromagnetic interference (EMI) noise by avalanche oscillations is the major barrier to improve power device performance. Especially the oscillations of three-terminal devices are more complex than two-terminal devices in point of the mutual relationship between devices and external circuit. Scattering parameter (S-parameter) under avalanche condition is obtained to establish stable-unstable criterion with stability factor (K-factor). The stable-unstable criterion clearly indicates the unstable frequency range with each change in MOSFET design. In addition the oscillation mechanism on power MOSFET is modeled with junction capacitance, which is the same as that of diode. For EMI suppression, resonant frequency of external circuit has to be different from unstable frequency of MOSFETs.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121850846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229070
Jae-Hoon Lee, Y. Kwak, Jae-Hyun Jeong, Heon-Bok Lee, W. Lim, Ki-Se Kim, Ki‐Won Kim, Dong-Suck Kim, Jung-Hee Lee
AlGaN/GaN Schottky barrier diodes (SBDs) with and without in-situ silicon carbon nitride (SiCN) cap layer were investigated. The fabricated SBD with SiCN cap layer exhibited improved electrical characteristics, such as the forward turn on voltage of about 0.7 V, the forward current of 4.1 A at 1.5 V, and the reverse breakdown voltage of 630 V, compared to the corresponding values of 0.8 V, 3.8 A, and 580 V for the reference SBD without the SiCN cap layer. This improvement in the device performance of the SiCN-SBD is because the in-situ SiCN cap layer not only lowers the barrier height, but also effectively passivates the surface of the device with better surface morphology.
{"title":"Reduction in Shottky barrier height of AlGaN-based SBD with in-situ deposited silicon carbon nitride (SiCN) cap layer","authors":"Jae-Hoon Lee, Y. Kwak, Jae-Hyun Jeong, Heon-Bok Lee, W. Lim, Ki-Se Kim, Ki‐Won Kim, Dong-Suck Kim, Jung-Hee Lee","doi":"10.1109/ISPSD.2012.6229070","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229070","url":null,"abstract":"AlGaN/GaN Schottky barrier diodes (SBDs) with and without in-situ silicon carbon nitride (SiCN) cap layer were investigated. The fabricated SBD with SiCN cap layer exhibited improved electrical characteristics, such as the forward turn on voltage of about 0.7 V, the forward current of 4.1 A at 1.5 V, and the reverse breakdown voltage of 630 V, compared to the corresponding values of 0.8 V, 3.8 A, and 580 V for the reference SBD without the SiCN cap layer. This improvement in the device performance of the SiCN-SBD is because the in-situ SiCN cap layer not only lowers the barrier height, but also effectively passivates the surface of the device with better surface morphology.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124789654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229079
H. Hirai, Y. Kasho, M. Tsukuda, I. Omura
Bonding wire current measurement technique has been highly desired to analyze failure phenomena, such as short circuit and avalanche destruction of IGBT and power diode. This paper challenged to measure bonding wire current distribution in an IGBT module with the multiple tiny film current sensors and the digital calculation technique. The authors successfully measured bonding wire current under a single shot measurement.
{"title":"Bonding wire current measurement with tiny film current sensors","authors":"H. Hirai, Y. Kasho, M. Tsukuda, I. Omura","doi":"10.1109/ISPSD.2012.6229079","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229079","url":null,"abstract":"Bonding wire current measurement technique has been highly desired to analyze failure phenomena, such as short circuit and avalanche destruction of IGBT and power diode. This paper challenged to measure bonding wire current distribution in an IGBT module with the multiple tiny film current sensors and the digital calculation technique. The authors successfully measured bonding wire current under a single shot measurement.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123103707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229092
O. Hilt, Eldad Bahat Treidel, E. Cho, S. Singwald, J. Wurfl
Switching experiments with normally-off GaN-HFETs using a carbon-doped GaN buffer or an AlGaN buffer showed very different magnitudes of increased dynamic on-state resistance. The dynamic on-state resistance is analyzed for variations in buffer composition and set into relation to the buffer voltage-blocking strength. Also, the impact of p-GaN gate normally-off and Schottky-gate normally-on device technologies on the dispersion is studied. It is concluded that a buffer with less trap sites and lower breakdown strength is more favorable for high-voltage switching than a buffer with incorporated acceptors to increase the buffer breakdown strength.
{"title":"Impact of buffer composition on the dynamic on-state resistance of high-voltage AlGaN/GaN HFETs","authors":"O. Hilt, Eldad Bahat Treidel, E. Cho, S. Singwald, J. Wurfl","doi":"10.1109/ISPSD.2012.6229092","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229092","url":null,"abstract":"Switching experiments with normally-off GaN-HFETs using a carbon-doped GaN buffer or an AlGaN buffer showed very different magnitudes of increased dynamic on-state resistance. The dynamic on-state resistance is analyzed for variations in buffer composition and set into relation to the buffer voltage-blocking strength. Also, the impact of p-GaN gate normally-off and Schottky-gate normally-on device technologies on the dispersion is studied. It is concluded that a buffer with less trap sites and lower breakdown strength is more favorable for high-voltage switching than a buffer with incorporated acceptors to increase the buffer breakdown strength.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123342212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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