Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229064
Junji Cheng, Xingbi Chen
A novel p-type DP-OPTVLD (Double-Paths & OPTimum-Variational-Lateral-Doping) LDMOS is proposed. It features the double hole-conductive paths formed by a top and a buried p-layer in the drift region using OPTVLD technique, which significantly contribute to reducing device specific on-resistance. The design principle and electrical characteristics of the proposed structure are investigated theoretically and experimentally. Simulation results show that the specific on-resistances are 155/689 mΩ·cm2 with breakdown voltages of 300/800 V for the proposed structure, respectively, which are less than 60% of that with corresponding breakdown voltages for the conventional structure. This structure used as high-side can apply to SPIC with a low integration difficulty and a low fabrication cost.
{"title":"Low specific on-resistance p-type OPTVLDLDMOS with double hole-conductive paths for SPIC application","authors":"Junji Cheng, Xingbi Chen","doi":"10.1109/ISPSD.2012.6229064","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229064","url":null,"abstract":"A novel p-type DP-OPTVLD (Double-Paths & OPTimum-Variational-Lateral-Doping) LDMOS is proposed. It features the double hole-conductive paths formed by a top and a buried p-layer in the drift region using OPTVLD technique, which significantly contribute to reducing device specific on-resistance. The design principle and electrical characteristics of the proposed structure are investigated theoretically and experimentally. Simulation results show that the specific on-resistances are 155/689 mΩ·cm2 with breakdown voltages of 300/800 V for the proposed structure, respectively, which are less than 60% of that with corresponding breakdown voltages for the conventional structure. This structure used as high-side can apply to SPIC with a low integration difficulty and a low fabrication cost.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115936398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229021
Xiangming Fang, Rongxiang Wu, Lulu Peng, J. Sin
In this paper, a new tapered silicon-embedded coreless power inductor is proposed and demonstrated. The width and depth for the different turns of the inductor are designed with different values to reduce the proximity effect. An 18.6 nH inductance and a peak Q factor of 12.1 are achieved at 23 MHz within a chip area of 0.8 mm2. The AC power loss of the inductor is reduced by a maximum of 56% using the novel design. The inductor shows a peak efficiency of 91% in ZVS conversion applications, and is the highest in monolithic ZVS DC-DC converters reported so far.
{"title":"A new embedded inductor for ZVS DC-DC converter applications","authors":"Xiangming Fang, Rongxiang Wu, Lulu Peng, J. Sin","doi":"10.1109/ISPSD.2012.6229021","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229021","url":null,"abstract":"In this paper, a new tapered silicon-embedded coreless power inductor is proposed and demonstrated. The width and depth for the different turns of the inductor are designed with different values to reduce the proximity effect. An 18.6 nH inductance and a peak Q factor of 12.1 are achieved at 23 MHz within a chip area of 0.8 mm2. The AC power loss of the inductor is reduced by a maximum of 56% using the novel design. The inductor shows a peak efficiency of 91% in ZVS conversion applications, and is the highest in monolithic ZVS DC-DC converters reported so far.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115976075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229067
R. Chu, D. Brown, D. Zehnder, Xu Chen, A. Williams, R. Li, M. Chen, S. Newell, K. Boutros
We report a GaN-on-Si metal-insulator-semiconductor field-effect transistor (MISFET) with normally-off operation and 600-V blocking capability at 200 °C temperature. The temperature-dependences of threshold voltage, on-resistance, and leakage characteristics are discussed.
{"title":"Normally-off GaN-on-Si metal-insulator-semiconductor field-effect transistor with 600-V blocking capability at 200 °C","authors":"R. Chu, D. Brown, D. Zehnder, Xu Chen, A. Williams, R. Li, M. Chen, S. Newell, K. Boutros","doi":"10.1109/ISPSD.2012.6229067","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229067","url":null,"abstract":"We report a GaN-on-Si metal-insulator-semiconductor field-effect transistor (MISFET) with normally-off operation and 600-V blocking capability at 200 °C temperature. The temperature-dependences of threshold voltage, on-resistance, and leakage characteristics are discussed.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115393315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229066
A. Tanaka, S. Ogata, T. Izumi, K. Nakayama, T. Hayashi, Y. Miyanagi, K. Asano
The reliability of SiC bipolar device modules consisting of SiC commutated gate turn-off thyristors and SiC pin diodes fabricated on a 4° off-cut SiC substrate is investigated. According to three-phase inverter operation using a Back to Back system at DC bus voltage of 2 kV and effective output power of approximately 120 kW, the SiC module could achieve the world's first successful inverter operation lasting more than 1000 hours, thereby verifying its reliability in long time inverter operation.
{"title":"Reliability investigation of SiC bipolar device module in long time inverter operation","authors":"A. Tanaka, S. Ogata, T. Izumi, K. Nakayama, T. Hayashi, Y. Miyanagi, K. Asano","doi":"10.1109/ISPSD.2012.6229066","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229066","url":null,"abstract":"The reliability of SiC bipolar device modules consisting of SiC commutated gate turn-off thyristors and SiC pin diodes fabricated on a 4° off-cut SiC substrate is investigated. According to three-phase inverter operation using a Back to Back system at DC bus voltage of 2 kV and effective output power of approximately 120 kW, the SiC module could achieve the world's first successful inverter operation lasting more than 1000 hours, thereby verifying its reliability in long time inverter operation.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"227 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123306671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229081
B. Mouawad, C. Buttay, M. Soueidan, H. Morel, V. Bley, D. Fabrègue, F. Mercier
Silicon Carbide (SiC) is a good candidate for high temperature power electronic applications. To ensure good reliability, packaging materials with a coefficient of thermal expansion (CTE) matching that of SiC are needed. A metallized ceramic substrate based on aluminium nitride (AlN) and molybdenum (Mo) is reported in this paper. This substrate is built using a spark plasma sintering equipment. Results show that a dense Mo layer can be sintered on an AlN plate, with good adhesion, forming a Mo/AlN/Mo structure with well-matched CTEs.
{"title":"Sintered molybdenum for a metallized ceramic substrate packaging for the wide-bandgap devices and high temperature applications","authors":"B. Mouawad, C. Buttay, M. Soueidan, H. Morel, V. Bley, D. Fabrègue, F. Mercier","doi":"10.1109/ISPSD.2012.6229081","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229081","url":null,"abstract":"Silicon Carbide (SiC) is a good candidate for high temperature power electronic applications. To ensure good reliability, packaging materials with a coefficient of thermal expansion (CTE) matching that of SiC are needed. A metallized ceramic substrate based on aluminium nitride (AlN) and molybdenum (Mo) is reported in this paper. This substrate is built using a spark plasma sintering equipment. Results show that a dense Mo layer can be sintered on an AlN plate, with good adhesion, forming a Mo/AlN/Mo structure with well-matched CTEs.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131464456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229044
B. Boksteen, S. Dhar, A. Heringa, G. Koops, R. Hueting
It has previously been reported that the lateral electric field (Ex) in the drain extension of thin SOI HV (700V) field plate assisted RESURF devices can be extracted from their ID-VD characteristics in the subthreshold regime. In this work the prerequisites for valid field extraction and the (voltage) range of validity are established for linearly graded drain extension based RESURF devices through a combination of analytical calculations and TCAD device modeling. It is shown that the most important condition for field extraction is that an increment dVDS should not affect the lateral field at the already depleted zone. This unique condition is found to be met in the drain extension at distances larger than a specific length (5.3λ) governed by the drain extension silicon and oxide thicknesses. For realistic device parameters the method is shown to hold for devices with a BVDS of ~ 150V and higher.
{"title":"Extraction of the electric field in field plate assisted RESURF devices","authors":"B. Boksteen, S. Dhar, A. Heringa, G. Koops, R. Hueting","doi":"10.1109/ISPSD.2012.6229044","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229044","url":null,"abstract":"It has previously been reported that the lateral electric field (Ex) in the drain extension of thin SOI HV (700V) field plate assisted RESURF devices can be extracted from their ID-VD characteristics in the subthreshold regime. In this work the prerequisites for valid field extraction and the (voltage) range of validity are established for linearly graded drain extension based RESURF devices through a combination of analytical calculations and TCAD device modeling. It is shown that the most important condition for field extraction is that an increment dVDS should not affect the lateral field at the already depleted zone. This unique condition is found to be met in the drain extension at distances larger than a specific length (5.3λ) governed by the drain extension silicon and oxide thicknesses. For realistic device parameters the method is shown to hold for devices with a BVDS of ~ 150V and higher.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131464971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229093
N. Lophitis, Marina Antoniou, F. Udrea, I. Nistor, Martin Arnold, T. Wikstrom, Jan Vobecky
In this paper we present a wafer level three-dimensional simulation model of the Gate Commutated Thyristor (GCT) under inductive switching conditions. The simulations are validated by extensive experimental measurements. To the authors' knowledge such a complex simulation domain has not been used so far. This method allows the in depth study of large area devices such as GCTs, Gate Turn Off Thyristors (GTOs) and Phase Control Thyristors (PCTs). The model captures complex phenomena, such as current filamentation including subsequent failure, which allow us to predict the Maximum Controllable turn-off Current (MCC) and the Safe Operating Area (SOA) previously impossible using 2D distributed models.
{"title":"Experimentally validated three dimensional GCT wafer level simulations","authors":"N. Lophitis, Marina Antoniou, F. Udrea, I. Nistor, Martin Arnold, T. Wikstrom, Jan Vobecky","doi":"10.1109/ISPSD.2012.6229093","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229093","url":null,"abstract":"In this paper we present a wafer level three-dimensional simulation model of the Gate Commutated Thyristor (GCT) under inductive switching conditions. The simulations are validated by extensive experimental measurements. To the authors' knowledge such a complex simulation domain has not been used so far. This method allows the in depth study of large area devices such as GCTs, Gate Turn Off Thyristors (GTOs) and Phase Control Thyristors (PCTs). The model captures complex phenomena, such as current filamentation including subsequent failure, which allow us to predict the Maximum Controllable turn-off Current (MCC) and the Safe Operating Area (SOA) previously impossible using 2D distributed models.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132915597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229076
Young-shil Kim, M. Ha, O. Seok, W. An, M. Han
We have proposed and fabricated AlGaN/GaN HEMTs employing a nickel oxide (NiOX) based double metal structure which showed a stable reverse blocking characteristics. The leakage current of the proposed device was decreased by four orders of magnitude. The leakage current of the conventional device at room temperature was 80 μA/mm while that of the proposed device was 16.6 nA/mm. In the high temperature reverse bias (HTRB) test, the ratio of the gate leakage current to the total leakage was decreased with operational temperature. From experimental results of the HTRB test, it was demonstrated that NiOX-based double gate contact was thermally and electrically robust and made a significant contribution to stable blocking operation. In terms of the breakdown behavior, the device with a double metal structure successfully suppressed the premature breakdown while conventional one showed a soft breakdown behavior. The measured breakdown voltage (VBR) of the conventional device was 1310 V while VBR of the proposed device was 1480 V with almost no walkout. The stable reverse blocking characteristics of the proposed device was attributed to the resistance switching property of the nickel oxide film and the high barrier height established between thermally oxidized nickel film and surface of the device.
{"title":"High breakdown AlGaN/GaN HEMTs employing double metal structure","authors":"Young-shil Kim, M. Ha, O. Seok, W. An, M. Han","doi":"10.1109/ISPSD.2012.6229076","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229076","url":null,"abstract":"We have proposed and fabricated AlGaN/GaN HEMTs employing a nickel oxide (NiOX) based double metal structure which showed a stable reverse blocking characteristics. The leakage current of the proposed device was decreased by four orders of magnitude. The leakage current of the conventional device at room temperature was 80 μA/mm while that of the proposed device was 16.6 nA/mm. In the high temperature reverse bias (HTRB) test, the ratio of the gate leakage current to the total leakage was decreased with operational temperature. From experimental results of the HTRB test, it was demonstrated that NiOX-based double gate contact was thermally and electrically robust and made a significant contribution to stable blocking operation. In terms of the breakdown behavior, the device with a double metal structure successfully suppressed the premature breakdown while conventional one showed a soft breakdown behavior. The measured breakdown voltage (VBR) of the conventional device was 1310 V while VBR of the proposed device was 1480 V with almost no walkout. The stable reverse blocking characteristics of the proposed device was attributed to the resistance switching property of the nickel oxide film and the high barrier height established between thermally oxidized nickel film and surface of the device.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"58 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132708499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229019
Zhongda Li, J. Waldron, R. Dayal, L. Parsa, M. Hella, T. Chow
We report our experimental results on high voltage normally-off GaN MOS channel HEMTs (MOSC-HEMT) on silicon substrates with best specific on-resistance (Ron,sp) of 4 mΩ-cm2 and breakdown voltage (BV) of 840V. The switching performance of the device was evaluated by SPICE simulations of a buck-boost converter and showed a system efficiency of 10% higher than that using a commercial GaN HEMT. A bidirectional switch consisted two GaN MOSC-HEMTs were also demonstrated.
{"title":"High voltage normally-off GaN MOSC-HEMTs on silicon substrates for power switching applications","authors":"Zhongda Li, J. Waldron, R. Dayal, L. Parsa, M. Hella, T. Chow","doi":"10.1109/ISPSD.2012.6229019","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229019","url":null,"abstract":"We report our experimental results on high voltage normally-off GaN MOS channel HEMTs (MOSC-HEMT) on silicon substrates with best specific on-resistance (Ron,sp) of 4 mΩ-cm2 and breakdown voltage (BV) of 840V. The switching performance of the device was evaluated by SPICE simulations of a buck-boost converter and showed a system efficiency of 10% higher than that using a commercial GaN HEMT. A bidirectional switch consisted two GaN MOSC-HEMTs were also demonstrated.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134462938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229089
D. Jin, Jesus A. del Alamo
We have developed a new methodology to study the dynamic ON-resistance (RON) of high-voltage GaN High-Electron-Mobility Transistors (HEMTs). With this technique, we have investigated dynamic RON transients over a time span of 11 decades. In OFF to ON time transients, we observe a fast release of trapped electrons through a temperature-independent tunneling process. We attribute this to border traps at the AlGaN barrier/AlN spacer interface. Over a longer time scale, we observe conventional thermally activated electron detrapping from traps at the surface of the device or inside the AlGaN barrier. These findings provide a path for power switching device engineering with minimum dynamic RON.
我们开发了一种新的方法来研究高压氮化镓高电子迁移率晶体管的动态导通电阻(RON)。使用这种技术，我们已经研究了11年时间跨度内的动态RON瞬态。在OFF - to - ON时间瞬态中，我们观察到捕获电子通过与温度无关的隧道过程快速释放。我们将其归因于AlGaN势垒/AlN间隔层界面的边界陷阱。在更长的时间尺度上，我们观察到传统的热激活电子从器件表面或AlGaN势垒内部的陷阱中脱出。这些发现为动态RON最小的功率开关器件工程提供了一条途径。
{"title":"Mechanisms responsible for dynamic ON-resistance in GaN high-voltage HEMTs","authors":"D. Jin, Jesus A. del Alamo","doi":"10.1109/ISPSD.2012.6229089","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229089","url":null,"abstract":"We have developed a new methodology to study the dynamic ON-resistance (RON) of high-voltage GaN High-Electron-Mobility Transistors (HEMTs). With this technique, we have investigated dynamic RON transients over a time span of 11 decades. In OFF to ON time transients, we observe a fast release of trapped electrons through a temperature-independent tunneling process. We attribute this to border traps at the AlGaN barrier/AlN spacer interface. Over a longer time scale, we observe conventional thermally activated electron detrapping from traps at the surface of the device or inside the AlGaN barrier. These findings provide a path for power switching device engineering with minimum dynamic RON.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116410082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：