Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229068
S. Khandelwal, T. Fjeldly
In this paper we present a physics based analytical model for the drain current Id in AlGaN/GaN high electron mobility transistors. The proposed model is developed based on the analytical 2-D electron gas density ns model developed previously by our group. The model includes important effects like velocity saturation, channel length modulation, short channel effect, pinch-off, mobility degradation, and self-heating. The model is in excellent agreement with the experimental data over a typical range of applied gate and drain voltages for various device geometries.
{"title":"A physics based compact model for drain current in AlGaN/GaN HEMT devices","authors":"S. Khandelwal, T. Fjeldly","doi":"10.1109/ISPSD.2012.6229068","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229068","url":null,"abstract":"In this paper we present a physics based analytical model for the drain current Id in AlGaN/GaN high electron mobility transistors. The proposed model is developed based on the analytical 2-D electron gas density ns model developed previously by our group. The model includes important effects like velocity saturation, channel length modulation, short channel effect, pinch-off, mobility degradation, and self-heating. The model is in excellent agreement with the experimental data over a typical range of applied gate and drain voltages for various device geometries.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115795800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229085
M. Mahmud, Z. Çelik-Butler, Xu Cheng, Weixiao Huang, P. Hao, P. Srinivasan, F. Hou, B. Amey, S. Pendharkar
1/f noise analysis is implemented as a quantitative measure for the dielectric/silicon interface related reliability and degradation in RESURF lateral double-diffused MOS transistors. The effect of DC stress on 1/f noise performance as well as on the location of stress induced degradation have been investigated with respect to stressing time in differently processed low and medium voltage LDMOS. The distribution of traps has been extracted spatially into the oxide and as a function of band-gap energy. The effect of LDMOS drift length to noise degradation has been studied.
{"title":"Experimental analysis of DC and noise parameter degradation in n-channel reduced surface field (RESURF) LDMOS transistors","authors":"M. Mahmud, Z. Çelik-Butler, Xu Cheng, Weixiao Huang, P. Hao, P. Srinivasan, F. Hou, B. Amey, S. Pendharkar","doi":"10.1109/ISPSD.2012.6229085","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229085","url":null,"abstract":"1/f noise analysis is implemented as a quantitative measure for the dielectric/silicon interface related reliability and degradation in RESURF lateral double-diffused MOS transistors. The effect of DC stress on 1/f noise performance as well as on the location of stress induced degradation have been investigated with respect to stressing time in differently processed low and medium voltage LDMOS. The distribution of traps has been extracted spatially into the oxide and as a function of band-gap energy. The effect of LDMOS drift length to noise degradation has been studied.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114860480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229052
M. Tanaka, I. Omura
Deep trench gate is used for latest IGBT to improve device performance. By large difference from deep submicron CMOS structure, there is no process compatibility among CMOS device and trench gate IGBT. We propose IGBT scaling rule for shrinking IGBT cell structure both horizontally and vertically. The scaling rule is theoretically delivered by structure based equations. Device performance improvement was also predicted by TCAD simulations even with very shallow trench gate. The rule enables to produce trench gate IGBT on large diameter wafer in CMOS factory with superior productivity.
{"title":"Scaling rule for very shallow trench IGBT toward CMOS process compatibility","authors":"M. Tanaka, I. Omura","doi":"10.1109/ISPSD.2012.6229052","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229052","url":null,"abstract":"Deep trench gate is used for latest IGBT to improve device performance. By large difference from deep submicron CMOS structure, there is no process compatibility among CMOS device and trench gate IGBT. We propose IGBT scaling rule for shrinking IGBT cell structure both horizontally and vertically. The scaling rule is theoretically delivered by structure based equations. Device performance improvement was also predicted by TCAD simulations even with very shallow trench gate. The rule enables to produce trench gate IGBT on large diameter wafer in CMOS factory with superior productivity.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129777367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229104
Shigeki Takahashi, A. Akio, Y. Youichi, S. Satoshi, N. Norihito
We have successfully developed novel extraction enhanced lateral insulated gate bipolar transistors (E2LIGBTs), which exhibit super-high speed switching of 34 ns turn-off time and a low on-state voltage of 3.7 V at 84 A/cm2 simultaneously with a high breakdown voltage of 738V. For the first time, E2LIGBTs have exceeded the counterpart lateral DMOS both in switching speed and in on-resistance. The superior performance is achieved by the novel anode structure consisting of a narrow p+-injector and a wide Schottky contact on a lightly doped p-layer over an n-buffer. The on-state voltage can be further reduced to 3.0V at 84 A/cm2 by introducing Carrier Storage (CS) layer. The developed E2LIGBTs achieved the best trade-off between on-resistance and switching speed among all the lateral MOS power devices, so far reported.
我们成功开发了一种新型的提取增强侧绝缘栅双极晶体管(e2lightts)，该晶体管具有34 ns关断时间的超高速开关和84 a /cm2时3.7 V的低导通电压，同时具有738V的高击穿电压。第一次，e2light在开关速度和导通电阻方面都超过了对应的横向DMOS。该新型阳极结构由窄的p+注入器和宽的肖特基触点组成，在n缓冲层上的轻掺杂p层上实现了优越的性能。通过引入载波存储(CS)层，可以进一步将导通电压降低到84 A/cm2时的3.0V。开发的e2lights在所有横向MOS功率器件中实现了导通电阻和开关速度之间的最佳权衡。
{"title":"Carrier-storage effect and extraction-enhanced lateral IGBT (E2LIGBT): A super-high speed and low on-state voltage LIGBT superior to LDMOSFET","authors":"Shigeki Takahashi, A. Akio, Y. Youichi, S. Satoshi, N. Norihito","doi":"10.1109/ISPSD.2012.6229104","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229104","url":null,"abstract":"We have successfully developed novel extraction enhanced lateral insulated gate bipolar transistors (E2LIGBTs), which exhibit super-high speed switching of 34 ns turn-off time and a low on-state voltage of 3.7 V at 84 A/cm2 simultaneously with a high breakdown voltage of 738V. For the first time, E2LIGBTs have exceeded the counterpart lateral DMOS both in switching speed and in on-resistance. The superior performance is achieved by the novel anode structure consisting of a narrow p+-injector and a wide Schottky contact on a lightly doped p-layer over an n-buffer. The on-state voltage can be further reduced to 3.0V at 84 A/cm2 by introducing Carrier Storage (CS) layer. The developed E2LIGBTs achieved the best trade-off between on-resistance and switching speed among all the lateral MOS power devices, so far reported.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129095237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229041
E. Marcault, A. Bourennane, M. Breil, P. Tounsi, P. Dupuy
This paper deals with the power assembly failure anticipation by monitoring its mechanical state. From this perspective, we evaluate the impact of mechanical stress accumulation before crack opening on the electrical characteristics of a VDMOS transistor using 2D physical simulations. The power device I(V) characteristics depend both on temperature and mechanical stress. To estimate the impact of mechanical stress on the VDMOS I(V) characteristics, we exploit the VDMOS Zero Thermal Coefficient operating point. At this operating point, the VDMOS I(V) characteristics are temperature independent.
{"title":"Using zero thermal coefficient point property for VDMOS power devices health monitoring","authors":"E. Marcault, A. Bourennane, M. Breil, P. Tounsi, P. Dupuy","doi":"10.1109/ISPSD.2012.6229041","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229041","url":null,"abstract":"This paper deals with the power assembly failure anticipation by monitoring its mechanical state. From this perspective, we evaluate the impact of mechanical stress accumulation before crack opening on the electrical characteristics of a VDMOS transistor using 2D physical simulations. The power device I(V) characteristics depend both on temperature and mechanical stress. To estimate the impact of mechanical stress on the VDMOS I(V) characteristics, we exploit the VDMOS Zero Thermal Coefficient operating point. At this operating point, the VDMOS I(V) characteristics are temperature independent.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126943730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229049
A. Irace, P. Spirito, M. Riccio, G. Breglio
The aim of this paper is to analyze the typical voltage and current waveforms of UIS test in order to find signature of uneven current conduction behavior. This information could help the identification of phenomena that can eventually lead to device failure, reduce its capability of sustaining high currents in avalanche operation or impair long-term device reliability.
{"title":"Voltage drops, sawtooth oscillations and HF bursts in Breakdown Current and Voltage waveforms during UIS experiments","authors":"A. Irace, P. Spirito, M. Riccio, G. Breglio","doi":"10.1109/ISPSD.2012.6229049","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229049","url":null,"abstract":"The aim of this paper is to analyze the typical voltage and current waveforms of UIS test in order to find signature of uneven current conduction behavior. This information could help the identification of phenomena that can eventually lead to device failure, reduce its capability of sustaining high currents in avalanche operation or impair long-term device reliability.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126427510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229109
R. Germana
A sensefet monitoring is used for overload, open-load detection and load current analog feedback. The sensefet matching properties to the main power mos represent the main quality factor of the device. Its current should be proportional to the main power one, maintaining the same coefficient over the entire temperature and biasing working range. In this work the effects of the edge cells layout and process are analyzed by the help of 3D device simulations. The causes for the real to theoretical ratio mismatch and the drift behavior versus the temperature are put into evidence. The corrective actions allow to reach 1÷2% of drift in the range -40°C to 150°C. Only technological considerations are here faced, concerning the construction and optimization of the structure.
{"title":"Power mos current sensefet temperature drift study and improvement by the help of 3D simulations","authors":"R. Germana","doi":"10.1109/ISPSD.2012.6229109","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229109","url":null,"abstract":"A sensefet monitoring is used for overload, open-load detection and load current analog feedback. The sensefet matching properties to the main power mos represent the main quality factor of the device. Its current should be proportional to the main power one, maintaining the same coefficient over the entire temperature and biasing working range. In this work the effects of the edge cells layout and process are analyzed by the help of 3D device simulations. The causes for the real to theoretical ratio mismatch and the drift behavior versus the temperature are put into evidence. The corrective actions allow to reach 1÷2% of drift in the range -40°C to 150°C. Only technological considerations are here faced, concerning the construction and optimization of the structure.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133292053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229046
S. Soneda, A. Narazaki, T. Takahashi, K. Takano, S. Kido, Y. Fukada, K. Taguchi, T. Terashima
In this paper, we investigate a mechanism of drain-voltage oscillation of MOSFET under high dV/dt UIS condition by using numerical simulation and experiments. One of the trigger events of the oscillation is found to be the current path switching between the active region and the termination region with close BVDSS characteristics. By optimizing the device parameters to make appropriate the BVDSS balance, avalanche capability is improved over ~ 40%, enabling the oscillation-free turn-off.
{"title":"Analysis of a drain-voltage oscillation of MOSFET under high dV/dt UIS condition","authors":"S. Soneda, A. Narazaki, T. Takahashi, K. Takano, S. Kido, Y. Fukada, K. Taguchi, T. Terashima","doi":"10.1109/ISPSD.2012.6229046","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229046","url":null,"abstract":"In this paper, we investigate a mechanism of drain-voltage oscillation of MOSFET under high dV/dt UIS condition by using numerical simulation and experiments. One of the trigger events of the oscillation is found to be the current path switching between the active region and the termination region with close BVDSS characteristics. By optimizing the device parameters to make appropriate the BVDSS balance, avalanche capability is improved over ~ 40%, enabling the oscillation-free turn-off.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132346746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229071
S. Harada, M. Kato, T. Kojima, K. Ariyoshi, Y. Tanaka, H. Okumura
A critical issue for the 4H-SiC UMOSFET is a shielding of the gate oxide at the bottom of the trench gate from the high electric field during the blocking state. This study develops the UMOSFET structure with low specific on-resistance and low electric field in the gate oxide by the two-dimensional numerical device simulation. The gate oxide field is successfully decreased without the degradation of the on-resistance by the structure with the buried p-base region. Furthermore, two-zone Superjunction structure that applies the buried p-base region is also proposed for the 3300 V device.
{"title":"Determination of optimum structure of 4H-SiC Trench MOSFET","authors":"S. Harada, M. Kato, T. Kojima, K. Ariyoshi, Y. Tanaka, H. Okumura","doi":"10.1109/ISPSD.2012.6229071","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229071","url":null,"abstract":"A critical issue for the 4H-SiC UMOSFET is a shielding of the gate oxide at the bottom of the trench gate from the high electric field during the blocking state. This study develops the UMOSFET structure with low specific on-resistance and low electric field in the gate oxide by the two-dimensional numerical device simulation. The gate oxide field is successfully decreased without the degradation of the on-resistance by the structure with the buried p-base region. Furthermore, two-zone Superjunction structure that applies the buried p-base region is also proposed for the 3300 V device.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122050957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229014
Ze Chen, K. Nakamura, T. Terashima
In this paper, the phenomena of current crowding and impact ionization in edge termination of High-Voltage (HV) LPT(II)-CSTBT™(III) is investigated. It is discovered for the first time that these two phenomena act as separated heat sources and induce one local hot spot which causes the thermal destruction in the edge termination during large current and high voltage turn-off switching. A novel edge termination design called “Partial P Collector” is proposed and evaluated. The novel design reduces current crowding and relaxes electric field in the edge termination. Simulated and measured results show that the failure mode of the novel design is determined by current filament phenomenon inside active cell region. It concludes that HV LPT(II)-CSTBT™(III) utilizing Partial P Collector edge termination design has ultra robust turn-off capability without deteriorating other electrical performances.
{"title":"LPT(II)-CSTBT™(III) for High Voltage application with ultra robust turn-off capability utilizing novel edge termination design","authors":"Ze Chen, K. Nakamura, T. Terashima","doi":"10.1109/ISPSD.2012.6229014","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229014","url":null,"abstract":"In this paper, the phenomena of current crowding and impact ionization in edge termination of High-Voltage (HV) LPT(II)-CSTBT™(III) is investigated. It is discovered for the first time that these two phenomena act as separated heat sources and induce one local hot spot which causes the thermal destruction in the edge termination during large current and high voltage turn-off switching. A novel edge termination design called “Partial P Collector” is proposed and evaluated. The novel design reduces current crowding and relaxes electric field in the edge termination. Simulated and measured results show that the failure mode of the novel design is determined by current filament phenomenon inside active cell region. It concludes that HV LPT(II)-CSTBT™(III) utilizing Partial P Collector edge termination design has ultra robust turn-off capability without deteriorating other electrical performances.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114966254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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