Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229014
Ze Chen, K. Nakamura, T. Terashima
In this paper, the phenomena of current crowding and impact ionization in edge termination of High-Voltage (HV) LPT(II)-CSTBT™(III) is investigated. It is discovered for the first time that these two phenomena act as separated heat sources and induce one local hot spot which causes the thermal destruction in the edge termination during large current and high voltage turn-off switching. A novel edge termination design called “Partial P Collector” is proposed and evaluated. The novel design reduces current crowding and relaxes electric field in the edge termination. Simulated and measured results show that the failure mode of the novel design is determined by current filament phenomenon inside active cell region. It concludes that HV LPT(II)-CSTBT™(III) utilizing Partial P Collector edge termination design has ultra robust turn-off capability without deteriorating other electrical performances.
{"title":"LPT(II)-CSTBT™(III) for High Voltage application with ultra robust turn-off capability utilizing novel edge termination design","authors":"Ze Chen, K. Nakamura, T. Terashima","doi":"10.1109/ISPSD.2012.6229014","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229014","url":null,"abstract":"In this paper, the phenomena of current crowding and impact ionization in edge termination of High-Voltage (HV) LPT(II)-CSTBT™(III) is investigated. It is discovered for the first time that these two phenomena act as separated heat sources and induce one local hot spot which causes the thermal destruction in the edge termination during large current and high voltage turn-off switching. A novel edge termination design called “Partial P Collector” is proposed and evaluated. The novel design reduces current crowding and relaxes electric field in the edge termination. Simulated and measured results show that the failure mode of the novel design is determined by current filament phenomenon inside active cell region. It concludes that HV LPT(II)-CSTBT™(III) utilizing Partial P Collector edge termination design has ultra robust turn-off capability without deteriorating other electrical performances.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114966254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229071
S. Harada, M. Kato, T. Kojima, K. Ariyoshi, Y. Tanaka, H. Okumura
A critical issue for the 4H-SiC UMOSFET is a shielding of the gate oxide at the bottom of the trench gate from the high electric field during the blocking state. This study develops the UMOSFET structure with low specific on-resistance and low electric field in the gate oxide by the two-dimensional numerical device simulation. The gate oxide field is successfully decreased without the degradation of the on-resistance by the structure with the buried p-base region. Furthermore, two-zone Superjunction structure that applies the buried p-base region is also proposed for the 3300 V device.
{"title":"Determination of optimum structure of 4H-SiC Trench MOSFET","authors":"S. Harada, M. Kato, T. Kojima, K. Ariyoshi, Y. Tanaka, H. Okumura","doi":"10.1109/ISPSD.2012.6229071","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229071","url":null,"abstract":"A critical issue for the 4H-SiC UMOSFET is a shielding of the gate oxide at the bottom of the trench gate from the high electric field during the blocking state. This study develops the UMOSFET structure with low specific on-resistance and low electric field in the gate oxide by the two-dimensional numerical device simulation. The gate oxide field is successfully decreased without the degradation of the on-resistance by the structure with the buried p-base region. Furthermore, two-zone Superjunction structure that applies the buried p-base region is also proposed for the 3300 V device.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122050957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229032
S. Mouhoubi, Y. Wu, F. Bauwens, J. Roig, P. Gassot, M. Tack
This paper presents different methodologies to optimize devices of smart power technologies for robustness consideration. A split gate concept is used to improve the flatness of Id-Vd curves of the nVDMOS by maintaining the Intrinsic MOS in a stable operating regime. The split gate is also used to increase the BVdss of the pLDMOS. An additional buffer at the end of the drift region of the nLDMOS helps extending the SOA limits due to a controlled positive differential resistor branch.
{"title":"A family of robust DMOS devices for automotive applications","authors":"S. Mouhoubi, Y. Wu, F. Bauwens, J. Roig, P. Gassot, M. Tack","doi":"10.1109/ISPSD.2012.6229032","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229032","url":null,"abstract":"This paper presents different methodologies to optimize devices of smart power technologies for robustness consideration. A split gate concept is used to improve the flatness of Id-Vd curves of the nVDMOS by maintaining the Intrinsic MOS in a stable operating regime. The split gate is also used to increase the BVdss of the pLDMOS. An additional buffer at the end of the drift region of the nLDMOS helps extending the SOA limits due to a controlled positive differential resistor branch.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128765410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229101
H. Niwa, G. Feng, J. Suda, T. Kimoto
Ultrahigh-voltage 4H-SiC PiN diodes with improved junction termination extension (JTE) structures have been investigated. Breakdown characteristics of 4H-SiC PiN diodes with conventional single-zone JTE was shown to be severely affected by the charge near the SiO2/SiC interface from experiment and device simulation. Taking the effect of the interface charge into account, and by using “Space-Modulated” JTE structure with a wide optimum JTE-dose window to tolerate the impact of interface charge, we achieved a breakdown voltage of 21.7 kV (81 % of the ideal breakdown voltage calculated from the epilayer structure), which is the highest breakdown voltage among any semiconductor devices ever reported.
{"title":"Breakdown characteristics of 12–20 kV-class 4H-SiC PiN diodes with improved junction termination structures","authors":"H. Niwa, G. Feng, J. Suda, T. Kimoto","doi":"10.1109/ISPSD.2012.6229101","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229101","url":null,"abstract":"Ultrahigh-voltage 4H-SiC PiN diodes with improved junction termination extension (JTE) structures have been investigated. Breakdown characteristics of 4H-SiC PiN diodes with conventional single-zone JTE was shown to be severely affected by the charge near the SiO2/SiC interface from experiment and device simulation. Taking the effect of the interface charge into account, and by using “Space-Modulated” JTE structure with a wide optimum JTE-dose window to tolerate the impact of interface charge, we achieved a breakdown voltage of 21.7 kV (81 % of the ideal breakdown voltage calculated from the epilayer structure), which is the highest breakdown voltage among any semiconductor devices ever reported.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130845754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229086
A. Dikshit, V. Subramanian, S. Pandharpure, S. Sirohi, T. Letavic
The effect of drift region on the flicker noise in LDMOS devices in the linear and saturation regions is analyzed using measured data and device simulations. In the linear region, noise in the drift region arises from gate-drain overlap region and is significant for longer channel length devices. For shorter channel length devices, the sub-surface current flow in the gate-drain overlap region reduces the contribution of noise from the drift region. In the saturation region, noise is dependent on quasi-saturation condition, and reaches its lowest value only when the channel is saturated.
{"title":"Influence of drift region on the 1/f noise in LDMOS","authors":"A. Dikshit, V. Subramanian, S. Pandharpure, S. Sirohi, T. Letavic","doi":"10.1109/ISPSD.2012.6229086","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229086","url":null,"abstract":"The effect of drift region on the flicker noise in LDMOS devices in the linear and saturation regions is analyzed using measured data and device simulations. In the linear region, noise in the drift region arises from gate-drain overlap region and is significant for longer channel length devices. For shorter channel length devices, the sub-surface current flow in the gate-drain overlap region reduces the contribution of noise from the drift region. In the saturation region, noise is dependent on quasi-saturation condition, and reaches its lowest value only when the channel is saturated.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124272347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229082
Hsueh-Rong Chang, J. Bu, Henning M. Hauenstein, Michael Wittmann, Jack Marcinkowski, Mark Pavier, Scott Palmer, Jim Tompkins
High power compact IGBT half bridge modules with a current rating of 300A and a blocking voltage of 650V using ultra thin IGBTs and diodes have been successfully developed with double-sided cooling capability. The wirebond-less package building block called COOLiR2DIE™ has a small area of 28.5 mm × 16 mm with a power rating 200 kVA, This is the most compact IGBT package reported today. A low on-state voltage of 1.6V at 300A is achieved in the wirebond-less package. The combination of lower on-state voltage and larger heat exchange area due to the solderable front metal (SFM), increases the IGBT module current carrying capability by 30%.
采用超薄IGBT和二极管的高功率紧凑型IGBT半桥模块已成功开发，额定电流为300A，阻塞电压为650V，具有双面冷却能力。称为COOLiR2DIE™的无线连接封装模块面积为28.5 mm × 16 mm，额定功率为200kva，这是目前报道的最紧凑的IGBT封装。在无线连接封装中实现了300A时1.6V的低导通电压。较低的导通电压和较大的热交换面积(由于可焊接的前金属(SFM))的组合，使IGBT模块的载流能力提高了30%。
{"title":"200 kVA compact IGBT modules with double-sided cooling for HEV and EV","authors":"Hsueh-Rong Chang, J. Bu, Henning M. Hauenstein, Michael Wittmann, Jack Marcinkowski, Mark Pavier, Scott Palmer, Jim Tompkins","doi":"10.1109/ISPSD.2012.6229082","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229082","url":null,"abstract":"High power compact IGBT half bridge modules with a current rating of 300A and a blocking voltage of 650V using ultra thin IGBTs and diodes have been successfully developed with double-sided cooling capability. The wirebond-less package building block called COOLiR2DIE™ has a small area of 28.5 mm × 16 mm with a power rating 200 kVA, This is the most compact IGBT package reported today. A low on-state voltage of 1.6V at 300A is achieved in the wirebond-less package. The combination of lower on-state voltage and larger heat exchange area due to the solderable front metal (SFM), increases the IGBT module current carrying capability by 30%.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126057474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229059
T. Nitta, Y. Yoshihisa, T. Kuroi, K. Hatasako, S. Maegawa, K. Onishi
In this paper, protection techniques against parasitic action due to minority carrier injection into substrate for Smart Power ICs have been presented. We investigated the protection efficiency of active type protection for various layout arrangements that are applicable to realistic IC, and found that the protection efficiency was strongly dependent on the layout. We propose the active type protection structure at collector side, which is effective at avoiding interferences from other components in realistic IC. We also found that separate type protection, which is one variation of the collector side protection, is more effective. The area penalty and the dependence of protection efficiency on temperature were also discussed.
{"title":"Enhanced active protection technique for substrate minority carrier injection in Smart Power IC","authors":"T. Nitta, Y. Yoshihisa, T. Kuroi, K. Hatasako, S. Maegawa, K. Onishi","doi":"10.1109/ISPSD.2012.6229059","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229059","url":null,"abstract":"In this paper, protection techniques against parasitic action due to minority carrier injection into substrate for Smart Power ICs have been presented. We investigated the protection efficiency of active type protection for various layout arrangements that are applicable to realistic IC, and found that the protection efficiency was strongly dependent on the layout. We propose the active type protection structure at collector side, which is effective at avoiding interferences from other components in realistic IC. We also found that separate type protection, which is one variation of the collector side protection, is more effective. The area penalty and the dependence of protection efficiency on temperature were also discussed.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126926037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229108
Jun Wang, Shuming Xu, J. Korec, F. Baiocchi
Power converters, e.g. in a popular synchronous buck topology, need high performance power MOSFETs in order to achieve high efficiency, low voltage ringing, ESD protection and low EMI. To satisfy these requirements, an asymmetric gate resistor power MOSFET is proposed by integrating a shunt resistor with a parallel LDMOSFET-connected diode in a source down power MOSFET (NexFET). The novel MOSFET has several advantages. First, the shunt resistor is used to slow down the turn-on speed of the high-side (HS) MOSFET, resulting in small voltage ringing of the switch node and low EMI in a synchronous buck converter. Second, the integrated diode preserves a fast turn-off speed and high conversion efficiency. Third, the bulk diode of the LDMOSFET can achieve ESD protection for gate oxide.
{"title":"Asymmetric gate resistor power MOSFET","authors":"Jun Wang, Shuming Xu, J. Korec, F. Baiocchi","doi":"10.1109/ISPSD.2012.6229108","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229108","url":null,"abstract":"Power converters, e.g. in a popular synchronous buck topology, need high performance power MOSFETs in order to achieve high efficiency, low voltage ringing, ESD protection and low EMI. To satisfy these requirements, an asymmetric gate resistor power MOSFET is proposed by integrating a shunt resistor with a parallel LDMOSFET-connected diode in a source down power MOSFET (NexFET). The novel MOSFET has several advantages. First, the shunt resistor is used to slow down the turn-on speed of the high-side (HS) MOSFET, resulting in small voltage ringing of the switch node and low EMI in a synchronous buck converter. Second, the integrated diode preserves a fast turn-off speed and high conversion efficiency. Third, the bulk diode of the LDMOSFET can achieve ESD protection for gate oxide.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126828781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229017
A. Fontserè, A. Pérez‐Tomás, V. Banu, P. Godignon, J. Millán, H. De Vleeschouwer, J. Parsey, P. Moens
Innovative 800V/300°C AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) fabricated with a 4-inch Si CMOS compatible technology are presented in this paper. High performance AlGaN/GaN MIS gated HEMT (MIS-HEMT) and passivated HEMT (i-HEMT) were fabricated using 5nm-thick HfO2, and 30nm-thick CVD Si3N4 as the gate and passivation insulator, respectively. Contact resistance maps yield reduced Rc of 1.32±0.26 Ωmm for Au-free compared to 0.86±0.58 Ωmm for conventional Au-based Ohmic metallization. The off-state breakdown voltage is around 800V with a specific on-resistance of 2 mΩcm2. Gate and drain leakage currents as well as dynamic I-V trapping are significantly improved with the MIS-HEMT architecture with almost no trade-off to the on-state.
{"title":"A HfO2 based 800V/300°C Au-free AlGaN/GaN-on-Si HEMT technology","authors":"A. Fontserè, A. Pérez‐Tomás, V. Banu, P. Godignon, J. Millán, H. De Vleeschouwer, J. Parsey, P. Moens","doi":"10.1109/ISPSD.2012.6229017","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229017","url":null,"abstract":"Innovative 800V/300°C AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) fabricated with a 4-inch Si CMOS compatible technology are presented in this paper. High performance AlGaN/GaN MIS gated HEMT (MIS-HEMT) and passivated HEMT (i-HEMT) were fabricated using 5nm-thick HfO<sub>2</sub>, and 30nm-thick CVD Si<sub>3</sub>N<sub>4</sub> as the gate and passivation insulator, respectively. Contact resistance maps yield reduced R<sub>c</sub> of 1.32±0.26 Ωmm for Au-free compared to 0.86±0.58 Ωmm for conventional Au-based Ohmic metallization. The off-state breakdown voltage is around 800V with a specific on-resistance of 2 mΩcm<sup>2</sup>. Gate and drain leakage currents as well as dynamic I-V trapping are significantly improved with the MIS-HEMT architecture with almost no trade-off to the on-state.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127810004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229084
Yandong He, Ganggang Zhang, Xing Zhang
The STI-based laterally diffused metal-oxide-semiconductor (LDMOS) devices have become popular with its better tradeoff between breakdown voltage and on-resistance and its compatibility with the standard complementary metal-oxide-semiconductor (CMOS) process. In this paper, a multi-region trap characterization direct current current-voltage (MR-DCIV) technique was proposed to characterize interface state generation in both channel and STI drift regions. The correlation between interface trap and MR-DCIV current has been verified by two-dimensional device simulation. Degradation of STI-based LDMOS transistors in various reliability stress modes is investigated experimentally by proposed technique. The impact of interface state location on device electrical characteristics is analyzed from measurement and simulation. Our study reveals that OFF-state stress becomes the worst degradation mode in term of the on-resistance degradation, which is attributed to interface state generation under STI drift region.
{"title":"A multi-region trap characterization method and its reliability application on STI-based high-voltage LDMOSFETs","authors":"Yandong He, Ganggang Zhang, Xing Zhang","doi":"10.1109/ISPSD.2012.6229084","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229084","url":null,"abstract":"The STI-based laterally diffused metal-oxide-semiconductor (LDMOS) devices have become popular with its better tradeoff between breakdown voltage and on-resistance and its compatibility with the standard complementary metal-oxide-semiconductor (CMOS) process. In this paper, a multi-region trap characterization direct current current-voltage (MR-DCIV) technique was proposed to characterize interface state generation in both channel and STI drift regions. The correlation between interface trap and MR-DCIV current has been verified by two-dimensional device simulation. Degradation of STI-based LDMOS transistors in various reliability stress modes is investigated experimentally by proposed technique. The impact of interface state location on device electrical characteristics is analyzed from measurement and simulation. Our study reveals that OFF-state stress becomes the worst degradation mode in term of the on-resistance degradation, which is attributed to interface state generation under STI drift region.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124522036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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