Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4549996
M. Lu, P. Lauro, D. Shih, R. Polastre, C. Goldsmith, D. W. Henderson, Hongqing Zhang, M. Cho
A series of electromigration (EM) experiments were undertaken to evaluate the time to failure performance of solder joints comprised of Sn-Ag and Sn-Cu alloys in combination with three solderable surface finishes, Cu, Ni-Au and Ni-Cu. The opposing pad structure in the solder joints was the same in all experiments and was comprised of a layered structure, simulating Ni based under - bump - metallurgies (UBM) for controlled collapse chip connection (C4). As anticipated the Sn grain size was large with the typical solder joint containing only a few grains. In all experiments, reported here, the electron current exited the pad with the surface finish under evaluation and passed into the solder. Two failure modes were identified. The manifested failure mode depended on the orientation of the c-axis of the larger Sn grains in the solder joint with respect to the applied current direction. When the c-axis is not closely aligned with the current direction, cavitation at solder-IMC interface leads to electrical failure. A more rapid failure mode occurred when the c-axis was closely aligned with the current direction. With this alignment the interfacial IMC structures were swept away by rapid diffusive processes from the pad surface and the pad material was quickly consumed. Interfacial void formation leads to rapid failure in this mode. The Sn-Ag solder appeared to demonstrate greater microstructural stability. But, clearly the best EM performance was seen with the addition of significant levels of Cu to the Sn-Ag alloy. This alloy modification showed the best EM lifetime in combination with a Ni pad structure.
{"title":"Comparison of electromigration performance for Pb-free solders and surface finishes with Ni UBM","authors":"M. Lu, P. Lauro, D. Shih, R. Polastre, C. Goldsmith, D. W. Henderson, Hongqing Zhang, M. Cho","doi":"10.1109/ECTC.2008.4549996","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4549996","url":null,"abstract":"A series of electromigration (EM) experiments were undertaken to evaluate the time to failure performance of solder joints comprised of Sn-Ag and Sn-Cu alloys in combination with three solderable surface finishes, Cu, Ni-Au and Ni-Cu. The opposing pad structure in the solder joints was the same in all experiments and was comprised of a layered structure, simulating Ni based under - bump - metallurgies (UBM) for controlled collapse chip connection (C4). As anticipated the Sn grain size was large with the typical solder joint containing only a few grains. In all experiments, reported here, the electron current exited the pad with the surface finish under evaluation and passed into the solder. Two failure modes were identified. The manifested failure mode depended on the orientation of the c-axis of the larger Sn grains in the solder joint with respect to the applied current direction. When the c-axis is not closely aligned with the current direction, cavitation at solder-IMC interface leads to electrical failure. A more rapid failure mode occurred when the c-axis was closely aligned with the current direction. With this alignment the interfacial IMC structures were swept away by rapid diffusive processes from the pad surface and the pad material was quickly consumed. Interfacial void formation leads to rapid failure in this mode. The Sn-Ag solder appeared to demonstrate greater microstructural stability. But, clearly the best EM performance was seen with the addition of significant levels of Cu to the Sn-Ag alloy. This alloy modification showed the best EM lifetime in combination with a Ni pad structure.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128345705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550133
R. Frye, Kai Liu, Haijing Cao, Phoo Hlaing, M. P. Chelvam
3D packaging is extensively used in digital applications, and is under consideration for analog RF applications as well. A key problem, however, is the coupling of strong output signals from front-end passive devices into the local oscillator of a transceiver chip. The main mechanism for this is mutual inductive coupling. In this study, a test structure has been designed, built and measured to examine the problem of mutual inductive coupling in stacked-die assemblies. Simulated results show good agreement with measurement, and can be used to predict the coupling. Additional simulation results are used to devise rough placement guidelines for the assembly to avoid excessive coupling. Surprisingly, even for modest amounts of lateral offset between coils on a stacked passive die and the tank coil of the underlying local oscillator, acceptably low levels of coupling can usually be obtained.
{"title":"Investigation of mutual inductive coupling in RF stacked-die assemblies","authors":"R. Frye, Kai Liu, Haijing Cao, Phoo Hlaing, M. P. Chelvam","doi":"10.1109/ECTC.2008.4550133","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550133","url":null,"abstract":"3D packaging is extensively used in digital applications, and is under consideration for analog RF applications as well. A key problem, however, is the coupling of strong output signals from front-end passive devices into the local oscillator of a transceiver chip. The main mechanism for this is mutual inductive coupling. In this study, a test structure has been designed, built and measured to examine the problem of mutual inductive coupling in stacked-die assemblies. Simulated results show good agreement with measurement, and can be used to predict the coupling. Additional simulation results are used to devise rough placement guidelines for the assembly to avoid excessive coupling. Surprisingly, even for modest amounts of lateral offset between coils on a stacked passive die and the tank coil of the underlying local oscillator, acceptably low levels of coupling can usually be obtained.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128646914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550038
T. Mattila, L. Suotula, J. Kivilahti
Due to the more extensive testing of new portable products the employment of efficient testing methods has become ever more important. The replacement of the commonly employed JESD22-B111 drop test with the vibration test has been investigated owing to the inconveniences related to the drop testing. The emphasis of the study has been placed on how the results of the vibration tests correlate with those of the drop tests at different temperatures. Comparison of the test methods was carried out by implementing the same experimental design with both testers and by using the observed failure modes and the number of load-cycles-to-failure as the evaluation criteria. The component boards used in this work were composed of the 12 mm x 12 mm Ball Grid Array (144 bumps, the pitch of 0.8 mm, and the bump size of 0.5 mm) and the printed wiring board (PWB), which was designed according to the JESD22-B111 standard. The experimental design consisted of three variables: i) composition of solder interconnections (Sn3.1Ag0.5Cu or Snl.lAg0.5Cu0.lNi), ii) PWB protective coating (Cu|OSP ja Ni(P)|Au), and iii) temperature of the component (23degC , 70degC, or 110degC). The failure modes observed in the component boards vibration-tested at the different temperatures were the same as those observed in the drop tests. However, copper trace failures were more common in the vibration-tested boards as compared to the drop-tested boards. In both the tests the performances of the component boards with different interconnection compositions and PWB coatings were very similar at the different temperatures. However, the relative decrease of the number of load-cycles- to-failure with increased temperature was larger in the vibration tests.
由于新型便携式产品的测试越来越广泛，采用高效的测试方法变得越来越重要。由于跌落测试带来的不便，人们研究了用振动测试代替常用的JESD22-B111跌落测试。研究的重点是在不同温度下振动试验的结果与跌落试验的结果之间的关系。采用相同的试验设计，以观察到的破坏模式和荷载循环次数作为评价标准，对两种试验方法进行了比较。本工作中使用的元件板由12mm × 12mm球栅阵列(144个凸点，凸点间距为0.8 mm，凸点尺寸为0.5 mm)和印刷配线板(PWB)组成，按照JESD22-B111标准设计。实验设计包括三个变量:i)焊料互连的组成(Sn3.1Ag0.5Cu或Snl.lAg0.5Cu0.lNi)， ii) PWB保护涂层(Cu|OSP ja Ni(P)|Au)， iii)组件的温度(23℃，70℃或110℃)。在不同温度下的构件板振动试验中观察到的失效模式与跌落试验中观察到的失效模式相同。然而，与跌落测试板相比，在振动测试板中铜痕量故障更为常见。在这两种测试中，不同互连成分的组件板和PWB涂层在不同温度下的性能非常相似。然而，在振动试验中，随着温度的升高，载荷循环次数相对减少的幅度更大。
{"title":"Replacement of the drop test with the vibration test — The effect of test temperature on reliability","authors":"T. Mattila, L. Suotula, J. Kivilahti","doi":"10.1109/ECTC.2008.4550038","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550038","url":null,"abstract":"Due to the more extensive testing of new portable products the employment of efficient testing methods has become ever more important. The replacement of the commonly employed JESD22-B111 drop test with the vibration test has been investigated owing to the inconveniences related to the drop testing. The emphasis of the study has been placed on how the results of the vibration tests correlate with those of the drop tests at different temperatures. Comparison of the test methods was carried out by implementing the same experimental design with both testers and by using the observed failure modes and the number of load-cycles-to-failure as the evaluation criteria. The component boards used in this work were composed of the 12 mm x 12 mm Ball Grid Array (144 bumps, the pitch of 0.8 mm, and the bump size of 0.5 mm) and the printed wiring board (PWB), which was designed according to the JESD22-B111 standard. The experimental design consisted of three variables: i) composition of solder interconnections (Sn3.1Ag0.5Cu or Snl.lAg0.5Cu0.lNi), ii) PWB protective coating (Cu|OSP ja Ni(P)|Au), and iii) temperature of the component (23degC , 70degC, or 110degC). The failure modes observed in the component boards vibration-tested at the different temperatures were the same as those observed in the drop tests. However, copper trace failures were more common in the vibration-tested boards as compared to the drop-tested boards. In both the tests the performances of the component boards with different interconnection compositions and PWB coatings were very similar at the different temperatures. However, the relative decrease of the number of load-cycles- to-failure with increased temperature was larger in the vibration tests.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127048122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550251
Q. Liang, K. Moon, Yuelan Zhang, C. Wong
SiC particles and epoxy resin were applied to prepare a potential high thermal conductivity underfill material. SiC particles are thermally coated with a nano layer silica by oxidation at high temperature. Then silane was used as the surface treatment of the silica coated SiC particles to improve the interaction between filler and polymer matrix. TEM and TGA measurements were used to characterize the treated SiC particles. Mechanical properties of the epoxy composite with the treated SiC filler were measured by DMA, TMA and die shear adhesion test. This study also focused on optimizing the thermal conductivity of the polymer composites by filler surface pretreatment to increase interfacial bonding and decrease the thermal resistance.
{"title":"Low stress and high thermal conductive underfill for cu/low-k application","authors":"Q. Liang, K. Moon, Yuelan Zhang, C. Wong","doi":"10.1109/ECTC.2008.4550251","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550251","url":null,"abstract":"SiC particles and epoxy resin were applied to prepare a potential high thermal conductivity underfill material. SiC particles are thermally coated with a nano layer silica by oxidation at high temperature. Then silane was used as the surface treatment of the silica coated SiC particles to improve the interaction between filler and polymer matrix. TEM and TGA measurements were used to characterize the treated SiC particles. Mechanical properties of the epoxy composite with the treated SiC filler were measured by DMA, TMA and die shear adhesion test. This study also focused on optimizing the thermal conductivity of the polymer composites by filler surface pretreatment to increase interfacial bonding and decrease the thermal resistance.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129916190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550037
T. Chai, D.Q. Yu, J. Lau, W.H. Zhu, X.R. Zhang
A high speed shear test of solder ball at different shear angles has been developed and investigated for SnAgCu solder balls. The objective of the test is to introduce vertical loading component in the high speed shear test and to study intermetallic response of different solder balls. The shear test is performed at three angles of attack e. g. 3, 5 and 10 degree. The basic shear tester allow high speed shear tool movement of up to 4000 mm per second, and capture the load-displacement curve experienced by the shear tool. Using this setup, high-speed shear characterization has been carried out on microBGA sample with Sn3Ag0.5Cu and Sn1Ag0.5Cu solder on Ni/Au pad finish. In this paper, the effect of angle shear at high speed on these SnAgCu BGA balls is presented, with the details of load-displacement response and failure mode for these solder balls. Generally all the samples show changes in ductile-to-brittle failure as shear speed increases. The angled shear test lead to down shift of ductile-brittle transition to occur at lower shear speed with larger shear angle. It is found to improve sensitivity in revealing brittle failure for solder ball characterization.
{"title":"Angled high strain rate shear testing for SnAgCu solder balls","authors":"T. Chai, D.Q. Yu, J. Lau, W.H. Zhu, X.R. Zhang","doi":"10.1109/ECTC.2008.4550037","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550037","url":null,"abstract":"A high speed shear test of solder ball at different shear angles has been developed and investigated for SnAgCu solder balls. The objective of the test is to introduce vertical loading component in the high speed shear test and to study intermetallic response of different solder balls. The shear test is performed at three angles of attack e. g. 3, 5 and 10 degree. The basic shear tester allow high speed shear tool movement of up to 4000 mm per second, and capture the load-displacement curve experienced by the shear tool. Using this setup, high-speed shear characterization has been carried out on microBGA sample with Sn3Ag0.5Cu and Sn1Ag0.5Cu solder on Ni/Au pad finish. In this paper, the effect of angle shear at high speed on these SnAgCu BGA balls is presented, with the details of load-displacement response and failure mode for these solder balls. Generally all the samples show changes in ductile-to-brittle failure as shear speed increases. The angled shear test lead to down shift of ductile-brittle transition to occur at lower shear speed with larger shear angle. It is found to improve sensitivity in revealing brittle failure for solder ball characterization.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125683396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550208
W. Lee, S. Hwang, J. Lim, B. Rho
We fabricated straight multimode optical waveguide films to analyze quantitatively the effectiveness of the helical bending. The optical waveguide films were very flexible and the refractive index difference between the core and the clad was 1.53% at a wavelength of 0.85 mum. This paper focuses on the helical bending losses under a proper index difference. Therefore, we measured first the bending losses with various bending radiuses and then the helical bending losses with various inclined angles and the radiuses, sequentially. As a result, we could improve the bending loss by 4 dB at 60deg- inclined angle and 1 mm radius, compared to a normal bending structure. In addition, we fabricated a flexible optical interconnection module linked with the flexible optical waveguide to investigate how the helical bending has an effect on data transmission. The optical interconnection module was composed of vertical cavity surface emitting laser, photodiode, and a 45deg-ended waveguide. The helical bending was applied to the waveguide of the optical interconnection module and data transmission characteristics with the inclined angles were measured.
{"title":"Helically bent structure of straight optical waveguide for flexible optical interconnection","authors":"W. Lee, S. Hwang, J. Lim, B. Rho","doi":"10.1109/ECTC.2008.4550208","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550208","url":null,"abstract":"We fabricated straight multimode optical waveguide films to analyze quantitatively the effectiveness of the helical bending. The optical waveguide films were very flexible and the refractive index difference between the core and the clad was 1.53% at a wavelength of 0.85 mum. This paper focuses on the helical bending losses under a proper index difference. Therefore, we measured first the bending losses with various bending radiuses and then the helical bending losses with various inclined angles and the radiuses, sequentially. As a result, we could improve the bending loss by 4 dB at 60deg- inclined angle and 1 mm radius, compared to a normal bending structure. In addition, we fabricated a flexible optical interconnection module linked with the flexible optical waveguide to investigate how the helical bending has an effect on data transmission. The optical interconnection module was composed of vertical cavity surface emitting laser, photodiode, and a 45deg-ended waveguide. The helical bending was applied to the waveguide of the optical interconnection module and data transmission characteristics with the inclined angles were measured.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126966492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550214
M. Heimann, M. Wirts-Ruetters, B. Boehme, K. Wolter
The part of electronics packaging is steadily forced to adapt the requirements of the microelectronic industry. For future electronics application such needs will be: 1) steady miniaturisation of the electronic devices 2) high pin count up to 5000 i / o per device 3) pitches down to 20 mum 4) higher current density per devices 5) higher thermal dissipation loss This is only a small extract of the challenges facing the electronics packaging industry in the future. The aim and duty for electronics packaging is to realize a reliable package for future electronics. Commonplace materials for joining elements like solder are not able to solve these requirements. For example in [1] the authors describe that future IC's operating at high frequencies of 10-28 GHz, signal bandwidths of 20 Gbps and lower supply voltages require an estimated maximum of R (< 10 mOhm), L (<5-10pH) and C (<5-10 fF).[l] Current joining elements can not meet these requirements. To solve these problems the electronics packaging industry researches technologies and materials of the nanotechnology. Especially researches concerning new materials for electronics packaging rise up since the last three years. One of the most researched new materials are Carbon Nanotubes (CNT). Carbon Nanotubes have superior mechanical, electrical and thermal properties. Due to these properties CNT are considered as promising candidates in packaging technology. The most interesting field of application is the use of the Carbon Nanotubes as filler in electrical conductive adhesives. The aim is to improve the performance of conductive adhesives in comparison to common products. This study deals with characterization of carbon nanotube / epoxy adhesives in electronics packaging. For this study we optimize the CNT - adhesive system by modification of the CNT, use of different dispersion technologies and under variation of the epoxy matrix. The resulting adhesives are characterized by measuring their viscosity, mechanical strength and their thermal and electrical conductivity. For all studies Multi Wall Nanotubes were used which can be purchased at a reasonable price. For modification of the CNT they can be treated by low pressure plasma (cvd), UV / ozone treatment or modifiedchemically in solution to achieve a higher polarity resulting in a better dispersibility. Also bonding to the polymer matrix is improved. Success of the processes is studied by XPS and REM. For dispersion technology ultrasonic bath, speed mixing and/or treatment with a roll calander can be used. The polymer matrix is also varied in order to achieve an appropriate viscosity at the CNT-content of interest that enables good results in screen printing. Also CNT-polymer interaction can be adapted by varying polarity of the resin used. The distribution of CNT in the matrix is studied by TEM. The first investigations show that ultrasonic finger is the favourable dispersion technology to achieve well dispersed CNT. For modification of the CNT th
电子封装部分不断被迫适应微电子工业的要求。对于未来的电子应用，这些需求将是:1)电子器件的稳定小型化2)每个器件高达5000 i / o的高引脚数3)节距降至20mum 4)每个器件更高的电流密度5)更高的散热损耗这只是电子封装行业未来面临的挑战的一小部分。电子封装的目标和职责是为未来的电子产品实现可靠的封装。用于连接元件的普通材料如焊料无法满足这些要求。例如，在b[1]中，作者描述了未来的IC在10-28 GHz的高频，20 Gbps的信号带宽和更低的电源电压下工作，估计最大需要R (< 10 mOhm)， L (<5-10pH)和C (<5-10 fF)。[1]目前的连接元件不能满足这些要求。为了解决这些问题，电子封装行业开始研究纳米技术和材料。特别是近三年来，对电子封装新材料的研究迅速兴起。碳纳米管(CNT)是目前研究最多的新材料之一。碳纳米管具有优异的机械、电学和热性能。由于这些特性，碳纳米管被认为是包装技术中有前途的候选人。最有趣的应用领域是将碳纳米管用作导电胶粘剂的填料。目的是提高导电胶粘剂与普通产品相比的性能。本文研究了电子封装中碳纳米管/环氧胶粘剂的特性。本研究通过对碳纳米管进行改性、采用不同的分散技术和改变环氧树脂基体来优化碳纳米管-胶粘剂体系。所得到的粘合剂通过测量其粘度，机械强度和导热性和导电性来表征。所有的研究都使用了价格合理的多壁纳米管。对于碳纳米管的改性，它们可以通过低压等离子体(cvd)，紫外线/臭氧处理或在溶液中进行化学改性来获得更高的极性，从而获得更好的分散性。与聚合物基体的结合也得到了改善。通过XPS和REM研究了工艺的成功。对于分散技术，可以使用超声波浴、快速混合和/或辊压机处理。聚合物基体也会发生变化，以便在碳纳米管含量下达到适当的粘度，从而在丝网印刷中获得良好的效果。此外，碳纳米管-聚合物的相互作用可以通过改变所使用的树脂的极性来适应。用透射电镜研究了碳纳米管在基体中的分布。初步研究表明，超声指状分散技术是实现碳纳米管良好分散的有利技术。对于碳纳米管的改性，等离子体处理是有效的，给予适量的羟基。
{"title":"Investigations of carbon nanotubes epoxy composites for electronics packaging","authors":"M. Heimann, M. Wirts-Ruetters, B. Boehme, K. Wolter","doi":"10.1109/ECTC.2008.4550214","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550214","url":null,"abstract":"The part of electronics packaging is steadily forced to adapt the requirements of the microelectronic industry. For future electronics application such needs will be: 1) steady miniaturisation of the electronic devices 2) high pin count up to 5000 i / o per device 3) pitches down to 20 mum 4) higher current density per devices 5) higher thermal dissipation loss This is only a small extract of the challenges facing the electronics packaging industry in the future. The aim and duty for electronics packaging is to realize a reliable package for future electronics. Commonplace materials for joining elements like solder are not able to solve these requirements. For example in [1] the authors describe that future IC's operating at high frequencies of 10-28 GHz, signal bandwidths of 20 Gbps and lower supply voltages require an estimated maximum of R (< 10 mOhm), L (<5-10pH) and C (<5-10 fF).[l] Current joining elements can not meet these requirements. To solve these problems the electronics packaging industry researches technologies and materials of the nanotechnology. Especially researches concerning new materials for electronics packaging rise up since the last three years. One of the most researched new materials are Carbon Nanotubes (CNT). Carbon Nanotubes have superior mechanical, electrical and thermal properties. Due to these properties CNT are considered as promising candidates in packaging technology. The most interesting field of application is the use of the Carbon Nanotubes as filler in electrical conductive adhesives. The aim is to improve the performance of conductive adhesives in comparison to common products. This study deals with characterization of carbon nanotube / epoxy adhesives in electronics packaging. For this study we optimize the CNT - adhesive system by modification of the CNT, use of different dispersion technologies and under variation of the epoxy matrix. The resulting adhesives are characterized by measuring their viscosity, mechanical strength and their thermal and electrical conductivity. For all studies Multi Wall Nanotubes were used which can be purchased at a reasonable price. For modification of the CNT they can be treated by low pressure plasma (cvd), UV / ozone treatment or modifiedchemically in solution to achieve a higher polarity resulting in a better dispersibility. Also bonding to the polymer matrix is improved. Success of the processes is studied by XPS and REM. For dispersion technology ultrasonic bath, speed mixing and/or treatment with a roll calander can be used. The polymer matrix is also varied in order to achieve an appropriate viscosity at the CNT-content of interest that enables good results in screen printing. Also CNT-polymer interaction can be adapted by varying polarity of the resin used. The distribution of CNT in the matrix is studied by TEM. The first investigations show that ultrasonic finger is the favourable dispersion technology to achieve well dispersed CNT. For modification of the CNT th","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132864920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550106
Xuejun Fan, Jiang Zhou, A. Chandra
There are three types of failures when an electronic package is exposed to a humidity environment: the popcorn failure at soldering reflow, the delamination and cracking at HAST without electrical bias, and the corrosion under biased HAST. Despite the difference in failure mechanisms, the common and most contributory factor to moisture induced failures is the degradation of adhesion strength in the presence of moisture. Therefore, understanding interface behavior with moisture becomes a key for package integrity and reliability analysis. In this paper, first, several methods to characterize the interfacial fracture toughness or adhesion strength at elevated temperature with moisture effect are presented. The interfaces between polyimide on silicon chip and underfill (PI/UF) are used as a carrier to investigate the influence of moisture. Both interface fracture mechanics based fracture toughness measurement techniques and the quick-turn method such as die shear test are applied to investigate the interface behaviors with moisture. Details of several sample preparation methods, by which the fracture can be made to stay along the desired interface, are illustrated. Key results on the influence of the moisture on fracture toughness are presented. Next, the hygroscopic swelling characterization techniques are reviewed. Due to the fact that the moisture diffusion is a slow process, specimens used in hygroscopic swelling measurement are often subjected to a non-uniform moisture distribution. This becomes a potential hidden error in obtaining the coefficient of hygroscopic swelling. Analytical solutions have been devised to predict the errors caused by the non-uniform moisture distribution. A simple procedure in obtaining the accurate swelling characteristics is proposed. Both TGA-TMA method and Moire interferometry method are applied to measure the hygroscopic swelling behaviors of several underfills. A very good agreement between these two methods is achieved. Subsequent to hygroscopic swelling characterization, the paper presents a novel method to allow a time-dependent nonlinear finite element analysis for package deformations and stresses induced by hygroscopic as well as thermal mismatches. This has been a challenging problem since commonly used commercial finite element software such as ABAQUS and ANSYS do not explicitly allow the fully coupled nonlinear thermal and hygroscopic stress analysis. The existing linear superposition method, which couples hygroscopic stress with thermal stress analysis, can not apply to the problem with nonlinear materials such as polymers and solder materials. A fully integrated finite element stress modeling methodology is demonstrated through an example of flip chip package subjected to a multi-step humidity/temperature loading profile. The results of the effect of hygroscopic swelling on the inter-layer dielectric (ILD) and under bump metallurgy (UBM) structures reveals that the overall ILD stresses under HAST can b
{"title":"Package structural integrity analysis considering moisture","authors":"Xuejun Fan, Jiang Zhou, A. Chandra","doi":"10.1109/ECTC.2008.4550106","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550106","url":null,"abstract":"There are three types of failures when an electronic package is exposed to a humidity environment: the popcorn failure at soldering reflow, the delamination and cracking at HAST without electrical bias, and the corrosion under biased HAST. Despite the difference in failure mechanisms, the common and most contributory factor to moisture induced failures is the degradation of adhesion strength in the presence of moisture. Therefore, understanding interface behavior with moisture becomes a key for package integrity and reliability analysis. In this paper, first, several methods to characterize the interfacial fracture toughness or adhesion strength at elevated temperature with moisture effect are presented. The interfaces between polyimide on silicon chip and underfill (PI/UF) are used as a carrier to investigate the influence of moisture. Both interface fracture mechanics based fracture toughness measurement techniques and the quick-turn method such as die shear test are applied to investigate the interface behaviors with moisture. Details of several sample preparation methods, by which the fracture can be made to stay along the desired interface, are illustrated. Key results on the influence of the moisture on fracture toughness are presented. Next, the hygroscopic swelling characterization techniques are reviewed. Due to the fact that the moisture diffusion is a slow process, specimens used in hygroscopic swelling measurement are often subjected to a non-uniform moisture distribution. This becomes a potential hidden error in obtaining the coefficient of hygroscopic swelling. Analytical solutions have been devised to predict the errors caused by the non-uniform moisture distribution. A simple procedure in obtaining the accurate swelling characteristics is proposed. Both TGA-TMA method and Moire interferometry method are applied to measure the hygroscopic swelling behaviors of several underfills. A very good agreement between these two methods is achieved. Subsequent to hygroscopic swelling characterization, the paper presents a novel method to allow a time-dependent nonlinear finite element analysis for package deformations and stresses induced by hygroscopic as well as thermal mismatches. This has been a challenging problem since commonly used commercial finite element software such as ABAQUS and ANSYS do not explicitly allow the fully coupled nonlinear thermal and hygroscopic stress analysis. The existing linear superposition method, which couples hygroscopic stress with thermal stress analysis, can not apply to the problem with nonlinear materials such as polymers and solder materials. A fully integrated finite element stress modeling methodology is demonstrated through an example of flip chip package subjected to a multi-step humidity/temperature loading profile. The results of the effect of hygroscopic swelling on the inter-layer dielectric (ILD) and under bump metallurgy (UBM) structures reveals that the overall ILD stresses under HAST can b","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128877327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550220
I. Papakonstantinou, David R. Selviah, Kai Wang, R. Pitwon, K. Hopkins, D. Milward
The paper introduces a low cost, precision alignment technique designed to be unaffected by temperature or process variations in the thickness of the PCB FR4 board, the thickness of the lower cladding between the PCB board and the waveguide core, the thickness of the upper cladding above the waveguide core, the relative lateral position of waveguides across the PCB, and the axial position of the cut entrance and exit faces of the waveguide.
{"title":"Optical 8-channel, 10 Gb/s MT pluggable connector alignment technology for precision coupling of laser and photodiode arrays to polymer waveguide arrays for optical board-to-board interconnects","authors":"I. Papakonstantinou, David R. Selviah, Kai Wang, R. Pitwon, K. Hopkins, D. Milward","doi":"10.1109/ECTC.2008.4550220","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550220","url":null,"abstract":"The paper introduces a low cost, precision alignment technique designed to be unaffected by temperature or process variations in the thickness of the PCB FR4 board, the thickness of the lower cladding between the PCB board and the waveguide core, the thickness of the upper cladding above the waveguide core, the relative lateral position of waveguides across the PCB, and the axial position of the cut entrance and exit faces of the waveguide.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125320314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550262
J. Lee, M. Mayer, Y. Zhou, S. Hong, J. Moon
The tail breaking process is studied by investigating tail bond imprint micrographs. The imprints were made on Ag metallization (diepad) with Cu wire (Cu-Ag) and with Au wire (Au-Ag). In the Au-Ag case, Au wire residue was found on the diepad indicating fracture occurred in the Au wire. In the Cu-Ag case, no Cu residue was found on the imprint, but material fracture of the substrate metallization. A more detailed investigation of the Cu wire tail end clearly shows the Ag pick-up. The FAB formation from tails with and without pick-up is studied with various electrical flame off (EFO) parameters and electrode to wire distances (EWDs). Hardness of FAB cross-sections is a microhardness tester. The hardness change of the FAB is important for stress developed on the bond pad during ball bonding process. The EWD parameter is found to be the main parameter to obtain spherical and oxide free FABs. As the EWD increases above 0.3 mm, oxide lines containing 1.09+/-0.47 wt%Ag are found on the FAB surface. The oxide lines further contain roughly 3 wt% of O2 and 96 wt% of Cu. Etching the sample showed that the oxide lines locations agree with those of the boundaries of the FAB grains, leading to the conclusion that the Ag pick-up material is concentrated on the grain boundaries inside the FAB. The results show that the FAB diameter is not significantly changed by the Ag pick-up. The FAB hardness is reduced by about 3%.
{"title":"Silver pick-up during tail formation and its effect on free air ball in thermosonic copper ball bonding","authors":"J. Lee, M. Mayer, Y. Zhou, S. Hong, J. Moon","doi":"10.1109/ECTC.2008.4550262","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550262","url":null,"abstract":"The tail breaking process is studied by investigating tail bond imprint micrographs. The imprints were made on Ag metallization (diepad) with Cu wire (Cu-Ag) and with Au wire (Au-Ag). In the Au-Ag case, Au wire residue was found on the diepad indicating fracture occurred in the Au wire. In the Cu-Ag case, no Cu residue was found on the imprint, but material fracture of the substrate metallization. A more detailed investigation of the Cu wire tail end clearly shows the Ag pick-up. The FAB formation from tails with and without pick-up is studied with various electrical flame off (EFO) parameters and electrode to wire distances (EWDs). Hardness of FAB cross-sections is a microhardness tester. The hardness change of the FAB is important for stress developed on the bond pad during ball bonding process. The EWD parameter is found to be the main parameter to obtain spherical and oxide free FABs. As the EWD increases above 0.3 mm, oxide lines containing 1.09+/-0.47 wt%Ag are found on the FAB surface. The oxide lines further contain roughly 3 wt% of O2 and 96 wt% of Cu. Etching the sample showed that the oxide lines locations agree with those of the boundaries of the FAB grains, leading to the conclusion that the Ag pick-up material is concentrated on the grain boundaries inside the FAB. The results show that the FAB diameter is not significantly changed by the Ag pick-up. The FAB hardness is reduced by about 3%.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126895957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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