Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550219
M. Mayer
A real-time in situ ball bond stress signal is recorded without destructing the sample, using a piezoresistive integrated CMOS microsensor located next to a test pad on a testchip. The sensor is sensitive to in-plane shear stress tauxy that arises due to changes of the principal stress components at the test pad. Without the ball bond, the signal remains almost unchanged during 400 h high temperature storage (HTS) at 200degC. With a ball bond at the contact zone, significant stress changes are observed during HTS. For comparison, the contact resistance of the bond was measured with a four-wire method. Two connection paths lead to the test pad, and a second wire was bonded on top of the test ball bond. Constant current was introduced via the first ball bond and the first pad contact, and the voltage drop was sensed using the second ball bond and the second pad contact. The contact resistance values measured at room temperature (25degC) before and after HTS are 2.1 mOmega to 6.1 mOmega, respectively. Effects influencing the microsensor signal during HTS include the temperature coefficient of the signal offset and bond degradation by the growth of intermetallics and cracks. The first effect is accounted for by using the signal from reference pads without ball bond. An increasing stress signal means an increase in tensile stress as caused by the formation of IMCs expanding in volume compared to the base material. The initial two phases of tensile stress growth observed might correspond to IMC growth without the presence of interfacial cracks, resulting in a volume shrinkage. The subsequent phase of signal drop indicates the presence of different mechanisms partly reducing the tensile stress built up before.
{"title":"Non-destructive monitoring of Au ball bond stress during high-temperature aging","authors":"M. Mayer","doi":"10.1109/ECTC.2008.4550219","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550219","url":null,"abstract":"A real-time in situ ball bond stress signal is recorded without destructing the sample, using a piezoresistive integrated CMOS microsensor located next to a test pad on a testchip. The sensor is sensitive to in-plane shear stress tauxy that arises due to changes of the principal stress components at the test pad. Without the ball bond, the signal remains almost unchanged during 400 h high temperature storage (HTS) at 200degC. With a ball bond at the contact zone, significant stress changes are observed during HTS. For comparison, the contact resistance of the bond was measured with a four-wire method. Two connection paths lead to the test pad, and a second wire was bonded on top of the test ball bond. Constant current was introduced via the first ball bond and the first pad contact, and the voltage drop was sensed using the second ball bond and the second pad contact. The contact resistance values measured at room temperature (25degC) before and after HTS are 2.1 mOmega to 6.1 mOmega, respectively. Effects influencing the microsensor signal during HTS include the temperature coefficient of the signal offset and bond degradation by the growth of intermetallics and cracks. The first effect is accounted for by using the signal from reference pads without ball bond. An increasing stress signal means an increase in tensile stress as caused by the formation of IMCs expanding in volume compared to the base material. The initial two phases of tensile stress growth observed might correspond to IMC growth without the presence of interfacial cracks, resulting in a volume shrinkage. The subsequent phase of signal drop indicates the presence of different mechanisms partly reducing the tensile stress built up before.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124122230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4549976
F. Doany, C. Schow, C. Tsang, N. Ruiz, R. Horton, D. Kuchta, C. Patel, J. Knickerbocker, J. Kash
A parallel optical transceiver module with 24-transmitter plus 24-receiver channels has been designed and fabricated. The transceiver Optochip relies on silicon carrier technology to provide a high level of integration of the electrical and optical components onto a single substrate with high density interconnection. The transceiver Optochip consists of the Si carrier platform with 4 flip-chip attached components: two 24-channel 850 nm optoelectronic arrays (VCSELs and photodiodes) and two 24-channel CMOS ICs (receivers and laser drivers). Furthermore, 150-mum diameter "optical vias" are incorporated in the Si carrier at 48 locations of the VCSEL and PD array element in order to allow optical transmission through the silicon carrier. A lens arrays aligned to the optical vias can also be integrated into the Si carrier to collimate the optical inputs/outputs and facilitate optical coupling to/from the Optochip. Complete Optochips have been assembled and fully characterized using optical coupling into multimode fiber (MMF) with all channels fully operational. The 24 transmitter channels showed good performance up to 15 Gb/s with uniform, high optical output power and low jitter. The 24 receiver channels, characterized as full Tx-to-Rx Optochip links, operated error-free up to 12.5 Gb/s. At 12.5 Gb/s, each complete link consumes only 11 mW/Gb/s. The Optochip achieves a 300 Gb/s bidirectional data rate, a new record for parallel optical transceivers.
{"title":"300-Gb/s 24-channel bidirectional Si carrier transceiver Optochip for board-level interconnects","authors":"F. Doany, C. Schow, C. Tsang, N. Ruiz, R. Horton, D. Kuchta, C. Patel, J. Knickerbocker, J. Kash","doi":"10.1109/ECTC.2008.4549976","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4549976","url":null,"abstract":"A parallel optical transceiver module with 24-transmitter plus 24-receiver channels has been designed and fabricated. The transceiver Optochip relies on silicon carrier technology to provide a high level of integration of the electrical and optical components onto a single substrate with high density interconnection. The transceiver Optochip consists of the Si carrier platform with 4 flip-chip attached components: two 24-channel 850 nm optoelectronic arrays (VCSELs and photodiodes) and two 24-channel CMOS ICs (receivers and laser drivers). Furthermore, 150-mum diameter \"optical vias\" are incorporated in the Si carrier at 48 locations of the VCSEL and PD array element in order to allow optical transmission through the silicon carrier. A lens arrays aligned to the optical vias can also be integrated into the Si carrier to collimate the optical inputs/outputs and facilitate optical coupling to/from the Optochip. Complete Optochips have been assembled and fully characterized using optical coupling into multimode fiber (MMF) with all channels fully operational. The 24 transmitter channels showed good performance up to 15 Gb/s with uniform, high optical output power and low jitter. The 24 receiver channels, characterized as full Tx-to-Rx Optochip links, operated error-free up to 12.5 Gb/s. At 12.5 Gb/s, each complete link consumes only 11 mW/Gb/s. The Optochip achieves a 300 Gb/s bidirectional data rate, a new record for parallel optical transceivers.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127783401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550107
Yumin Liu, Y. Liu, S. Irving, T. Luk
Integrated passive technologies have obtained more and more attention due to the increasing demand for functional integration for cost, performance and size reasons. Integration of passive components such as capacitors into semiconductor devices drives a higher degree of system-level integration. Currently, integrated capacitors are fabricated by using metal-insulator-metal (MIM) structure. In the MIM capacitor fabrication process, the dielectrics, electrodes and final protection layer are deposited on the substrate, layer by layer, at different temperatures. This may generate thermal stress because of the deposition temperature changes. If the thermal stress is very high, as it may be for certain device layouts, it may even cause cracks in the dielectric layer due to the CTE mismatch of different layers. Therefore, in this paper, the MIM capacitor fabrication process is simulated to obtain the thermal stress in different layers and at different process stages. The effect of the parameters of a typical MIM structure is studied. Especially the impact of guard ring thickness, space or overlap of a polyimide layer and guard ring to bottom metal, space or overlap of between metal layers are thoroughly investigated. A total of 15 DoEs in reasonable parameter ranges are designed and conducted for the thermal stress simulation.
{"title":"Thermal stress simulation in the metal-insulator-metal (MIM) wafer fabrication process","authors":"Yumin Liu, Y. Liu, S. Irving, T. Luk","doi":"10.1109/ECTC.2008.4550107","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550107","url":null,"abstract":"Integrated passive technologies have obtained more and more attention due to the increasing demand for functional integration for cost, performance and size reasons. Integration of passive components such as capacitors into semiconductor devices drives a higher degree of system-level integration. Currently, integrated capacitors are fabricated by using metal-insulator-metal (MIM) structure. In the MIM capacitor fabrication process, the dielectrics, electrodes and final protection layer are deposited on the substrate, layer by layer, at different temperatures. This may generate thermal stress because of the deposition temperature changes. If the thermal stress is very high, as it may be for certain device layouts, it may even cause cracks in the dielectric layer due to the CTE mismatch of different layers. Therefore, in this paper, the MIM capacitor fabrication process is simulated to obtain the thermal stress in different layers and at different process stages. The effect of the parameters of a typical MIM structure is studied. Especially the impact of guard ring thickness, space or overlap of a polyimide layer and guard ring to bottom metal, space or overlap of between metal layers are thoroughly investigated. A total of 15 DoEs in reasonable parameter ranges are designed and conducted for the thermal stress simulation.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126326871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550207
J. Caers, X.J. Zhao, J. D. de Vries, E. Wong, G. Kums, A.R.C. Engelfriet
The Highly Accelerated Robustness Test, HART, is an approach that allows the assessment or the robustness of adhesive interconnects at a throughput rate that is 10 times faster than the conventional accelerated humidity test, without going to higher stress levels. The test is based on the physics of a conductive adhesive interconnect. In stead of using the contact resistance drift over time in a static temperature- humidity environment, HART uses the effect of a changing temperature or humidity environment on the contact resistance as a characteristic of the robustness of the interconnect. HART using moisture as stressor is by far the most powerful approach of the two. Both the response and hysteresis in a cyclic humidity environment are proposed as new criteria for the interconnect robustness. Flip chip on flex interconnections with conductive and non-conductive adhesives are used as a carrier. Different contact material combinations and different adhesives are used in this study.
{"title":"HART: A new highly accelerated robustness test for conductive adhesive interconnects","authors":"J. Caers, X.J. Zhao, J. D. de Vries, E. Wong, G. Kums, A.R.C. Engelfriet","doi":"10.1109/ECTC.2008.4550207","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550207","url":null,"abstract":"The Highly Accelerated Robustness Test, HART, is an approach that allows the assessment or the robustness of adhesive interconnects at a throughput rate that is 10 times faster than the conventional accelerated humidity test, without going to higher stress levels. The test is based on the physics of a conductive adhesive interconnect. In stead of using the contact resistance drift over time in a static temperature- humidity environment, HART uses the effect of a changing temperature or humidity environment on the contact resistance as a characteristic of the robustness of the interconnect. HART using moisture as stressor is by far the most powerful approach of the two. Both the response and hysteresis in a cyclic humidity environment are proposed as new criteria for the interconnect robustness. Flip chip on flex interconnections with conductive and non-conductive adhesives are used as a carrier. Different contact material combinations and different adhesives are used in this study.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126374883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550135
P. Limaye, X. Rottenberg, R. D'Ippolito, S. Donders, W. De Raedt, I. De Wolf, E. Beyne
This paper presents a new approach to designing robust circuits implementing integrated passive devices (IPD) for radio frequency applications fabricated with thin film technology. IMEC's thin film rf-IPD technology allows defining high-accuracy and high-Q passive components, e.g. transmission lines, inductors, resistors and various types of capacitors, in a cost-effective process. This paper uses a case study based on electrical characterization data for a LC tank based filter using Ta2O5 and BCB dielectrics. The effect of the variations in the fabrication process on the performance of the filter and the resulting feedback to the manufacturing of the RF - IPDs is studied. Deterministic approaches are unable to take into account actual variability in design and manufacturing without over-dimensioning the design or assuming a too pessimistic view on the actual characteristics. The probabilistic design approach can be used to align the design with the realistic manufacturing tolerances so that the final design will be always reliable for the given processing variations.
{"title":"Probabilistic design approach for integrated passive devices in RF applications","authors":"P. Limaye, X. Rottenberg, R. D'Ippolito, S. Donders, W. De Raedt, I. De Wolf, E. Beyne","doi":"10.1109/ECTC.2008.4550135","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550135","url":null,"abstract":"This paper presents a new approach to designing robust circuits implementing integrated passive devices (IPD) for radio frequency applications fabricated with thin film technology. IMEC's thin film rf-IPD technology allows defining high-accuracy and high-Q passive components, e.g. transmission lines, inductors, resistors and various types of capacitors, in a cost-effective process. This paper uses a case study based on electrical characterization data for a LC tank based filter using Ta2O5 and BCB dielectrics. The effect of the variations in the fabrication process on the performance of the filter and the resulting feedback to the manufacturing of the RF - IPDs is studied. Deterministic approaches are unable to take into account actual variability in design and manufacturing without over-dimensioning the design or assuming a too pessimistic view on the actual characteristics. The probabilistic design approach can be used to align the design with the realistic manufacturing tolerances so that the final design will be always reliable for the given processing variations.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122206354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550162
G. Mehrotra, G. Jha, J. Goud, P. Raj, M. Venkatesan, M. Iyer, D. Hess, R. Tummala
High speed digital and mixed signal applications are driving short and more reliable fine pitch interconnection with higher I/O count in 3D architectures. Thin film die to wafer and wafer to wafer bonding with copper-based interconnections have several benefits in terms of low cost, process compatibility with semiconductor infrastructure, and the shortest interconnection with the best electrical performance. However, the bonding is accomplished at around 400 C, with pressures exceeding 30 N/cm2 which may not be compatible with thinned dies, and in ultrahigh vacuum and cleanroom environments with careful copper oxide cleaning procedures. The bonding time is typically 1 hour, which also limits the throughput. The process windows are relatively narrow with several temperature compatibility issues. This paper deals with low temperature bonding process using high surface energy metallic nanoparticles such as copper and gold. Bonding is enhanced by accelerated diffusion kinetics. Self patterning technique has also been developed to assist fine pitch bonding. This is based on selective wetting or selective deposition of nanoparticles.
{"title":"Low-temperature, fine-pitch interconnections using self-patternable metallic nanoparticles as the bonding layer","authors":"G. Mehrotra, G. Jha, J. Goud, P. Raj, M. Venkatesan, M. Iyer, D. Hess, R. Tummala","doi":"10.1109/ECTC.2008.4550162","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550162","url":null,"abstract":"High speed digital and mixed signal applications are driving short and more reliable fine pitch interconnection with higher I/O count in 3D architectures. Thin film die to wafer and wafer to wafer bonding with copper-based interconnections have several benefits in terms of low cost, process compatibility with semiconductor infrastructure, and the shortest interconnection with the best electrical performance. However, the bonding is accomplished at around 400 C, with pressures exceeding 30 N/cm2 which may not be compatible with thinned dies, and in ultrahigh vacuum and cleanroom environments with careful copper oxide cleaning procedures. The bonding time is typically 1 hour, which also limits the throughput. The process windows are relatively narrow with several temperature compatibility issues. This paper deals with low temperature bonding process using high surface energy metallic nanoparticles such as copper and gold. Bonding is enhanced by accelerated diffusion kinetics. Self patterning technique has also been developed to assist fine pitch bonding. This is based on selective wetting or selective deposition of nanoparticles.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131460524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550035
Daeil Kwon, M. Azarian, M. Pecht
The trend for many types of electronic products is toward higher operating frequencies or digital bit rates. At high frequencies, signal propagation is concentrated at the surface of interconnects, a phenomenon known as the skin effect. Degradation of interconnects, such as cracking of solder joints due to fatigue or shock loading, also usually initiates at the surface and propagates inward. Therefore, even a small crack at the surface of a solder joint may affect the performance of high speed electronic assemblies. Traditional DC resistance measurements are not appropriate for detecting such a small fault. More accurate and sensitive alternatives are required for monitoring the reliability of current and future electronic products. RF impedance analysis offers an improved means of sensing interconnect degradation. This study demonstrates the use of RF impedance changes as an early indicator of physical degradation of solder joints, due to the skin effect, and compares this to DC resistance measurements. Mechanical shear tests at an elevated temperature have been conducted with an impedance- controlled circuit board on which a surface mount component was soldered. Simultaneous measurements were performed of DC resistance and the time domain reflection coefficient, as a measure of RF impedance, while the solder joints were stressed. The RF impedance was observed to increase in response to cracking of the solder joint earlier than the DC resistance. These results were qualitatively repeatable over multiple trials.
{"title":"Detection of solder joint degradation using RF impedance analysis","authors":"Daeil Kwon, M. Azarian, M. Pecht","doi":"10.1109/ECTC.2008.4550035","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550035","url":null,"abstract":"The trend for many types of electronic products is toward higher operating frequencies or digital bit rates. At high frequencies, signal propagation is concentrated at the surface of interconnects, a phenomenon known as the skin effect. Degradation of interconnects, such as cracking of solder joints due to fatigue or shock loading, also usually initiates at the surface and propagates inward. Therefore, even a small crack at the surface of a solder joint may affect the performance of high speed electronic assemblies. Traditional DC resistance measurements are not appropriate for detecting such a small fault. More accurate and sensitive alternatives are required for monitoring the reliability of current and future electronic products. RF impedance analysis offers an improved means of sensing interconnect degradation. This study demonstrates the use of RF impedance changes as an early indicator of physical degradation of solder joints, due to the skin effect, and compares this to DC resistance measurements. Mechanical shear tests at an elevated temperature have been conducted with an impedance- controlled circuit board on which a surface mount component was soldered. Simultaneous measurements were performed of DC resistance and the time domain reflection coefficient, as a measure of RF impedance, while the solder joints were stressed. The RF impedance was observed to increase in response to cracking of the solder joint earlier than the DC resistance. These results were qualitatively repeatable over multiple trials.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132076541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550024
N. Fediakine, Hong Shi
A design of the proper frequency behavior of a power distribution network (PDN) of input/output (I/O) circuitry of an FPGA enhances performance and is able to withstand synchronous switching noise (SSN) for applications in specific frequency bandwidths. A methodology of PDN evaluation and modeling is presented in this paper, with different types of packages having on-package decoupling capacitance (OPD) of 10 nF (chip), and embedded on-package decoupling capacitances (EPD) of 10 nF (film), and 100 nF (chip) studied for evaluation. The working models of PDN in the 300 kHz-6 GHz range for all packages are designed and summarized in the paper. Direct measurement of chip PDN impedance is quite complicated because it requires applying wideband microprobes to a very small area. Instead, a power supply compression (PSC) measurement due to SSN in FPGA is used to view the impedance from the silicon side. This method is compared with indirect measurement of PDN done from the ball side. A second method requires standard 1 mm microprobes and VNA with the following processing of data and equivalent circuit reconstruction. This very elaborate technique clearly describes one peak PDN (neither OPD nor EPD), but requires additional tweaking to get the correct peak positions of packages with OPD (or EPD).
{"title":"Evaluations of package technologies for power distribution network decoupling by measurement and correlation","authors":"N. Fediakine, Hong Shi","doi":"10.1109/ECTC.2008.4550024","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550024","url":null,"abstract":"A design of the proper frequency behavior of a power distribution network (PDN) of input/output (I/O) circuitry of an FPGA enhances performance and is able to withstand synchronous switching noise (SSN) for applications in specific frequency bandwidths. A methodology of PDN evaluation and modeling is presented in this paper, with different types of packages having on-package decoupling capacitance (OPD) of 10 nF (chip), and embedded on-package decoupling capacitances (EPD) of 10 nF (film), and 100 nF (chip) studied for evaluation. The working models of PDN in the 300 kHz-6 GHz range for all packages are designed and summarized in the paper. Direct measurement of chip PDN impedance is quite complicated because it requires applying wideband microprobes to a very small area. Instead, a power supply compression (PSC) measurement due to SSN in FPGA is used to view the impedance from the silicon side. This method is compared with indirect measurement of PDN done from the ball side. A second method requires standard 1 mm microprobes and VNA with the following processing of data and equivalent circuit reconstruction. This very elaborate technique clearly describes one peak PDN (neither OPD nor EPD), but requires additional tweaking to get the correct peak positions of packages with OPD (or EPD).","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134201903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4549994
S. Karajgikar, V. Nagaraj, D. Agonafer, S. Pekin
The advancement in flip chip technology has enabled us to meet the requirement of smaller die size along with the increased functionality. Due to this development in flip chip packaging technology along with higher current carrying requirement of solder bumps, electromigration has now become a reliability concern. In this paper, a commercially available finite element tool is adopted in order to study the distribution of current density in eutectic solder bump for variety of back end design parameters. Parameters such as passivation opening (PO) diameter, trace width, under bump metallurgy (UBM) thickness and UBM diameter were studied in detail. The results were evaluated for input currents of 0.1 A and 0.5 A. Based on the results, a guideline for solder bump configuration is proposed. In the metallization, the most important design attribute found is the Al trace width. In the solder bump, the most important parameters found are Al trace width and UBM thickness. In the metallization of the structures used in our study, current density varied from 5times105 A/cm2 to 7times105 A/cm2 and from 2.5times106 A/cm2 to 3.5times106 A/cm2 at 0.1 and 0.5 A per bump, respectively. In the solder of the structures used in our study, current density varied from 2.8times103 A/cm2 to 4.2times104 A/cm2 and from 1.4times104 and 2.1times105 A/cm2 at 0.1 and 0.5 A per bump, respectively.
{"title":"Flip chip back end design parameters to reduce bump electromigration","authors":"S. Karajgikar, V. Nagaraj, D. Agonafer, S. Pekin","doi":"10.1109/ECTC.2008.4549994","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4549994","url":null,"abstract":"The advancement in flip chip technology has enabled us to meet the requirement of smaller die size along with the increased functionality. Due to this development in flip chip packaging technology along with higher current carrying requirement of solder bumps, electromigration has now become a reliability concern. In this paper, a commercially available finite element tool is adopted in order to study the distribution of current density in eutectic solder bump for variety of back end design parameters. Parameters such as passivation opening (PO) diameter, trace width, under bump metallurgy (UBM) thickness and UBM diameter were studied in detail. The results were evaluated for input currents of 0.1 A and 0.5 A. Based on the results, a guideline for solder bump configuration is proposed. In the metallization, the most important design attribute found is the Al trace width. In the solder bump, the most important parameters found are Al trace width and UBM thickness. In the metallization of the structures used in our study, current density varied from 5times10<sup>5</sup> A/cm<sup>2</sup> to 7times10<sup>5</sup> A/cm<sup>2</sup> and from 2.5times10<sup>6</sup> A/cm<sup>2</sup> to 3.5times10<sup>6</sup> A/cm<sup>2</sup> at 0.1 and 0.5 A per bump, respectively. In the solder of the structures used in our study, current density varied from 2.8times10<sup>3</sup> A/cm<sup>2</sup> to 4.2times10<sup>4</sup> A/cm<sup>2</sup> and from 1.4times10<sup>4</sup> and 2.1times10<sup>5</sup> A/cm<sup>2</sup> at 0.1 and 0.5 A per bump, respectively.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131831844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550045
R. Oikawa
This paper proposes a new method to resolve the on-die capacitance issue of the high-seed SerDes (serializer-deserializer). This issue can be resolved by incorporating a three-dimensionally controlled distributed impedance matching circuit into the package substrate. The distributed matching circuit has been applied to the 6.25 Gbps SerDes device by using a conventional build-up substrate as a package substrate. As a result, the return loss showed a ~6 dB (~200%) improvement as well as showing a better signal waveform than standard 50 Ohm package design. Because this method does not require any additional manufacturing technology other than conventional build-up substrate, the cost of high speed (Gbps) communication devices can be reduced and also extend conventional technology to the even higher speed devices.
{"title":"Package substrate built-in three-dimensional distributed matching circuit for high-speed SerDes applications","authors":"R. Oikawa","doi":"10.1109/ECTC.2008.4550045","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550045","url":null,"abstract":"This paper proposes a new method to resolve the on-die capacitance issue of the high-seed SerDes (serializer-deserializer). This issue can be resolved by incorporating a three-dimensionally controlled distributed impedance matching circuit into the package substrate. The distributed matching circuit has been applied to the 6.25 Gbps SerDes device by using a conventional build-up substrate as a package substrate. As a result, the return loss showed a ~6 dB (~200%) improvement as well as showing a better signal waveform than standard 50 Ohm package design. Because this method does not require any additional manufacturing technology other than conventional build-up substrate, the cost of high speed (Gbps) communication devices can be reduced and also extend conventional technology to the even higher speed devices.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131849665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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