Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550080
S. Wright, P. Andry, E. Sprogis, B. Dang, R. Polastre
A robust through-silicon via technology is necessary for high-power, high-performance 3D-silicon applications. To study through-via interconnection reliability, modules consisting of a test chip, silicon carrier interposer with through-vias, and ceramic substrate were constructed. A socket assembly containing a microchannel water cooler was also constructed to apply pulsed power to via daisy chain test sites. Test results to date indicate that the interconnection reliability is limited by the solder bump portions of the interconnection, not the through-silicon via itself.
{"title":"Reliability testing of through-silicon vias for high-current 3D applications","authors":"S. Wright, P. Andry, E. Sprogis, B. Dang, R. Polastre","doi":"10.1109/ECTC.2008.4550080","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550080","url":null,"abstract":"A robust through-silicon via technology is necessary for high-power, high-performance 3D-silicon applications. To study through-via interconnection reliability, modules consisting of a test chip, silicon carrier interposer with through-vias, and ceramic substrate were constructed. A socket assembly containing a microchannel water cooler was also constructed to apply pulsed power to via daisy chain test sites. Test results to date indicate that the interconnection reliability is limited by the solder bump portions of the interconnection, not the through-silicon via itself.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131179518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550161
A. Shigetou, T. Itoh, K. Sawada, T. Suga
Bumpless interconnect of 6-mum-pitch Cu electrodes was realized at room temperature with the surface activated bonding (SAB) method. In this study, we propose a novel bumpless structure, where the electrodes and a surrounding Cu frame are fabricated with the same height to increase bond strength and demonstrate the feasibility of a sealing interconnection between Cu surfaces. The Cu damascene process, assisted by the reactive ion beam etching (RIE) process, was used to fabricate the Cu structures. 1,048,748 electrodes were fabricated in a square of about 6-mm2 area; 923,521 connections were placed inside the 10-mum-wide Cu frame. These 923,521 electrodes were arranged into a spiral chain to enable the detection of the positions with insufficient interconnection by electrical resistance measurements. Using the SAB conditions optimized in the previous studies, we found that 744,769 electrodes among them were successfully interconnected. The failure in the electrical interconnection reappeared in some lines near the frame of all samples. The optical beam induced resistance change (OBIRCH) analysis, in which particularly high resistance is presented as a bright contrast, showed that these insufficient connections might be due to sample preparation error rather than a bond defect, because high resistance was observed only at some specific electrodes amid the line in this area. In other well-bonded area, the mean contact resistance was as low as 0.08 Omega; it is considered that a sealing effect was achieved at the frame structure because there was little increase in the contact resistance in high temperature storage test performed at 150degC for 1000 h, in ambient air.
{"title":"Bumpless interconnect of 6-μm pitch Cu electrodes at room temperature","authors":"A. Shigetou, T. Itoh, K. Sawada, T. Suga","doi":"10.1109/ECTC.2008.4550161","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550161","url":null,"abstract":"Bumpless interconnect of 6-mum-pitch Cu electrodes was realized at room temperature with the surface activated bonding (SAB) method. In this study, we propose a novel bumpless structure, where the electrodes and a surrounding Cu frame are fabricated with the same height to increase bond strength and demonstrate the feasibility of a sealing interconnection between Cu surfaces. The Cu damascene process, assisted by the reactive ion beam etching (RIE) process, was used to fabricate the Cu structures. 1,048,748 electrodes were fabricated in a square of about 6-mm2 area; 923,521 connections were placed inside the 10-mum-wide Cu frame. These 923,521 electrodes were arranged into a spiral chain to enable the detection of the positions with insufficient interconnection by electrical resistance measurements. Using the SAB conditions optimized in the previous studies, we found that 744,769 electrodes among them were successfully interconnected. The failure in the electrical interconnection reappeared in some lines near the frame of all samples. The optical beam induced resistance change (OBIRCH) analysis, in which particularly high resistance is presented as a bright contrast, showed that these insufficient connections might be due to sample preparation error rather than a bond defect, because high resistance was observed only at some specific electrodes amid the line in this area. In other well-bonded area, the mean contact resistance was as low as 0.08 Omega; it is considered that a sealing effect was achieved at the frame structure because there was little increase in the contact resistance in high temperature storage test performed at 150degC for 1000 h, in ambient air.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130728868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550076
T. Kuo, Shu-Ming Chang, Y. Shih, C. Chiang, Chao-Kai Hsu, Ching-Kuan Lee, Chun-Te Lin, Yu-Hua Chen, W. Lo
In order to achieve the shorter circuit design of multiple chips, three-dimensional (3D) packaging technologies with through silicon vias were developed to achieve high performance, low power consumption and small packaging size. In this paper, a PCB (Printed Circuit Board) processing compatible structure of three-dimensional chip stacking with low cost and easy fabrication will be shown. 3D and through Si via connections were formed by UV laser drilling technology. Laser drilling is a non-contact manufacture method and laser beam with high energy can be focused to a small spot (15 mum beam diameter) for material ablating and removing without mask used. Several processes are the keys to accomplish 3D stacking, such as wafer thinning process, through silicon via forming process, dielectric layer forming process, metallization process, and inter chips bonding process. By integration of the mentioned key processes, a 3D chip stacking structure with 10 layers was carried out. The thickness of chip was 100 mum. Daisy chain pattern was designed for the electrical measurement of 3D stacking structure. The testing results show that the resistance of multi- chip stacking structure is about 0.056 Omega/cm. Some reliability test, such as temperature cycling test and pressure cooker test were also done. These testing results verified this PCB processing compatible 3D chip stacking technology with low cost is a reliable structure for 3D SiP (System in Packaging) module application.
为了实现多芯片的更短电路设计，开发了硅通孔三维封装技术，以实现高性能、低功耗和小封装尺寸。本文将展示一种低成本、易于制造的三维芯片堆叠PCB (Printed Circuit Board)加工兼容结构。通过UV激光钻孔技术形成3D和through Si via连接。激光打孔是一种非接触式制造方法，高能量的激光束可以聚焦到一个小点(15 μ m光束直径)，无需使用掩模即可进行材料的烧蚀和去除。实现三维堆叠的关键工艺有:晶圆减薄工艺、硅通孔成形工艺、介电层成形工艺、金属化工艺和芯片间键合工艺。通过集成上述关键工艺，实现了10层的三维芯片堆叠结构。切片厚度为100 μ m。设计了雏菊链图，用于三维堆垛结构的电测量。测试结果表明，多芯片堆叠结构的电阻约为0.056 ω /cm。并进行了温度循环试验、高压锅试验等可靠性试验。这些测试结果验证了这种低成本的PCB加工兼容3D芯片堆叠技术是3D封装系统(System in Packaging, SiP)模块应用的可靠结构。
{"title":"Reliability tests for a three dimensional chip stacking structure with through silicon via connections and low cost","authors":"T. Kuo, Shu-Ming Chang, Y. Shih, C. Chiang, Chao-Kai Hsu, Ching-Kuan Lee, Chun-Te Lin, Yu-Hua Chen, W. Lo","doi":"10.1109/ECTC.2008.4550076","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550076","url":null,"abstract":"In order to achieve the shorter circuit design of multiple chips, three-dimensional (3D) packaging technologies with through silicon vias were developed to achieve high performance, low power consumption and small packaging size. In this paper, a PCB (Printed Circuit Board) processing compatible structure of three-dimensional chip stacking with low cost and easy fabrication will be shown. 3D and through Si via connections were formed by UV laser drilling technology. Laser drilling is a non-contact manufacture method and laser beam with high energy can be focused to a small spot (15 mum beam diameter) for material ablating and removing without mask used. Several processes are the keys to accomplish 3D stacking, such as wafer thinning process, through silicon via forming process, dielectric layer forming process, metallization process, and inter chips bonding process. By integration of the mentioned key processes, a 3D chip stacking structure with 10 layers was carried out. The thickness of chip was 100 mum. Daisy chain pattern was designed for the electrical measurement of 3D stacking structure. The testing results show that the resistance of multi- chip stacking structure is about 0.056 Omega/cm. Some reliability test, such as temperature cycling test and pressure cooker test were also done. These testing results verified this PCB processing compatible 3D chip stacking technology with low cost is a reliable structure for 3D SiP (System in Packaging) module application.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132664075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550105
A. Agwai, I. Guven, E. Madenci
In this study, peridynamic theory is used to investigate dynamic response of electronic packages subjected to impact loading arising from drop-shock. First, the theory is briefly described, followed by validation against a fundamental dynamic fracture problem. Finally, peridynamic theory was demonstrated by considering a drop test experiment.
{"title":"Peridynamic theory for impact damage prediction and propagation in electronic packages due to drop","authors":"A. Agwai, I. Guven, E. Madenci","doi":"10.1109/ECTC.2008.4550105","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550105","url":null,"abstract":"In this study, peridynamic theory is used to investigate dynamic response of electronic packages subjected to impact loading arising from drop-shock. First, the theory is briefly described, followed by validation against a fundamental dynamic fracture problem. Finally, peridynamic theory was demonstrated by considering a drop test experiment.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131413907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550095
D. Liang, A. Fang, J. Bowers
We report the large epitaxial transfer of 100 mm InP/InGaAs/InP wafers to Silicon-on-insulator (SOI) substrates through a low-temperature (300degC) O2 plasma- assisted wafer bonding process. Efficient vertical outgassing channels (VOCs) are developed to eliminate the fundamental obstacle of interfacial voids in bonding due to intrinsic chemical reactions. Generated gas species of H2O and H2 can quickly diffuse to VOCs, etched through-holes to buried oxide layer (BOX), and absorbed by the BOX layer owing to the open network structure and large gas permeability. The interfacial void density is reduced from 55,000 cm-2 down to 3 cm-2, more than five orders of magnitude reduction for appropriate design of VOCs. Uniform patterning of VOCs leads to a no outgassing "dead zone" across the entire bonding area, and decrease of the thermal mismatch-induced interfacial strain potentially as well, which both result in the wafer scale-independent bonding. The bonding strain is observed through X-ray rocking curve measurement conducted on both of a 2 times 2 cm2 bonded pair and 100 mm wafer-scale bonding sample. A variety of devices have been fabricated using this technique. As one example, hybrid silicon evanescent distributed feedback (DFB) lasers integrated with monitor photodiodes have been fabricated using this bonding technique. These highly single mode lasers may find applications in computer interconnects.
我们报道了通过低温(300℃)O2等离子体辅助晶圆键合工艺将100 mm InP/InGaAs/InP晶圆大规模外延转移到绝缘体上硅(SOI)衬底上。高效的垂直放气通道(VOCs)被开发出来，以消除由于内在化学反应而导致的界面空隙对键合的根本障碍。由于网状结构开放，透气性大，生成的H2O和H2气体可以快速扩散到VOCs中，通过孔洞蚀蚀到埋藏氧化层(BOX)，并被BOX层吸收。界面空隙密度从55000 cm-2降至3 cm-2，降低了5个数量级以上，有利于VOCs的合理设计。挥发性有机化合物的均匀分布导致整个键合区域没有放气的“死区”，并且潜在地减少了热不匹配引起的界面应变，这两者都导致了晶圆尺度无关的键合。通过对2 × 2 cm2键合对和100 mm晶圆尺度键合样品进行x射线摇摆曲线测量，观察键合应变。利用这种技术已经制造了各种各样的器件。作为一个例子，利用这种键合技术，已经制造出了与监测光电二极管集成的混合硅倏逝分布反馈(DFB)激光器。这些高度单模激光器可以在计算机互连中找到应用。
{"title":"100 mm wafer-scale InP-based (λ=1.6 μm) epitaxial transfer for hybrid silicon evanescent lasers","authors":"D. Liang, A. Fang, J. Bowers","doi":"10.1109/ECTC.2008.4550095","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550095","url":null,"abstract":"We report the large epitaxial transfer of 100 mm InP/InGaAs/InP wafers to Silicon-on-insulator (SOI) substrates through a low-temperature (300degC) O2 plasma- assisted wafer bonding process. Efficient vertical outgassing channels (VOCs) are developed to eliminate the fundamental obstacle of interfacial voids in bonding due to intrinsic chemical reactions. Generated gas species of H2O and H2 can quickly diffuse to VOCs, etched through-holes to buried oxide layer (BOX), and absorbed by the BOX layer owing to the open network structure and large gas permeability. The interfacial void density is reduced from 55,000 cm-2 down to 3 cm-2, more than five orders of magnitude reduction for appropriate design of VOCs. Uniform patterning of VOCs leads to a no outgassing \"dead zone\" across the entire bonding area, and decrease of the thermal mismatch-induced interfacial strain potentially as well, which both result in the wafer scale-independent bonding. The bonding strain is observed through X-ray rocking curve measurement conducted on both of a 2 times 2 cm2 bonded pair and 100 mm wafer-scale bonding sample. A variety of devices have been fabricated using this technique. As one example, hybrid silicon evanescent distributed feedback (DFB) lasers integrated with monitor photodiodes have been fabricated using this bonding technique. These highly single mode lasers may find applications in computer interconnects.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131675423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4549984
M. Wojnowski, M. Engl, B. Dehlink, G. Sommer, M. Brunnbauer, K. Pressel, R. Weigel
We present a fully operational 77 GHz SiGe mixer assembled in a chip-scale embedded wafer level BGA (eWLB) package. This innovative package has a footprint with a standard pad pitch of 0.5 mm and a standard package height of 0.4 mm. The results demonstrate an excellent potential of the eWLB package concept for mm-wave applications. The measured gain of the packaged mixer is in best case only 1 dB smaller than measured on-wafer. Further, we analyze the transition from the printed circuit board (PCB) to the chip in package. We compare the results of our analysis with the measured performance of the packaged mixers. We achieve a good agreement between simulations and measurements. Finally, we discuss the methods for improving the electrical performance of the packages assembled on the PCB.
{"title":"A 77 GHz SiGe mixer in an embedded wafer level BGA package","authors":"M. Wojnowski, M. Engl, B. Dehlink, G. Sommer, M. Brunnbauer, K. Pressel, R. Weigel","doi":"10.1109/ECTC.2008.4549984","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4549984","url":null,"abstract":"We present a fully operational 77 GHz SiGe mixer assembled in a chip-scale embedded wafer level BGA (eWLB) package. This innovative package has a footprint with a standard pad pitch of 0.5 mm and a standard package height of 0.4 mm. The results demonstrate an excellent potential of the eWLB package concept for mm-wave applications. The measured gain of the packaged mixer is in best case only 1 dB smaller than measured on-wafer. Further, we analyze the transition from the printed circuit board (PCB) to the chip in package. We compare the results of our analysis with the measured performance of the packaged mixers. We achieve a good agreement between simulations and measurements. Finally, we discuss the methods for improving the electrical performance of the packages assembled on the PCB.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114319743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/EPTC.2008.4763517
H.-Y Son, K. Paik, Il-ho Kim, Jin-Hyoung Park, Soon-Bok Lee, Gi-Jo Jung, Byung-Jin Park, Kwang-yoo Byun
A thick Cu column based double-bump flip-chip structure is one of the promising alternatives for fine pitch flip-chip applications. In this study, the thermal cycling (T/C) reliability of Cu/SnAg double-bump flip-chip assemblies was firstly investigated and the failure mechanism was analyzed through correlation of T/C test and the finite element analysis (FEA) results. After 1000 thermal cycles, the T/C failure site was the Cu column/Si chip interface, where was identified via a FEA as the location of the maximum stress concentration during thermal cycling. During thermal cycling, the Al pad and Ti layer between the Si chip and Cu column bumps were displaced due to thermo-mechanical stress. Based on the low cycle fatigue model, the accumulation of equivalent plastic strain resulted in thermal fatigue deformation of the Cu column bumps, and ultimately reduced the thermal cycling lifetime. In addition, the normal plastic strain of the y-direction, 822, was determined to be compressive and was a dominant component in relation to the plastic deformation of Cu/SnAg double-bumps. As the number of thermal cycles increased, normal plastic strains in the perpendicular direction to the Si chip were accumulated on the Cu column bumps at the chip edge in the low temperature region. Thus it was found that displacement failure of the Al pad and Ti layer, the main T/C failure mode of the Cu/SnAg flip-chip assembly, occurred at the Si chip/Cu column interface by compressive normal deformation during thermal cycling. Next, the effect of Cu column height was investigated for the enhancement T/C reliability. As results of T/C test for 60 um and 85 um Cu column heights, flip chip assemblies with thicker Cu column height showed better T/C reliability. In the real time moire interferomerry, shear strain and normal strain of the x-direction was almost same regardless of Cu column height. On the other hand, the normal strain of y-direction (perpendicular direction to the Si chip) at Si chip/Cu column interface for 85 um-thick Cu samples shows significantly reduced value compared with 60 um-thick Cu samples. This relaxation of the normal plastic strain of the y-direction is the origin that thicker Cu column height guarantees better T/C reliability.
{"title":"Studies on the thermal cycling reliability of fine pitch Cu/SnAg double-bump flip chip assemblies on organic substrates: Experimental results and numerical analysis","authors":"H.-Y Son, K. Paik, Il-ho Kim, Jin-Hyoung Park, Soon-Bok Lee, Gi-Jo Jung, Byung-Jin Park, Kwang-yoo Byun","doi":"10.1109/EPTC.2008.4763517","DOIUrl":"https://doi.org/10.1109/EPTC.2008.4763517","url":null,"abstract":"A thick Cu column based double-bump flip-chip structure is one of the promising alternatives for fine pitch flip-chip applications. In this study, the thermal cycling (T/C) reliability of Cu/SnAg double-bump flip-chip assemblies was firstly investigated and the failure mechanism was analyzed through correlation of T/C test and the finite element analysis (FEA) results. After 1000 thermal cycles, the T/C failure site was the Cu column/Si chip interface, where was identified via a FEA as the location of the maximum stress concentration during thermal cycling. During thermal cycling, the Al pad and Ti layer between the Si chip and Cu column bumps were displaced due to thermo-mechanical stress. Based on the low cycle fatigue model, the accumulation of equivalent plastic strain resulted in thermal fatigue deformation of the Cu column bumps, and ultimately reduced the thermal cycling lifetime. In addition, the normal plastic strain of the y-direction, 822, was determined to be compressive and was a dominant component in relation to the plastic deformation of Cu/SnAg double-bumps. As the number of thermal cycles increased, normal plastic strains in the perpendicular direction to the Si chip were accumulated on the Cu column bumps at the chip edge in the low temperature region. Thus it was found that displacement failure of the Al pad and Ti layer, the main T/C failure mode of the Cu/SnAg flip-chip assembly, occurred at the Si chip/Cu column interface by compressive normal deformation during thermal cycling. Next, the effect of Cu column height was investigated for the enhancement T/C reliability. As results of T/C test for 60 um and 85 um Cu column heights, flip chip assemblies with thicker Cu column height showed better T/C reliability. In the real time moire interferomerry, shear strain and normal strain of the x-direction was almost same regardless of Cu column height. On the other hand, the normal strain of y-direction (perpendicular direction to the Si chip) at Si chip/Cu column interface for 85 um-thick Cu samples shows significantly reduced value compared with 60 um-thick Cu samples. This relaxation of the normal plastic strain of the y-direction is the origin that thicker Cu column height guarantees better T/C reliability.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114327060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550209
D. D. Evans
Solid State Lighting is pervasive and will continue to grow in popularity as performance and costs mature. Products include camera phone flashes, televisions, display backlighting, automotive lighting, medical products, architectural lighting, projectors, and others still in development. Reaching performance and cost targets will require continuous improvements in LED devices and packaging to extract ever increasing lumens per watt. Several new products use a matrix of LED devices packaged together. These matrix LED packages present challenges for both die attach and wire bonding compared to single die packages. A brief overview of market applications and the package options is presented. A case study is presented to highlight the challenges and solutions when producing matrix LED packages. Pulsed heat eutectic die attach and wire chain bonding are explored for application to matrix LED assembly.
{"title":"High brightness matrix LED assembly challenges and solutions","authors":"D. D. Evans","doi":"10.1109/ECTC.2008.4550209","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550209","url":null,"abstract":"Solid State Lighting is pervasive and will continue to grow in popularity as performance and costs mature. Products include camera phone flashes, televisions, display backlighting, automotive lighting, medical products, architectural lighting, projectors, and others still in development. Reaching performance and cost targets will require continuous improvements in LED devices and packaging to extract ever increasing lumens per watt. Several new products use a matrix of LED devices packaged together. These matrix LED packages present challenges for both die attach and wire bonding compared to single die packages. A brief overview of market applications and the package options is presented. A case study is presented to highlight the challenges and solutions when producing matrix LED packages. Pulsed heat eutectic die attach and wire chain bonding are explored for application to matrix LED assembly.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114310151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550217
W. V. van Driel, J. Zaal, D.G. Yang, M. van Kleef, G.Q. Zhang
This paper presents our effort to predict reliability problems for MEMS packages. MEMS devices are vulnerable to the external loads subjected to it. As such, MEMS devices need to be protected. Capping the device can generate protections: a piece of silicon is placed on top of it to create a cavity above it. Parametric Finite Element models are combined with dedicated verification experiments to address the reliability of four different capping concepts. The results gain a better understanding of MEMS capping issues, with failure modes as cavity deflection, cap fractures, and moisture penetration.
{"title":"Mechanical reliability of MEMS packages","authors":"W. V. van Driel, J. Zaal, D.G. Yang, M. van Kleef, G.Q. Zhang","doi":"10.1109/ECTC.2008.4550217","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550217","url":null,"abstract":"This paper presents our effort to predict reliability problems for MEMS packages. MEMS devices are vulnerable to the external loads subjected to it. As such, MEMS devices need to be protected. Capping the device can generate protections: a piece of silicon is placed on top of it to create a cavity above it. Parametric Finite Element models are combined with dedicated verification experiments to address the reliability of four different capping concepts. The results gain a better understanding of MEMS capping issues, with failure modes as cavity deflection, cap fractures, and moisture penetration.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114564808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4549997
H. Noda, M. Usami
An ultra-small (0.075x0.075-mm area) ultra-thin (7.5-mum thickness) radio-frequency identification (RFID) chip, called a "mu-chip," is expected to be adopted in applications like counterfeit prevention and product tracking of paper media and other small goods. For adoption in these applications, technology for mounting a mu-chip on an external antenna must be developed. Accordingly, we have developed a new technique for handling ultra-small mu-chips (called the "UH technique") by means of an automated apparatus. By the UH technique, the mu-chips are kept dispersed by liquid agitation, and only a single chip is captured and manipulated by micropipette. The efficiency of capturing a single mu-chip depends on the micropipette configuration, number of chips, and mu-chip stock solutions. A flat-end glass capillary micropipette with an inner and outer diameter of, respectively, 41 and 87 mum, which was treated by an optic-fiber cleaver, only successfully captured a single chip with an ideal orientation. The yield rate of capturing a single mu-chip, picked up from various types of liquid solutions, was investigated. This investigation found that a surfactant addition to the mu-chip stock solutions effectively prevented sticking between chips. In single-chip capturing performed in 0.5% NP-40, yield rate was 62%. Mounting of single mu-chips on films with constant 0.7-mm pitch was demonstrated. The time needed for an automated procedure for manipulating 100 chips was 44 min (26.4 s/chip).
{"title":"0.075 × 0.075 mm2 ultra-small 7.5 μm ultra-thin RFID-chip mounting technology","authors":"H. Noda, M. Usami","doi":"10.1109/ECTC.2008.4549997","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4549997","url":null,"abstract":"An ultra-small (0.075x0.075-mm area) ultra-thin (7.5-mum thickness) radio-frequency identification (RFID) chip, called a \"mu-chip,\" is expected to be adopted in applications like counterfeit prevention and product tracking of paper media and other small goods. For adoption in these applications, technology for mounting a mu-chip on an external antenna must be developed. Accordingly, we have developed a new technique for handling ultra-small mu-chips (called the \"UH technique\") by means of an automated apparatus. By the UH technique, the mu-chips are kept dispersed by liquid agitation, and only a single chip is captured and manipulated by micropipette. The efficiency of capturing a single mu-chip depends on the micropipette configuration, number of chips, and mu-chip stock solutions. A flat-end glass capillary micropipette with an inner and outer diameter of, respectively, 41 and 87 mum, which was treated by an optic-fiber cleaver, only successfully captured a single chip with an ideal orientation. The yield rate of capturing a single mu-chip, picked up from various types of liquid solutions, was investigated. This investigation found that a surfactant addition to the mu-chip stock solutions effectively prevented sticking between chips. In single-chip capturing performed in 0.5% NP-40, yield rate was 62%. Mounting of single mu-chips on films with constant 0.7-mm pitch was demonstrated. The time needed for an automated procedure for manipulating 100 chips was 44 min (26.4 s/chip).","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116978352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：