Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550153
M. Rowlands, R. Das
We have designed and built a LCP-based flip-chip package using Z-interconnect building blocks for reliability and electrical performance. Manufacturing a Z-interconnect substrate involves building mini-substrates (sub-composites) of 2 or 3 layers each, then assembling several mini-substrates together to make the finished product. "Z-interconnect" is used to connect metal layers vertically, using a conductive adhesive. Z-axis interconnection was achieved using joining cores. Through holes in the joining cores, formed by laser drilling and having diameters 60 microns, were filled with an optimized, electrically conductive adhesive. The adhesive- filled joining cores were laminated with circuitized sub- composites to produce a composite structure. High temperature lamination was used to cure the adhesive in the composite and provide Z-interconnection among the circuitized sub-composites. Designing and manufacturing the mini-substrates separately makes it possible to reliably manufacture substrates with no via stubs, very low-loss materials, nearly arbitrary transmission line structures and lots of flexibility to tune features to reduce signal loss. Here we are using 5 sub-composites with 16 metal layers , including 3 0S2P joining cores, 2 2S2P signals cores, plated copper on top and bottom and embedded resistance on layer 7. Each sub-composite (0S2P/2S2P) made with high and low melting point LCP. There was no de-lamination of conductive adhesive filled LCP samples after pressure cooker test (PCT), and solder shock. Evaluation criteria for the test vehicle will include its ability to perform as a reliable, manufacturable, high-performance substrate. Results will be compared to typical ceramic and PTFE chip packages and the improvements over ceramic will be noted.
{"title":"Manufacture and ultra-high frequency performance of an LCP-based, Z-interconnect, flip-chip package","authors":"M. Rowlands, R. Das","doi":"10.1109/ECTC.2008.4550153","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550153","url":null,"abstract":"We have designed and built a LCP-based flip-chip package using Z-interconnect building blocks for reliability and electrical performance. Manufacturing a Z-interconnect substrate involves building mini-substrates (sub-composites) of 2 or 3 layers each, then assembling several mini-substrates together to make the finished product. \"Z-interconnect\" is used to connect metal layers vertically, using a conductive adhesive. Z-axis interconnection was achieved using joining cores. Through holes in the joining cores, formed by laser drilling and having diameters 60 microns, were filled with an optimized, electrically conductive adhesive. The adhesive- filled joining cores were laminated with circuitized sub- composites to produce a composite structure. High temperature lamination was used to cure the adhesive in the composite and provide Z-interconnection among the circuitized sub-composites. Designing and manufacturing the mini-substrates separately makes it possible to reliably manufacture substrates with no via stubs, very low-loss materials, nearly arbitrary transmission line structures and lots of flexibility to tune features to reduce signal loss. Here we are using 5 sub-composites with 16 metal layers , including 3 0S2P joining cores, 2 2S2P signals cores, plated copper on top and bottom and embedded resistance on layer 7. Each sub-composite (0S2P/2S2P) made with high and low melting point LCP. There was no de-lamination of conductive adhesive filled LCP samples after pressure cooker test (PCT), and solder shock. Evaluation criteria for the test vehicle will include its ability to perform as a reliable, manufacturable, high-performance substrate. Results will be compared to typical ceramic and PTFE chip packages and the improvements over ceramic will be noted.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127502293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550200
Zhang Kai, M. Yuen, D. Xiao, Y. Fu, P. Chan
Vertically aligned carbon nanotube (VACNT) arrays were synthesized directly on aluminum alloy substrates by thermal chemical vapor deposition (CVD). Iron nitrate (Fe(NO3)3ldr9H2O) was used as the catalyst. Parameters influencing CNT synthesis were studied and optimized. Several surface treatment methods were proposed to improve the quality of CNTs synthesized on aluminum alloy substrates. The grown CNT arrays were used as thermal interface material (TIM) while the aluminum alloy substrate used as the heat sink in high brightness LED packages. The measured thermal resistance of the grown CNT-TIM was 38 mm2-K/W. The output light power testing demonstrated CNT-TIM is an attractive thermal management solution for HB- LED packages.
{"title":"Directly synthesizing CNT-TIM on aluminum alloy heat sink for HB-LED thermal management","authors":"Zhang Kai, M. Yuen, D. Xiao, Y. Fu, P. Chan","doi":"10.1109/ECTC.2008.4550200","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550200","url":null,"abstract":"Vertically aligned carbon nanotube (VACNT) arrays were synthesized directly on aluminum alloy substrates by thermal chemical vapor deposition (CVD). Iron nitrate (Fe(NO3)3ldr9H2O) was used as the catalyst. Parameters influencing CNT synthesis were studied and optimized. Several surface treatment methods were proposed to improve the quality of CNTs synthesized on aluminum alloy substrates. The grown CNT arrays were used as thermal interface material (TIM) while the aluminum alloy substrate used as the heat sink in high brightness LED packages. The measured thermal resistance of the grown CNT-TIM was 38 mm2-K/W. The output light power testing demonstrated CNT-TIM is an attractive thermal management solution for HB- LED packages.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132885754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550273
Xiaohui Song, Sheng Liu, Han Yan, Z. Gan
An ab initio approach of Car-Parrinello molecular dynamics is used to study the chemisorption of a single oxygen atom on outer surface of zigzag single-wall carbon nanotubes under various uniaxial strains and bending deformation. The effect of mechanical deformation on adsorption of oxygen atom on CNT is demonstrated by linking the chemical reactivity and structural deformation. The adsorption energy Eb and pyramidalization angle thetasP are obtained by structural relaxation calculations, and ground- state electronic structures are described according to density functional theory (DFT) within a plane-wave pseudopotential framework. Our results show that the surface reactivity of CNT is mostly determined by its pyramidalization angle of carbon atom. For bending SWCNT, both Eb and thetasP vary with adsorption sites, the Eb is higher at sites with larger pyramidalization angle. An approximate linear relation of strain and adsorption energy can be obtained. It is indicated that the structure of CNT is crucial for its surface reactivity, and the mechanical deformation can be a method for controlling the surface reactivity of CNT and offering adsorption site selectivity as the adsorption is facilitated on the sites with higher pyramidalization angle.
{"title":"Effects of mechanical deformation on outer surface reactivity of carbon nanotubes","authors":"Xiaohui Song, Sheng Liu, Han Yan, Z. Gan","doi":"10.1109/ECTC.2008.4550273","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550273","url":null,"abstract":"An ab initio approach of Car-Parrinello molecular dynamics is used to study the chemisorption of a single oxygen atom on outer surface of zigzag single-wall carbon nanotubes under various uniaxial strains and bending deformation. The effect of mechanical deformation on adsorption of oxygen atom on CNT is demonstrated by linking the chemical reactivity and structural deformation. The adsorption energy Eb and pyramidalization angle thetasP are obtained by structural relaxation calculations, and ground- state electronic structures are described according to density functional theory (DFT) within a plane-wave pseudopotential framework. Our results show that the surface reactivity of CNT is mostly determined by its pyramidalization angle of carbon atom. For bending SWCNT, both Eb and thetasP vary with adsorption sites, the Eb is higher at sites with larger pyramidalization angle. An approximate linear relation of strain and adsorption energy can be obtained. It is indicated that the structure of CNT is crucial for its surface reactivity, and the mechanical deformation can be a method for controlling the surface reactivity of CNT and offering adsorption site selectivity as the adsorption is facilitated on the sites with higher pyramidalization angle.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114906209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550146
Jin Liu, J. Goud, P. Raj, M. Iyer, Z. Wang, R. Tummala
A nanoscale semiconducting ZnO based biosensor with integrated microfluidics is designed, fabricated and tested to demonstrate the detection of streptavidin, a commonly used protein. Amperometric (I-t) measurement is utilized to detect the change of conductivity over time. By comparing with the control experiment, the specific binding event between biotin and streptavidin is detected. The data indicates a conductivity change by more than 20% after the protein hybridization. The second part of the papers presents a ZnO thin film based biosensor which is integated with a microfluidic system. Same experiment protocols are carried and similar change in I-t characteristics is observed. This is the first demonstration of real time biosensing with ZnO nanowires and thin films that are integrated with microfluidic systems. This can be further extended to fabricate bio-sensors which can potentially detect any protein in real time. Amperometric sensing results in a label-free detection system as it detects the protein hybridization events electrically. when integrated on the system-on-package (SOP) platform, this technology can lead to portable, reliable and cost effective biosensors with applications in many areas.
{"title":"Real-time protein detection using ZnO nanowire/thin film bio-sensor integrated with microfluidic system","authors":"Jin Liu, J. Goud, P. Raj, M. Iyer, Z. Wang, R. Tummala","doi":"10.1109/ECTC.2008.4550146","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550146","url":null,"abstract":"A nanoscale semiconducting ZnO based biosensor with integrated microfluidics is designed, fabricated and tested to demonstrate the detection of streptavidin, a commonly used protein. Amperometric (I-t) measurement is utilized to detect the change of conductivity over time. By comparing with the control experiment, the specific binding event between biotin and streptavidin is detected. The data indicates a conductivity change by more than 20% after the protein hybridization. The second part of the papers presents a ZnO thin film based biosensor which is integated with a microfluidic system. Same experiment protocols are carried and similar change in I-t characteristics is observed. This is the first demonstration of real time biosensing with ZnO nanowires and thin films that are integrated with microfluidic systems. This can be further extended to fabricate bio-sensors which can potentially detect any protein in real time. Amperometric sensing results in a label-free detection system as it detects the protein hybridization events electrically. when integrated on the system-on-package (SOP) platform, this technology can lead to portable, reliable and cost effective biosensors with applications in many areas.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133762540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550021
M. Degerstrom, B. Buhrow, B. McCoy, P. Zabinski, B. Gilbert, E. Daniel
Weave-induced skew on printed wiring boards (PWB) for 10+ Gbps SerDes data rates can be very significant. In this paper, we not only investigate weave-induced skew but also look at other sources of skew. We show the weave skew results taken from measurements of three different test boards. Results from a fourth board are presented to examine PWB differential via skew. Measurements from a fifth board are analyzed to determine total channel skew. We propose a budget such that a certain amount of skew can be tolerated with a small increase in channel insertion loss. We then present a case study to project overall performance on PWB yield. We observe a number of anomalies with our test results and suggest additional studies to guard against unpredicted high skew.
{"title":"System level approach for assessing and mitigating differential skew for 10+ Gbps SerDes applications","authors":"M. Degerstrom, B. Buhrow, B. McCoy, P. Zabinski, B. Gilbert, E. Daniel","doi":"10.1109/ECTC.2008.4550021","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550021","url":null,"abstract":"Weave-induced skew on printed wiring boards (PWB) for 10+ Gbps SerDes data rates can be very significant. In this paper, we not only investigate weave-induced skew but also look at other sources of skew. We show the weave skew results taken from measurements of three different test boards. Results from a fourth board are presented to examine PWB differential via skew. Measurements from a fifth board are analyzed to determine total channel skew. We propose a budget such that a certain amount of skew can be tolerated with a small increase in channel insertion loss. We then present a case study to project overall performance on PWB yield. We observe a number of anomalies with our test results and suggest additional studies to guard against unpredicted high skew.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"271 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116834475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550084
D. Shi, Xuejun Fan, B. Xie
In order to devise an equivalent accelerated moisture sensitivity test, the JEDEC specification J-STD-020C has recommended an accelerated preconditioning time of 40 hrs exposure under 60degC / 60% RH, which is considered equivalent to the standard moisture sensitivity level 3 (MSL-3) of 216 hrs soak time under 30degC / 60% RH. However, the existing methodology for the accelerated moisture sensitivity test was developed based on the equivalency of local moisture concentration at the interest of location for leaded packages only. The failure mechanism is restricted to the potential delamination between mold compound and leadframe. In addition, such an equivalency requires the activation energy of molding compound for moisture diffusion in the range of 0.4 - 0.48 eV. This paper introduces a new method to accelerate JEDEC/IPC moisture sensitivity level testing. The methodology is developed based on the equivalency of both local moisture concentration and overall moisture distribution of packages. The local moisture concentration equivalency ensures identical adhesion strength and vapor pressure at interfaces of the interest, and the overall moisture distribution equivalency results in the same condition of applied driving forces, such as thermal and hygroscopic stresses, during reflow. In our previous study (Xie et al., 2007), this methodology was applied to a molded matrix array package, and an accelerated soak time subjected to 60degC / 60% RH was established. In this paper, the further reduction of soak time using 85degC / 60% RH is investigated. An ultra-thin stacked-die chip scale package (CSP) is used as the test vehicle. Extensive experiments have been carried out to obtain the failure rate as function of soak time under various environmental conditions. Finite element analysis was performed to obtain the equivalency conditions. According to finite element modeling results, it has been found that, at 70hrs under 60degC / 60% RH and 45 hrs under 85degC / 60% RH, respectively, both the local moisture concentration at critical interface and overall moisture distribution of package become identical to that under the standard MSL-3. Such an equivalency of the new accelerated test conditions has been proven by the test results. Failure site and failure mode indicates that the proposed accelerated tests are well correlated with the standard MSL-3. The new methodology can be extended to other packages.
{"title":"A new method for equivalent acceleration of JEDEC moisture sensitivity levels","authors":"D. Shi, Xuejun Fan, B. Xie","doi":"10.1109/ECTC.2008.4550084","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550084","url":null,"abstract":"In order to devise an equivalent accelerated moisture sensitivity test, the JEDEC specification J-STD-020C has recommended an accelerated preconditioning time of 40 hrs exposure under 60degC / 60% RH, which is considered equivalent to the standard moisture sensitivity level 3 (MSL-3) of 216 hrs soak time under 30degC / 60% RH. However, the existing methodology for the accelerated moisture sensitivity test was developed based on the equivalency of local moisture concentration at the interest of location for leaded packages only. The failure mechanism is restricted to the potential delamination between mold compound and leadframe. In addition, such an equivalency requires the activation energy of molding compound for moisture diffusion in the range of 0.4 - 0.48 eV. This paper introduces a new method to accelerate JEDEC/IPC moisture sensitivity level testing. The methodology is developed based on the equivalency of both local moisture concentration and overall moisture distribution of packages. The local moisture concentration equivalency ensures identical adhesion strength and vapor pressure at interfaces of the interest, and the overall moisture distribution equivalency results in the same condition of applied driving forces, such as thermal and hygroscopic stresses, during reflow. In our previous study (Xie et al., 2007), this methodology was applied to a molded matrix array package, and an accelerated soak time subjected to 60degC / 60% RH was established. In this paper, the further reduction of soak time using 85degC / 60% RH is investigated. An ultra-thin stacked-die chip scale package (CSP) is used as the test vehicle. Extensive experiments have been carried out to obtain the failure rate as function of soak time under various environmental conditions. Finite element analysis was performed to obtain the equivalency conditions. According to finite element modeling results, it has been found that, at 70hrs under 60degC / 60% RH and 45 hrs under 85degC / 60% RH, respectively, both the local moisture concentration at critical interface and overall moisture distribution of package become identical to that under the standard MSL-3. Such an equivalency of the new accelerated test conditions has been proven by the test results. Failure site and failure mode indicates that the proposed accelerated tests are well correlated with the standard MSL-3. The new methodology can be extended to other packages.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128202718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550263
Jang-Hee Lee, Gi-Tae Lim, Young-Bae Park, Seungtaek Yang, M. Suh, Q. Chung, Kwang-yoo Byun
To understand for size effect on electromigration behavior in flip chip Pb-free solder bump, electromigration tests were performed with change of pad open size and solder bump height at 140degC, 4.6times104 A/cm2. Electromigration lifetime increases with pad open size and bump height decreasing. In pad open size change, electromigration lifetime increase with pad open size increasing because applied current decrease with pad open size decreasing. In bump height change, electromigration resistance increase with bump height decreasing due to thermal gradient induced thermomigration effect decreasing. It seems to that electromigration resistance increase with size of solder bump decreasing.
{"title":"Size effect on electromigration reliability of pb-free flip chip solder bump","authors":"Jang-Hee Lee, Gi-Tae Lim, Young-Bae Park, Seungtaek Yang, M. Suh, Q. Chung, Kwang-yoo Byun","doi":"10.1109/ECTC.2008.4550263","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550263","url":null,"abstract":"To understand for size effect on electromigration behavior in flip chip Pb-free solder bump, electromigration tests were performed with change of pad open size and solder bump height at 140degC, 4.6times104 A/cm2. Electromigration lifetime increases with pad open size and bump height decreasing. In pad open size change, electromigration lifetime increase with pad open size increasing because applied current decrease with pad open size decreasing. In bump height change, electromigration resistance increase with bump height decreasing due to thermal gradient induced thermomigration effect decreasing. It seems to that electromigration resistance increase with size of solder bump decreasing.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131720396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550252
P. Nummila, M. Johansson, S. Puro
WLCSP, real wafer size package, usage has grown heavily during last years and volume is expected still to grow a lot. Main drivers for WLCSP usage are size and thickness reduction in portable devices and in some applications also price reduction by simplifying packaging structure. The main factor affecting these is reduction of component IO pitch. Growing usage volume has also increased the amount of WLCSP manufacturers, giving large variation of different package structures to the markets. As a consequence field of reliability is large, since different structures are behaving very differently especially under mechanical shock, which is considered to be most critical behavior of WLCSP packages in portable devices. However thermo-mechanical reliability should not be compromised either. Today there are many studies showing comparison of reliability test results between some factors, like dimensions. However from WLCSP end-user point of view whole system is more complex; there are several factors effecting to the overall mechanical and thermo-mechanical robustness of WLCSP packages, especially metallurgical factors play very remarkable role, including different underbump material and solder ball combinations. From WLCSP user point of view it is important to understand the variety of structures in the field and the complexity of factors effecting reliability in the area. Aim of the study is to increase knowledge of complexity of this area and factors effecting reliability of various WLCSP structures. As an introduction, data from last years WLCSP volumes in Nokia portable devices will be shown, together with an estimate of further usage volume. Overview of most common WLCSP structures will be presented, to give an overview of variety of different structures in the field. Reliability test results of mechanical shock will be presented and different package types and bump pitches will be compared. Also "weak links" between different package types will be compared, in terms of failure analysis results. As a conclusion there will be discussion of pros and cons of different package types, there is also not only one correct type to be used but several possibly good ones, defined also by electrical design.
{"title":"Mechanical shock robustness of different WLCSP types","authors":"P. Nummila, M. Johansson, S. Puro","doi":"10.1109/ECTC.2008.4550252","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550252","url":null,"abstract":"WLCSP, real wafer size package, usage has grown heavily during last years and volume is expected still to grow a lot. Main drivers for WLCSP usage are size and thickness reduction in portable devices and in some applications also price reduction by simplifying packaging structure. The main factor affecting these is reduction of component IO pitch. Growing usage volume has also increased the amount of WLCSP manufacturers, giving large variation of different package structures to the markets. As a consequence field of reliability is large, since different structures are behaving very differently especially under mechanical shock, which is considered to be most critical behavior of WLCSP packages in portable devices. However thermo-mechanical reliability should not be compromised either. Today there are many studies showing comparison of reliability test results between some factors, like dimensions. However from WLCSP end-user point of view whole system is more complex; there are several factors effecting to the overall mechanical and thermo-mechanical robustness of WLCSP packages, especially metallurgical factors play very remarkable role, including different underbump material and solder ball combinations. From WLCSP user point of view it is important to understand the variety of structures in the field and the complexity of factors effecting reliability in the area. Aim of the study is to increase knowledge of complexity of this area and factors effecting reliability of various WLCSP structures. As an introduction, data from last years WLCSP volumes in Nokia portable devices will be shown, together with an estimate of further usage volume. Overview of most common WLCSP structures will be presented, to give an overview of variety of different structures in the field. Reliability test results of mechanical shock will be presented and different package types and bump pitches will be compared. Also \"weak links\" between different package types will be compared, in terms of failure analysis results. As a conclusion there will be discussion of pros and cons of different package types, there is also not only one correct type to be used but several possibly good ones, defined also by electrical design.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134221278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550191
U. Ozkan, H. F. Nied
Interface delamination phenomenon has been a great concern for semiconductor package reliability. In order to better understand the package failure mechanisms, crack initiation and propagation behavior of interface flaws have to be investigated in detail. In this paper, three dimensional interface crack propagation is examined using the enriched finite element method. A fatigue crack growth simulation technique, which has been widely studied in the literature to predict steady state crack growth behavior after crack initiation in homogeneous materials, is extended to three dimensional interface cracks. The method described uses a modified version of the classical fatigue crack growth rate "law" developed by Paris and Erdogan to simulate stable crack growth under cyclic loading conditions, with the crack constrained to the plane of the interface. The crack driving force, which is chosen as cyclic strain energy release rate, is calculated using the enriched finite element method. As a practical example in semiconductor package reliability analysis, the method is used to simulate the propagation of a three-dimensional interface crack on a silicon/epoxy interface under various loading conditions. Plots of advancement of the crack front and the changes in total strain energy release rates as the crack shape evolves during propagation are also given. Lastly, crack propagation simulation is demonstrated for a generic package model using a submodeling technique.
{"title":"Finite element based three dimensional crack propagation simulation on interfaces in electronic packages","authors":"U. Ozkan, H. F. Nied","doi":"10.1109/ECTC.2008.4550191","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550191","url":null,"abstract":"Interface delamination phenomenon has been a great concern for semiconductor package reliability. In order to better understand the package failure mechanisms, crack initiation and propagation behavior of interface flaws have to be investigated in detail. In this paper, three dimensional interface crack propagation is examined using the enriched finite element method. A fatigue crack growth simulation technique, which has been widely studied in the literature to predict steady state crack growth behavior after crack initiation in homogeneous materials, is extended to three dimensional interface cracks. The method described uses a modified version of the classical fatigue crack growth rate \"law\" developed by Paris and Erdogan to simulate stable crack growth under cyclic loading conditions, with the crack constrained to the plane of the interface. The crack driving force, which is chosen as cyclic strain energy release rate, is calculated using the enriched finite element method. As a practical example in semiconductor package reliability analysis, the method is used to simulate the propagation of a three-dimensional interface crack on a silicon/epoxy interface under various loading conditions. Plots of advancement of the crack front and the changes in total strain energy release rates as the crack shape evolves during propagation are also given. Lastly, crack propagation simulation is demonstrated for a generic package model using a submodeling technique.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"155 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133039639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550260
Yuquan Li, R.W. Johnson, P. Thompson, T. Hooghan, J. Libres
Copper heat spreaders are often used in flip chip in package construction. While providing high thermal conductivity, Cu has a significantly higher coefficient of thermal expansion than Si. In this work, two heat spreader attachment materials, indium for high power and polymeric adhesive for medium power applications, have been investigated. For In solder based attach, the Cu heat spreader was metallized with Ni/Au. Two thin film metallizations, Ti/Ni/Au and Ti/Au, have been studied for the Si backside. A nearly void free heat spreader attach has been achieved with vacuum soldering. For Ti/Ni/Au backside metallized Si die, there was no significant shear strength change after 1000 hours aging at 120degC and there was no significant shear or pull strength variation after five lead free re flow cycles. The shear and pull failure mode was within the indium layer. For Ti/Au die backside metallization, the initial die pull strength and failure mode were a function of Au thickness. With 3000 A of Au, there is no significant variation for shear and pull strength after 600 hours aging at 120degC or after five lead free solder reflow cycles. Failure was in the indium layer. For both types of die metallization, 24 mm times 24 mm Cu heat spreaders assembled on 22 mm times 22 mm Si die, exhibited no delamination after two lead free solder reflow cycles followed by 500 air to air thermal shock cycles (-40degC to 85degC). At 1000 cycles, slight delamination was found at the edges of the assembly for both die metallurgies. For adhesive based flat heat spreader attachment, a thermally conductive adhesive was used as the thermal interface and a non-thermally conductive adhesive was applied at the substrate corners to provide mechanical reinforcement of the heat spreader. After pre-conditioning then aging at 100degC for 500 hours followed by 500 air-to-air thermal shock cycles (0degC to 100degC), no delamination was observed and there was no significant degradation in pull strength.
{"title":"Reliability of flip chip packages with high thermal conductivity heat spreader attach","authors":"Yuquan Li, R.W. Johnson, P. Thompson, T. Hooghan, J. Libres","doi":"10.1109/ECTC.2008.4550260","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550260","url":null,"abstract":"Copper heat spreaders are often used in flip chip in package construction. While providing high thermal conductivity, Cu has a significantly higher coefficient of thermal expansion than Si. In this work, two heat spreader attachment materials, indium for high power and polymeric adhesive for medium power applications, have been investigated. For In solder based attach, the Cu heat spreader was metallized with Ni/Au. Two thin film metallizations, Ti/Ni/Au and Ti/Au, have been studied for the Si backside. A nearly void free heat spreader attach has been achieved with vacuum soldering. For Ti/Ni/Au backside metallized Si die, there was no significant shear strength change after 1000 hours aging at 120degC and there was no significant shear or pull strength variation after five lead free re flow cycles. The shear and pull failure mode was within the indium layer. For Ti/Au die backside metallization, the initial die pull strength and failure mode were a function of Au thickness. With 3000 A of Au, there is no significant variation for shear and pull strength after 600 hours aging at 120degC or after five lead free solder reflow cycles. Failure was in the indium layer. For both types of die metallization, 24 mm times 24 mm Cu heat spreaders assembled on 22 mm times 22 mm Si die, exhibited no delamination after two lead free solder reflow cycles followed by 500 air to air thermal shock cycles (-40degC to 85degC). At 1000 cycles, slight delamination was found at the edges of the assembly for both die metallurgies. For adhesive based flat heat spreader attachment, a thermally conductive adhesive was used as the thermal interface and a non-thermally conductive adhesive was applied at the substrate corners to provide mechanical reinforcement of the heat spreader. After pre-conditioning then aging at 100degC for 500 hours followed by 500 air-to-air thermal shock cycles (0degC to 100degC), no delamination was observed and there was no significant degradation in pull strength.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124301922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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