Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550041
E. Liu, Xingchang Wei, Z. Oo, E. Li
A two-dimensional full-wave method is presented in this paper for efficient power integrity and EMI Analysis of highspeed electronic packages. The power/ground planes in electronic packages form a parallel-plate structure, which is solved by a 2D finite-different time domain (2D FDTD) method. Both the conductor loss and the substrate loss are modeled by the 2D method. Besides the parallel-plate structure, electronic packages also comprise of many transmission lines including microstrip- and stripline-type structures. Those two types of structures are also resolved by the 2D method. So a unified solver may be developed in the context of 2D method for the signal and power integrity analysis of electronic packages. The electromagnetic interference (EMI) issue of electronic packages is also touched in this paper, which is mainly focused on the radiation due to the edge effect of the parallel plate structure in a package. Numerical examples are given to demonstrate the method.
{"title":"An efficient method for power integrity and EMI Analysis of advanced packages","authors":"E. Liu, Xingchang Wei, Z. Oo, E. Li","doi":"10.1109/ECTC.2008.4550041","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550041","url":null,"abstract":"A two-dimensional full-wave method is presented in this paper for efficient power integrity and EMI Analysis of highspeed electronic packages. The power/ground planes in electronic packages form a parallel-plate structure, which is solved by a 2D finite-different time domain (2D FDTD) method. Both the conductor loss and the substrate loss are modeled by the 2D method. Besides the parallel-plate structure, electronic packages also comprise of many transmission lines including microstrip- and stripline-type structures. Those two types of structures are also resolved by the 2D method. So a unified solver may be developed in the context of 2D method for the signal and power integrity analysis of electronic packages. The electromagnetic interference (EMI) issue of electronic packages is also touched in this paper, which is mainly focused on the radiation due to the edge effect of the parallel plate structure in a package. Numerical examples are given to demonstrate the method.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122825585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550101
E. Wolak, K. Kuppuswamy, J. Harrison, Xu Jin, Hanxuan Li, B. Fidric, R. Miller, P. Cross, T. Towe, T. Truchan, Hoa Nguyen, C. Edirisinghe
This paper describes reliability data for multi-stripe arrays of laser diodes with limited emitter count. The empirical behavior of these arrays is compared with a model based on independent random failures of the individual stripes in a multi-element array operating in an ensemble mode. Such reliability data is of particular interest for multi-mode multi- stripe laser pump modules operating in the 910 nm to 990 nm wavelength range.
{"title":"Highly reliable multi stripe laser diodes","authors":"E. Wolak, K. Kuppuswamy, J. Harrison, Xu Jin, Hanxuan Li, B. Fidric, R. Miller, P. Cross, T. Towe, T. Truchan, Hoa Nguyen, C. Edirisinghe","doi":"10.1109/ECTC.2008.4550101","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550101","url":null,"abstract":"This paper describes reliability data for multi-stripe arrays of laser diodes with limited emitter count. The empirical behavior of these arrays is compared with a model based on independent random failures of the individual stripes in a multi-element array operating in an ensemble mode. Such reliability data is of particular interest for multi-mode multi- stripe laser pump modules operating in the 910 nm to 990 nm wavelength range.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126820713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550172
Sungwon Han, Kyung-Seob Kim, Chung-Hee Yu, M. Osterman, M. Pecht
This study evaluated the growth of tin whiskers on tin plated alloy 42 lead-frames and copper lead-frames stored in ambient conditions for 4 years, samples stored in ambient conditions after a post-bake treatment, and stored at 55plusmn1degC/85plusmn3% conditions for 3000 hours. Analysis was conducted to investigate the propensity and the mechanisms of growth.
{"title":"Observations of the spontaneous growth of tin whiskers in various reliability conditions","authors":"Sungwon Han, Kyung-Seob Kim, Chung-Hee Yu, M. Osterman, M. Pecht","doi":"10.1109/ECTC.2008.4550172","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550172","url":null,"abstract":"This study evaluated the growth of tin whiskers on tin plated alloy 42 lead-frames and copper lead-frames stored in ambient conditions for 4 years, samples stored in ambient conditions after a post-bake treatment, and stored at 55plusmn1degC/85plusmn3% conditions for 3000 hours. Analysis was conducted to investigate the propensity and the mechanisms of growth.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125892642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550193
S. Hwang, J. Lim, B. Rho
Our suggested VCSEL array optical subassembly (OSA) for 120 Gb/s-level parallel optical interconnect modules was composed of a 12 channel VCSEL array chip, a SiOB, two silicon spacers, and a molded microlens with accurate guide pin holes. For high speed operation above 10 Gb/s per a channel, we carefully designed transmission lines on the SiOB. The results of the transmission lines were measured as large bandwidth more than 26 GHz and low channel crosstalk less than -30 dB. And, to achieve high coupling efficiency, the planar-convex microlens was adopted. The average coupling efficiency coupled to 62.5 mum multi-mode fiber (MMF) ribbon was approximately 85%, the value of which means nothing but material loss itself. In this paper, the fabrication process of the VCSEL OSA is emphasized on low cost packaging. In particular, a suggested passive alignment technique is described in detail to align both the VCSEL and the microlens array. An accurate assembly in this work was carried out through vision alignment using 2-sight camera of a precise pick-and-place machine, Suss MicroTec TRIAD 05 flip-chip bonder. To evaluate the DC and AC characteristics of the completely fabricated VCSEL array OSA, we measured optical output powers (L-I-V curve) and 4.25 Gb/s, 6 Gb/s, 10.31 Gb/s eye-diagrams on condition of setting-up with MT ferrule terminated 12 channel 62.5 mum MMF and a G-S-G probe. We successfully demonstrated high speed and high efficient VCSEL array OSA with clear 10.31 Gb/s eye diagrams and low coupling loss.
{"title":"120 Gb/s-level VCSEL array optical subassembly using passive alignment technique","authors":"S. Hwang, J. Lim, B. Rho","doi":"10.1109/ECTC.2008.4550193","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550193","url":null,"abstract":"Our suggested VCSEL array optical subassembly (OSA) for 120 Gb/s-level parallel optical interconnect modules was composed of a 12 channel VCSEL array chip, a SiOB, two silicon spacers, and a molded microlens with accurate guide pin holes. For high speed operation above 10 Gb/s per a channel, we carefully designed transmission lines on the SiOB. The results of the transmission lines were measured as large bandwidth more than 26 GHz and low channel crosstalk less than -30 dB. And, to achieve high coupling efficiency, the planar-convex microlens was adopted. The average coupling efficiency coupled to 62.5 mum multi-mode fiber (MMF) ribbon was approximately 85%, the value of which means nothing but material loss itself. In this paper, the fabrication process of the VCSEL OSA is emphasized on low cost packaging. In particular, a suggested passive alignment technique is described in detail to align both the VCSEL and the microlens array. An accurate assembly in this work was carried out through vision alignment using 2-sight camera of a precise pick-and-place machine, Suss MicroTec TRIAD 05 flip-chip bonder. To evaluate the DC and AC characteristics of the completely fabricated VCSEL array OSA, we measured optical output powers (L-I-V curve) and 4.25 Gb/s, 6 Gb/s, 10.31 Gb/s eye-diagrams on condition of setting-up with MT ferrule terminated 12 channel 62.5 mum MMF and a G-S-G probe. We successfully demonstrated high speed and high efficient VCSEL array OSA with clear 10.31 Gb/s eye diagrams and low coupling loss.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114419639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550218
J. Chandrasekhar, E. Engin, M. Swaminathan, K. Uriu, T. Yamada
Differential lines are extensively used in high-speed digital circuits due to their ability to improve signal integrity by rejecting common-mode noise. However noise is injected into differential signals when there are irregularities in the signaling setup. These anomalies may be via transitions of differential lines through power planes in power distribution systems, via stubs, asymmetric lengths of differential lines, different transition points for each of the differential vias etc. This paper quantifies noise due to irregular differential structures in frequency domain. Presence of noise in differential signaling is verified through a set of test vehicles. The effect of signal to power coupling from differential lines on signal jitter is also investigated.
{"title":"Noise induced jitter in differential signaling","authors":"J. Chandrasekhar, E. Engin, M. Swaminathan, K. Uriu, T. Yamada","doi":"10.1109/ECTC.2008.4550218","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550218","url":null,"abstract":"Differential lines are extensively used in high-speed digital circuits due to their ability to improve signal integrity by rejecting common-mode noise. However noise is injected into differential signals when there are irregularities in the signaling setup. These anomalies may be via transitions of differential lines through power planes in power distribution systems, via stubs, asymmetric lengths of differential lines, different transition points for each of the differential vias etc. This paper quantifies noise due to irregular differential structures in frequency domain. Presence of noise in differential signaling is verified through a set of test vehicles. The effect of signal to power coupling from differential lines on signal jitter is also investigated.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122828099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550046
A. Kundu, M. Megahed, D. Schmidt
We have investigated the existing integrated passive device (IPD) technologies for cost effective IPD solutions for discrete radio frequency (RF) module. Based upon the investigation in terms of cost, size, performance & technology maturity, it comes out that silicon, glass & LTCC are the suitable technologies. We have designed IPDs using these technologies having same foot print to satisfy Intel Wi-MAX specs. Have taped out, validated the samples and made an electrical performance and cost comparison among three technologies. Result shows that Si_IPD & Glass_IPD both have well enough electrical performance required for Wi_MAX solution at lower cost and equivalent size compared to LTCC.
{"title":"Comparison and analysis of integrated passive device technologies for wireless radio frequency module","authors":"A. Kundu, M. Megahed, D. Schmidt","doi":"10.1109/ECTC.2008.4550046","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550046","url":null,"abstract":"We have investigated the existing integrated passive device (IPD) technologies for cost effective IPD solutions for discrete radio frequency (RF) module. Based upon the investigation in terms of cost, size, performance & technology maturity, it comes out that silicon, glass & LTCC are the suitable technologies. We have designed IPDs using these technologies having same foot print to satisfy Intel Wi-MAX specs. Have taped out, validated the samples and made an electrical performance and cost comparison among three technologies. Result shows that Si_IPD & Glass_IPD both have well enough electrical performance required for Wi_MAX solution at lower cost and equivalent size compared to LTCC.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121086840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550110
Jinseong Kim, Kiwook Lee, Dongjoo Park, Taekyung Hwang, Kwangho Kim, Daebyoung Kang, Jaedong Kim, Choonheung Lee, C. Scanlan, C. Berry, C. Zwenger, L. Smith, M. Dreiza, R. Darveaux
In recent years, package-on-package (PoP) has been rapidly adopted for 3D integration of logic and memory within mobile handsets and other portable multimedia devices. However, existing methods of making the PoP base package may not satisfy next generation applications that will require reduced memory interface pitches, higher memory interface pin-counts, reduced thickness, tight warpage control and higher levels of integration within the PoP base package. This paper introduces a new PoP base package structure that addresses the challenges of next generation applications. A PoP base package with through mold vias (TMV) will be described. Package flatness and package stacking results will be presented and advantages of TMV technology will be reviewed.
{"title":"Application of through mold via (TMV) as PoP base package","authors":"Jinseong Kim, Kiwook Lee, Dongjoo Park, Taekyung Hwang, Kwangho Kim, Daebyoung Kang, Jaedong Kim, Choonheung Lee, C. Scanlan, C. Berry, C. Zwenger, L. Smith, M. Dreiza, R. Darveaux","doi":"10.1109/ECTC.2008.4550110","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550110","url":null,"abstract":"In recent years, package-on-package (PoP) has been rapidly adopted for 3D integration of logic and memory within mobile handsets and other portable multimedia devices. However, existing methods of making the PoP base package may not satisfy next generation applications that will require reduced memory interface pitches, higher memory interface pin-counts, reduced thickness, tight warpage control and higher levels of integration within the PoP base package. This paper introduces a new PoP base package structure that addresses the challenges of next generation applications. A PoP base package with through mold vias (TMV) will be described. Package flatness and package stacking results will be presented and advantages of TMV technology will be reviewed.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126538513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4549993
M. Ahmad, K.C. Liu, C.J. Lee, J. Priest, S. Pak, S. Narasimhan, M. Nagar, J. Xue
A custom SRAM was developed for high performance and high reliability network switching applications using 90 nm low-k silicon technology. It is a 13.6 mm x 18.4 mm flip chip chip scale package (CSP) with a 11.12 mm x 16.36 mm die. The package has 838 BGA balls at 0.5 mm pitch. The 0.5 mm ball pitch CSP minimizes electrical package parasitics and enables higher data rate performance. However, the high aspect ratio of the die-to-package area leaves very little room for underfill dispensing and no room for a stiffener ring attachment. In addition, the high heat dissipation of the device requires the use of a metal heatspreader flip chip package as opposed to an overmolded flip chip package solution. The package design coupled with a large die and high I/O count presents significant challenges in the package assembly process and interconnect reliability. A lower glass transition (Tg) underfill material is typically preferred to reduce package warpage and to reduce the stress in the low-k dielectric caused by CTE mismatch between the silicon die and package materials. However, for high power applications where the operating temperature is very close to the underfill Tg, the system level thermal solution must be optimized for improved cooling while at the same time ensuring that the interconnect and package reliability at the system application level is not compromised. In this paper, both Experimental and Finite Element analyses were performed to investigate the key system level thermal solution design parameters that impact package interconnect reliability. The effect of heatsink compressive loading on the thermal excursions, the underfill material, and the interconnect metallurgy was evaluated. In addition to the compressive loading effect, the effect of the heatsink attachment method on interconnect reliability was also investigated. Three dimensional fatigue analyses were performed to derive the hysteresis loops for different test cases, to understand the interaction between the heatsink attachment method and the package material and design variables. The finite element model data was benchmarked against experimental data to determine the optimal design conditions for effective thermal cooling without compromising interconnect reliability. Real time pressure measurement and failure analysis were also performed to understand the potential failure modes and failure rates occurring in the system level design. Finally, recommendations are provided on ways to mitigate critical failure modes in the thermal and interconnect design of such complex flip chip CSP packages at the system level.
{"title":"Impact of system level thermal solution on the interconnect reliability of high performance and high heat dissipating CSP package","authors":"M. Ahmad, K.C. Liu, C.J. Lee, J. Priest, S. Pak, S. Narasimhan, M. Nagar, J. Xue","doi":"10.1109/ECTC.2008.4549993","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4549993","url":null,"abstract":"A custom SRAM was developed for high performance and high reliability network switching applications using 90 nm low-k silicon technology. It is a 13.6 mm x 18.4 mm flip chip chip scale package (CSP) with a 11.12 mm x 16.36 mm die. The package has 838 BGA balls at 0.5 mm pitch. The 0.5 mm ball pitch CSP minimizes electrical package parasitics and enables higher data rate performance. However, the high aspect ratio of the die-to-package area leaves very little room for underfill dispensing and no room for a stiffener ring attachment. In addition, the high heat dissipation of the device requires the use of a metal heatspreader flip chip package as opposed to an overmolded flip chip package solution. The package design coupled with a large die and high I/O count presents significant challenges in the package assembly process and interconnect reliability. A lower glass transition (Tg) underfill material is typically preferred to reduce package warpage and to reduce the stress in the low-k dielectric caused by CTE mismatch between the silicon die and package materials. However, for high power applications where the operating temperature is very close to the underfill Tg, the system level thermal solution must be optimized for improved cooling while at the same time ensuring that the interconnect and package reliability at the system application level is not compromised. In this paper, both Experimental and Finite Element analyses were performed to investigate the key system level thermal solution design parameters that impact package interconnect reliability. The effect of heatsink compressive loading on the thermal excursions, the underfill material, and the interconnect metallurgy was evaluated. In addition to the compressive loading effect, the effect of the heatsink attachment method on interconnect reliability was also investigated. Three dimensional fatigue analyses were performed to derive the hysteresis loops for different test cases, to understand the interaction between the heatsink attachment method and the package material and design variables. The finite element model data was benchmarked against experimental data to determine the optimal design conditions for effective thermal cooling without compromising interconnect reliability. Real time pressure measurement and failure analysis were also performed to understand the potential failure modes and failure rates occurring in the system level design. Finally, recommendations are provided on ways to mitigate critical failure modes in the thermal and interconnect design of such complex flip chip CSP packages at the system level.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126626907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550153
M. Rowlands, R. Das
We have designed and built a LCP-based flip-chip package using Z-interconnect building blocks for reliability and electrical performance. Manufacturing a Z-interconnect substrate involves building mini-substrates (sub-composites) of 2 or 3 layers each, then assembling several mini-substrates together to make the finished product. "Z-interconnect" is used to connect metal layers vertically, using a conductive adhesive. Z-axis interconnection was achieved using joining cores. Through holes in the joining cores, formed by laser drilling and having diameters 60 microns, were filled with an optimized, electrically conductive adhesive. The adhesive- filled joining cores were laminated with circuitized sub- composites to produce a composite structure. High temperature lamination was used to cure the adhesive in the composite and provide Z-interconnection among the circuitized sub-composites. Designing and manufacturing the mini-substrates separately makes it possible to reliably manufacture substrates with no via stubs, very low-loss materials, nearly arbitrary transmission line structures and lots of flexibility to tune features to reduce signal loss. Here we are using 5 sub-composites with 16 metal layers , including 3 0S2P joining cores, 2 2S2P signals cores, plated copper on top and bottom and embedded resistance on layer 7. Each sub-composite (0S2P/2S2P) made with high and low melting point LCP. There was no de-lamination of conductive adhesive filled LCP samples after pressure cooker test (PCT), and solder shock. Evaluation criteria for the test vehicle will include its ability to perform as a reliable, manufacturable, high-performance substrate. Results will be compared to typical ceramic and PTFE chip packages and the improvements over ceramic will be noted.
{"title":"Manufacture and ultra-high frequency performance of an LCP-based, Z-interconnect, flip-chip package","authors":"M. Rowlands, R. Das","doi":"10.1109/ECTC.2008.4550153","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550153","url":null,"abstract":"We have designed and built a LCP-based flip-chip package using Z-interconnect building blocks for reliability and electrical performance. Manufacturing a Z-interconnect substrate involves building mini-substrates (sub-composites) of 2 or 3 layers each, then assembling several mini-substrates together to make the finished product. \"Z-interconnect\" is used to connect metal layers vertically, using a conductive adhesive. Z-axis interconnection was achieved using joining cores. Through holes in the joining cores, formed by laser drilling and having diameters 60 microns, were filled with an optimized, electrically conductive adhesive. The adhesive- filled joining cores were laminated with circuitized sub- composites to produce a composite structure. High temperature lamination was used to cure the adhesive in the composite and provide Z-interconnection among the circuitized sub-composites. Designing and manufacturing the mini-substrates separately makes it possible to reliably manufacture substrates with no via stubs, very low-loss materials, nearly arbitrary transmission line structures and lots of flexibility to tune features to reduce signal loss. Here we are using 5 sub-composites with 16 metal layers , including 3 0S2P joining cores, 2 2S2P signals cores, plated copper on top and bottom and embedded resistance on layer 7. Each sub-composite (0S2P/2S2P) made with high and low melting point LCP. There was no de-lamination of conductive adhesive filled LCP samples after pressure cooker test (PCT), and solder shock. Evaluation criteria for the test vehicle will include its ability to perform as a reliable, manufacturable, high-performance substrate. Results will be compared to typical ceramic and PTFE chip packages and the improvements over ceramic will be noted.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127502293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550235
J. Liao, Shengling Deng, K. Connor, V. Joyner, Z.R. Huang
In this paper, a dual split director quasi-yagi antenna is introduced for RF/FSO integration. Bare die laser diodes and photodetectors are assembled on the antenna directors on the duroid substrate. Coupling between RF and optical dual mode wireless communication system is analyzed.
{"title":"Antenna integration with laser diodes and photodetectors for a miniaturized dual-mode wireless transceiver","authors":"J. Liao, Shengling Deng, K. Connor, V. Joyner, Z.R. Huang","doi":"10.1109/ECTC.2008.4550235","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550235","url":null,"abstract":"In this paper, a dual split director quasi-yagi antenna is introduced for RF/FSO integration. Bare die laser diodes and photodetectors are assembled on the antenna directors on the duroid substrate. Coupling between RF and optical dual mode wireless communication system is analyzed.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131303784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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