Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4549947
G. White, S. Dalmia, L. Carastro, C. Russell, V. Sundaram, M. Swaminathan
This paper presents for the first time a new paradigm in the construction of multilayer RF, digital and mixed signal circuits using conventional low-loss organic laminates. The new process termed low temperature laminated organics, LTLOtrade [1], is a multilayer parallel process where individual layers are circuitized, tested and co-laminated at temperatures below 280degC to form a multilayer structure. Both stacked and staggered via structures have been realized with LTLO, thereby allowing for the realization of any layer, and any via interconnection schemes. The LTLO technology also facilitates the introduction of embedded active and passive components allowing for true 3D package integration. To date up to 24 metal layers have been demonstrated using LTLO.
{"title":"A novel methodology (Low Temperature Laminated Organics) for 3D integration using multilayer organics","authors":"G. White, S. Dalmia, L. Carastro, C. Russell, V. Sundaram, M. Swaminathan","doi":"10.1109/ECTC.2008.4549947","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4549947","url":null,"abstract":"This paper presents for the first time a new paradigm in the construction of multilayer RF, digital and mixed signal circuits using conventional low-loss organic laminates. The new process termed low temperature laminated organics, LTLOtrade [1], is a multilayer parallel process where individual layers are circuitized, tested and co-laminated at temperatures below 280degC to form a multilayer structure. Both stacked and staggered via structures have been realized with LTLO, thereby allowing for the realization of any layer, and any via interconnection schemes. The LTLO technology also facilitates the introduction of embedded active and passive components allowing for true 3D package integration. To date up to 24 metal layers have been demonstrated using LTLO.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123187874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550183
B. Majeed, N. Pham, D. Tezcan, E. Beyne
This paper reports on the feasibility of parylene N as a dielectric material for through silicon vias (TSV). TSV are the key enabling technology for 3D wafer laver packaging. Parylene is used as an insulating material in one of the approaches adopted for realizing 3D wafer level packaging at IMEC. This paper discusses main issues regarding the processing of parylene N for the TSV application. First, the thickness uniformity of as-deposited parylene across the wafer and inside the via is investigated. The results show that for 200 mm wafers, within-wafer and wafer-to-wafer thickness is sufficiently uniform. The 1-sigma thickness variation of less than 4 percent for both cases is measured. 1 sigma thickness variation of less than 5 percent is observed from batch to batch. Second, the effect of substrate, temporary glue layer and carrier wafer for thinned device wafers on the dry etching of parylene is analyzed. The experiments show that the etching was sufficiently uniform across the wafer; and the uniformity across the surface is recorded to be greater than 95 percent. There is no considerable effect of substrate or bonding layer thickness, however carrier wafer influence the etching rate.
{"title":"Parylene N as a dielectric material for through silicon vias","authors":"B. Majeed, N. Pham, D. Tezcan, E. Beyne","doi":"10.1109/ECTC.2008.4550183","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550183","url":null,"abstract":"This paper reports on the feasibility of parylene N as a dielectric material for through silicon vias (TSV). TSV are the key enabling technology for 3D wafer laver packaging. Parylene is used as an insulating material in one of the approaches adopted for realizing 3D wafer level packaging at IMEC. This paper discusses main issues regarding the processing of parylene N for the TSV application. First, the thickness uniformity of as-deposited parylene across the wafer and inside the via is investigated. The results show that for 200 mm wafers, within-wafer and wafer-to-wafer thickness is sufficiently uniform. The 1-sigma thickness variation of less than 4 percent for both cases is measured. 1 sigma thickness variation of less than 5 percent is observed from batch to batch. Second, the effect of substrate, temporary glue layer and carrier wafer for thinned device wafers on the dry etching of parylene is analyzed. The experiments show that the etching was sufficiently uniform across the wafer; and the uniformity across the surface is recorded to be greater than 95 percent. There is no considerable effect of substrate or bonding layer thickness, however carrier wafer influence the etching rate.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123312818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550078
O. Lühn, A. Radisic, P. Vereecken, B. Swinnen, C. Hoof, W. Ruythooren, J. Celis
We present two approaches to reduce the process time needed for filling vias of 5 mum diameter and 25 mum depth with copper by electrodeposition. In the first approach, the effect of model additives on the filling of vias with electroplated copper was investigated as well as the influence of the applied current density on the filling process. The variation of the concentration of leveler and accelerator additives was investigated. Their influence on the void-free filling of such vias was determined. A high leveler concentration allowed to achieve a void-free fill. The copper deposited on the top surface was in the range of 2.5 mum. The filling was completed within 45 minutes. The filling time could even be further reduced to 25 minutes by introducing a waveform with two galvanostatic steps. The second approach demonstrates void-free via filling with copper electrodeposition at the top of the wafer surface blocked with self-assembled monolayers of octadecanethiol. With thin Ta-films deposited at the top surface before electrodeposition is started, almost no copper was deposited at the top surface as well. The vias were filled within 30 minutes when the top surface was completely blocked.
{"title":"Reducing the electrodeposition time for filling microvias with copper for 3D technology","authors":"O. Lühn, A. Radisic, P. Vereecken, B. Swinnen, C. Hoof, W. Ruythooren, J. Celis","doi":"10.1109/ECTC.2008.4550078","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550078","url":null,"abstract":"We present two approaches to reduce the process time needed for filling vias of 5 mum diameter and 25 mum depth with copper by electrodeposition. In the first approach, the effect of model additives on the filling of vias with electroplated copper was investigated as well as the influence of the applied current density on the filling process. The variation of the concentration of leveler and accelerator additives was investigated. Their influence on the void-free filling of such vias was determined. A high leveler concentration allowed to achieve a void-free fill. The copper deposited on the top surface was in the range of 2.5 mum. The filling was completed within 45 minutes. The filling time could even be further reduced to 25 minutes by introducing a waveform with two galvanostatic steps. The second approach demonstrates void-free via filling with copper electrodeposition at the top of the wafer surface blocked with self-assembled monolayers of octadecanethiol. With thin Ta-films deposited at the top surface before electrodeposition is started, almost no copper was deposited at the top surface as well. The vias were filled within 30 minutes when the top surface was completely blocked.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"517 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123104666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4549978
A. Suzuki, T. Ishikawa, Y. Wakazono, D. Nagao, T. Hino, Y. Hashimoto, H. Masuda, S. Suzuki, M. Tamura, T.-i. Suzuki, K. Kikuchi, Y. Okada, H. Nakagawa, M. Aoyaghi, T. Mikawa
We demonstrate 10-Gb/s/ch operations of high-density, low-cost 12-channel optical modules for optical interconnections. These optical modules that we developed are designed to be pluggable into cards with an electrical connector. These pluggable modules will enable cards to be manufactured much more easily since they allow the manufacturing processes of optical modules and cards to be separated. An electrical connector with a clamp spring is used to connect a ceramic substrate with a printed circuit board (PCB). An anisotropic conductive film (ACF) is used to transmit electrical signals between the ceramic substrate and the PCB. To achieve optical coupling, optical fibers are butt-coupled with optical devices mounted in a cavity on the ceramic substrate. Alignment between the twelve optical fibers and the 12-channel optical device is achieved using guide pins fabricated in the ceramic substrate and guide holes fabricated in the optical connector.
{"title":"10-Gb/s × 12-ch downsized optical modules with electrical conductive film connector","authors":"A. Suzuki, T. Ishikawa, Y. Wakazono, D. Nagao, T. Hino, Y. Hashimoto, H. Masuda, S. Suzuki, M. Tamura, T.-i. Suzuki, K. Kikuchi, Y. Okada, H. Nakagawa, M. Aoyaghi, T. Mikawa","doi":"10.1109/ECTC.2008.4549978","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4549978","url":null,"abstract":"We demonstrate 10-Gb/s/ch operations of high-density, low-cost 12-channel optical modules for optical interconnections. These optical modules that we developed are designed to be pluggable into cards with an electrical connector. These pluggable modules will enable cards to be manufactured much more easily since they allow the manufacturing processes of optical modules and cards to be separated. An electrical connector with a clamp spring is used to connect a ceramic substrate with a printed circuit board (PCB). An anisotropic conductive film (ACF) is used to transmit electrical signals between the ceramic substrate and the PCB. To achieve optical coupling, optical fibers are butt-coupled with optical devices mounted in a cavity on the ceramic substrate. Alignment between the twelve optical fibers and the 12-channel optical device is achieved using guide pins fabricated in the ceramic substrate and guide holes fabricated in the optical connector.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122267621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550103
J. Ong, A. Tay, X. Zhang, V. Kripesh, Y. K. Lim, J.B. Tan, D. Sohn
The trend toward finer pitch and higher performance integrated circuits (ICs) devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. However, the low-k materials have lower modulus and poorer adhesion compared to the common dielectric materials. Thus, thermo-mechanical failure is one of the major bottlenecks for development of fine-pitch, large-die Cu/low-k flip chip packages. In this paper, 3D finite element analyses were performed to investigate the reliability of 65 nm, 21times21 mm 9metal Cu/ low-k, chips with 150 mum interconnect pitch in a FCBGA package with a 750 mum die thickness and 1.0 mm substrate thickness. Three parametric cases involving different geometries of solder joints were analyze: (A) All 20 rows with spherical solder joints, (B) 10 hourglass joints followed by 10 spherical joints, and (C) 10 spherical joints followed by 10 hourglass joints. The spherical joints are stiffer than the hourglass joints. It was found that Case C gave the lowest inelastic energy dissipation (DeltaW) for the critical solder joint implying that Case C will have the longest fatigue life. It was also found that Case C gave the lowest maximum stress in the low-k material and it was further shown that reliability will be enhanced with decrease in die thickness and substrate thickness.
{"title":"Optimization of reliability of copper-low-k flip chip package with variable interconnect compliance","authors":"J. Ong, A. Tay, X. Zhang, V. Kripesh, Y. K. Lim, J.B. Tan, D. Sohn","doi":"10.1109/ECTC.2008.4550103","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550103","url":null,"abstract":"The trend toward finer pitch and higher performance integrated circuits (ICs) devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. However, the low-k materials have lower modulus and poorer adhesion compared to the common dielectric materials. Thus, thermo-mechanical failure is one of the major bottlenecks for development of fine-pitch, large-die Cu/low-k flip chip packages. In this paper, 3D finite element analyses were performed to investigate the reliability of 65 nm, 21times21 mm 9metal Cu/ low-k, chips with 150 mum interconnect pitch in a FCBGA package with a 750 mum die thickness and 1.0 mm substrate thickness. Three parametric cases involving different geometries of solder joints were analyze: (A) All 20 rows with spherical solder joints, (B) 10 hourglass joints followed by 10 spherical joints, and (C) 10 spherical joints followed by 10 hourglass joints. The spherical joints are stiffer than the hourglass joints. It was found that Case C gave the lowest inelastic energy dissipation (DeltaW) for the critical solder joint implying that Case C will have the longest fatigue life. It was also found that Case C gave the lowest maximum stress in the low-k material and it was further shown that reliability will be enhanced with decrease in die thickness and substrate thickness.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"69 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126017244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550091
F. Carson, S. Lee, I. Yoon
Package-on-package (PoP) has become the preferred means of stacking logic processors and memory for advanced mobile phones. The challenge is to reduce size, thickness, and cost of this PoP solution. The fan-in package-on-package (FiPoP) has been developed to address such concerns as well as enable more device integration while maintaining the desirable PoP business model. This paper will detail the development of the FiPoP to meet the size, thickness, flatness, and package level and board level reliability requirements of the typical handset application.
{"title":"The development of the Fan-in Package-on-Package","authors":"F. Carson, S. Lee, I. Yoon","doi":"10.1109/ECTC.2008.4550091","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550091","url":null,"abstract":"Package-on-package (PoP) has become the preferred means of stacking logic processors and memory for advanced mobile phones. The challenge is to reduce size, thickness, and cost of this PoP solution. The fan-in package-on-package (FiPoP) has been developed to address such concerns as well as enable more device integration while maintaining the desirable PoP business model. This paper will detail the development of the FiPoP to meet the size, thickness, flatness, and package level and board level reliability requirements of the typical handset application.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116127532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550124
A. Farris, Jianbiao Pan, A. Liddicoat, B. Toleno, D. Maslyk, D. Shangguan, J. Bath, D. Willie, D. Geiger
This paper presents the drop test reliability of 0.5 mm pitch lead-free chip scale packages (CSPs). Fifteen 0.5 mm pitch CSPs were assembled on a standard JEDEC drop reliability test board with Sn3.0Ag0.5Cu lead-free solder. Eight boards were edge-bonded with a UV-cured acrylic; eight boards were edge- bonded with a thermal-cured epoxy; and twelve boards were assembled without edge bonding. Half of the edge-bonded test boards were subjected to drop tests at a peak acceleration of 1500 G with a pulse duration of 0.5 ms, and the other half subjected to drop tests at a peak acceleration of 2900 G with a pulse duration of 0.3 ms. Half of the test boards without edge bonding were subjected to drop tests at a peak acceleration of 900 G with a pulse duration of 0.7 ms, and the other half subjected to drop tests at a peak acceleration of 1500 G with a pulse duration of 0.5 ms. Two drop test failure detection systems were used in this study to monitor the failure of solder joints: a high-speed resistance measurement system and a post-drop static resistance measurement system. The high-speed resistance measurement system, which has a scan frequency of 50 KHz and a 16-bit signal width, is able to detect intermittent failures during the short drop impact duration. Statistics of the number of drops to failure for the 15 component locations on each test board are reported. The effect of component position on drop test reliability is discussed. The test results show that the drop test performance of edge-bonded CSPs is five to eight times better than the CSPs without edge bonding. However, the drop test reliability of edge-bonded CSPs with the thermal-cured epoxy is different from that with edge-bonded CSPs with the UV-cured acrylic. The solder crack location and crack area are characterized with the dye penetrant method. The fracture surfaces are studied using scanning electron microscopy (SEM).
{"title":"Drop test reliability of lead-free chip scale packages","authors":"A. Farris, Jianbiao Pan, A. Liddicoat, B. Toleno, D. Maslyk, D. Shangguan, J. Bath, D. Willie, D. Geiger","doi":"10.1109/ECTC.2008.4550124","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550124","url":null,"abstract":"This paper presents the drop test reliability of 0.5 mm pitch lead-free chip scale packages (CSPs). Fifteen 0.5 mm pitch CSPs were assembled on a standard JEDEC drop reliability test board with Sn3.0Ag0.5Cu lead-free solder. Eight boards were edge-bonded with a UV-cured acrylic; eight boards were edge- bonded with a thermal-cured epoxy; and twelve boards were assembled without edge bonding. Half of the edge-bonded test boards were subjected to drop tests at a peak acceleration of 1500 G with a pulse duration of 0.5 ms, and the other half subjected to drop tests at a peak acceleration of 2900 G with a pulse duration of 0.3 ms. Half of the test boards without edge bonding were subjected to drop tests at a peak acceleration of 900 G with a pulse duration of 0.7 ms, and the other half subjected to drop tests at a peak acceleration of 1500 G with a pulse duration of 0.5 ms. Two drop test failure detection systems were used in this study to monitor the failure of solder joints: a high-speed resistance measurement system and a post-drop static resistance measurement system. The high-speed resistance measurement system, which has a scan frequency of 50 KHz and a 16-bit signal width, is able to detect intermittent failures during the short drop impact duration. Statistics of the number of drops to failure for the 15 component locations on each test board are reported. The effect of component position on drop test reliability is discussed. The test results show that the drop test performance of edge-bonded CSPs is five to eight times better than the CSPs without edge bonding. However, the drop test reliability of edge-bonded CSPs with the thermal-cured epoxy is different from that with edge-bonded CSPs with the UV-cured acrylic. The solder crack location and crack area are characterized with the dye penetrant method. The fracture surfaces are studied using scanning electron microscopy (SEM).","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116614661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550205
D. de Araujo, G. Pitner, M. Commens, B. Mutnury, J. Diepenbrock
In modern data centers, rack mount equipment provides ease of planning, installation, and management due to the standardized form-factors that multiple vendors follow. Within a single server or a blade environment, the predominant form factor is the backplane where multiple cards communicate through connectors. Within a rack, one or multiple servers may be installed and communication between racks and within a rack is accomplished through cables. In order to guarantee system performance, designers need accurate models of the cable's electrical behavior. Shielded TwinAx differential pair based cables are commonly used for short to medium reach (less than 10-20 meters) in standards such as SAS, InfiniBand, SATA, PCI-Express. In TwinAx shielded differential pair construction where the shield is wrapped around the TwinAx pair, it often has a band stop filter, or 'suckout' characteristic that limits its performance. This paper models and characterizes this effect using a full-wave finite element method (FEM) solver implemented in Ansoft HFSS. In this paper, the wrap effect is captured using full 3D electromagnetic model for the shielded TwinAx construction. The physics behind the suckout effect is explained using both 2D and 3D models. Finally, this paper describes the methods and techniques that can mitigate the suckout effect as well as a novel cable construction with a helical shield wrap without any suckout effects.
{"title":"Full-wave, TwinAx, differential cable modeling","authors":"D. de Araujo, G. Pitner, M. Commens, B. Mutnury, J. Diepenbrock","doi":"10.1109/ECTC.2008.4550205","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550205","url":null,"abstract":"In modern data centers, rack mount equipment provides ease of planning, installation, and management due to the standardized form-factors that multiple vendors follow. Within a single server or a blade environment, the predominant form factor is the backplane where multiple cards communicate through connectors. Within a rack, one or multiple servers may be installed and communication between racks and within a rack is accomplished through cables. In order to guarantee system performance, designers need accurate models of the cable's electrical behavior. Shielded TwinAx differential pair based cables are commonly used for short to medium reach (less than 10-20 meters) in standards such as SAS, InfiniBand, SATA, PCI-Express. In TwinAx shielded differential pair construction where the shield is wrapped around the TwinAx pair, it often has a band stop filter, or 'suckout' characteristic that limits its performance. This paper models and characterizes this effect using a full-wave finite element method (FEM) solver implemented in Ansoft HFSS. In this paper, the wrap effect is captured using full 3D electromagnetic model for the shielded TwinAx construction. The physics behind the suckout effect is explained using both 2D and 3D models. Finally, this paper describes the methods and techniques that can mitigate the suckout effect as well as a novel cable construction with a helical shield wrap without any suckout effects.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116595988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550016
F. Che, J. Luan, X. Baraton
In this work, five solder materials of Sn-3.0Ag-0.5Cu (SAC305), Sn-2.0Ag-0.5Cu (SAC205), Sn-1.0Ag-0.5Cu (SAC105), Sn-1.0Ag-0.5Cu-0.05Ni (SAC105Ni0.05) and Sn-1.0Ag-0.5Cu-0.02Ni (SAC105M0.02) were tested using tensile loading at room temperature to investigate the Ag content and Ni dopant effect on solder mechanical properties, respectively. In addition, different testing temperature conditions including -35 deg.C, 25 deg.C, 75 deg.C and 125 deg.C were used for SAC105M0.02 solder to investigate the temperature effect on mechanical properties. Tensile test under different strain rates from 0.000011/s to 0.11/s was conducted to study the strain rate effect on material properties. Test results show that the material properties of modulus, UTS and yield stress increase with strain rate and Ag content, but decrease with temperature. The 500 ppm Ni dopant has the significant effect on material properties of Sn-Ag-based solder than 200 ppm Ni dopant. Lower modulus, yield stress and UTS, higher elongation can be achieved for SAC105M0.05 solder compared to SAC105M0.02 solder. The rate dependent and Ag content dependent material models were developed for Sn-Ag-Cu lead free solders. In addition, the temperature and rate dependent models were developed for SAC105M0.02 solder. The microstructures of different solder alloys were analyzed based on SEM images. It was found that Ag content affects the Ag3Sn intermetallic compound dispersion and Sn grain size. The microstructure of solder alloy has finely dispersed IMC and fine Sn grain size for the high Ag content solder, which make the solder exhibit high strength.
{"title":"Effect of silver content and nickel dopant on mechanical properties of Sn-Ag-based solders","authors":"F. Che, J. Luan, X. Baraton","doi":"10.1109/ECTC.2008.4550016","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550016","url":null,"abstract":"In this work, five solder materials of Sn-3.0Ag-0.5Cu (SAC305), Sn-2.0Ag-0.5Cu (SAC205), Sn-1.0Ag-0.5Cu (SAC105), Sn-1.0Ag-0.5Cu-0.05Ni (SAC105Ni0.05) and Sn-1.0Ag-0.5Cu-0.02Ni (SAC105M0.02) were tested using tensile loading at room temperature to investigate the Ag content and Ni dopant effect on solder mechanical properties, respectively. In addition, different testing temperature conditions including -35 deg.C, 25 deg.C, 75 deg.C and 125 deg.C were used for SAC105M0.02 solder to investigate the temperature effect on mechanical properties. Tensile test under different strain rates from 0.000011/s to 0.11/s was conducted to study the strain rate effect on material properties. Test results show that the material properties of modulus, UTS and yield stress increase with strain rate and Ag content, but decrease with temperature. The 500 ppm Ni dopant has the significant effect on material properties of Sn-Ag-based solder than 200 ppm Ni dopant. Lower modulus, yield stress and UTS, higher elongation can be achieved for SAC105M0.05 solder compared to SAC105M0.02 solder. The rate dependent and Ag content dependent material models were developed for Sn-Ag-Cu lead free solders. In addition, the temperature and rate dependent models were developed for SAC105M0.02 solder. The microstructures of different solder alloys were analyzed based on SEM images. It was found that Ag content affects the Ag3Sn intermetallic compound dispersion and Sn grain size. The microstructure of solder alloy has finely dispersed IMC and fine Sn grain size for the high Ag content solder, which make the solder exhibit high strength.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125231489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4549943
Zhihong Huang, R. Chatterjee, P. Justison, R. Hernandez, S. Pozder, A. Jain, E. Acosta, D. Gajewski, V. Mathew, R.E. Jones
There is significant interest in 3D interconnect technology due to its capability to provide fast, efficient inter-die interconnects at a minimum package footprint. Intermetallic Cu-Sn bonding has been widely investigated for 3D interconnects. However, the electromigration (EM) intrinsic reliability of the 3D Cu-Sn die-to-die microconnects has not been reported. In this paper the EM performance of 3D Cu-Sn microconnects formed by thermo-compression bonding is investigated and the failure mechanisms are discussed. The 3D stacked dice were assembled in wire bond ceramic packages and EM tests were conducted in both air and nitrogen ambient at various temperatures. Microconnect chain and Kelvin structure's failure lifetime and the mean time to failure (MTTF) were measured. The failure analysis has been conducted and the possible failure mechanism has been proposed.
{"title":"Electromigration of Cu-Sn-Cu micropads in 3D interconnect","authors":"Zhihong Huang, R. Chatterjee, P. Justison, R. Hernandez, S. Pozder, A. Jain, E. Acosta, D. Gajewski, V. Mathew, R.E. Jones","doi":"10.1109/ECTC.2008.4549943","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4549943","url":null,"abstract":"There is significant interest in 3D interconnect technology due to its capability to provide fast, efficient inter-die interconnects at a minimum package footprint. Intermetallic Cu-Sn bonding has been widely investigated for 3D interconnects. However, the electromigration (EM) intrinsic reliability of the 3D Cu-Sn die-to-die microconnects has not been reported. In this paper the EM performance of 3D Cu-Sn microconnects formed by thermo-compression bonding is investigated and the failure mechanisms are discussed. The 3D stacked dice were assembled in wire bond ceramic packages and EM tests were conducted in both air and nitrogen ambient at various temperatures. Microconnect chain and Kelvin structure's failure lifetime and the mean time to failure (MTTF) were measured. The failure analysis has been conducted and the possible failure mechanism has been proposed.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125085897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：