Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550249
S. W. Ho, S. Yoon, Qiaoer Zhou, K. Pasad, V. Kripesh, J. Lau
Three dimensional system-in-package (3D SiP) based on silicon carriers or interposer is a fast emerging technology that offers system design flexibility and integration of heterogeneous technologies. One of the key technologies enabler for silicon carrier is through silicon via (TSV). The development of 3D SiP will require the devices with different functionality operating at high frequency to be densely packed on the silicon substrate. However, silicon substrate is usually of low resistivity, when a high frequency signal is transmitted vertically through the substrate via, significant signal attenuation can occur that leads to poor RF performance. In this paper, a coaxial TSV structure in silicon carrier is presented for high frequency applications. The coaxial TSV is able to suppress undesirable substrate loss as well as provide good impedance matching. Electrical modeling of coaxial TSV structure was carried out to obtain the required geometries for impedance matching. Three different types of test vehicles were fabricated; Cu-plug TSV in both low (~10 Omega-cm) and high resistivity (~4000 Omega-cm) silicon substrate, and coaxial TSV in low resistivity silicon substrate. The S-parameters of the via structure of the test vehicles were measured from 100 MHz to 10 GHz. The measured results show that the coaxial TSV structure is able to suppress silicon substrate loss and provide good RF performance compared to Cu-plug TSV structure.
{"title":"High RF performance TSV silicon carrier for high frequency application","authors":"S. W. Ho, S. Yoon, Qiaoer Zhou, K. Pasad, V. Kripesh, J. Lau","doi":"10.1109/ECTC.2008.4550249","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550249","url":null,"abstract":"Three dimensional system-in-package (3D SiP) based on silicon carriers or interposer is a fast emerging technology that offers system design flexibility and integration of heterogeneous technologies. One of the key technologies enabler for silicon carrier is through silicon via (TSV). The development of 3D SiP will require the devices with different functionality operating at high frequency to be densely packed on the silicon substrate. However, silicon substrate is usually of low resistivity, when a high frequency signal is transmitted vertically through the substrate via, significant signal attenuation can occur that leads to poor RF performance. In this paper, a coaxial TSV structure in silicon carrier is presented for high frequency applications. The coaxial TSV is able to suppress undesirable substrate loss as well as provide good impedance matching. Electrical modeling of coaxial TSV structure was carried out to obtain the required geometries for impedance matching. Three different types of test vehicles were fabricated; Cu-plug TSV in both low (~10 Omega-cm) and high resistivity (~4000 Omega-cm) silicon substrate, and coaxial TSV in low resistivity silicon substrate. The S-parameters of the via structure of the test vehicles were measured from 100 MHz to 10 GHz. The measured results show that the coaxial TSV structure is able to suppress silicon substrate loss and provide good RF performance compared to Cu-plug TSV structure.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125122265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550139
Seol-Min Yi, Jung-Kyu Jung, S. Choi, Inyoung Kim, Hyunchul Jung, J. Joung, Young‐Chang Joo
Inkjet printing technology is a pattern-on-demand technology which has numerous advantages. However, this technology needs an additional thermal treatment, i.e., drying process. This treatment results in microstructure evolution which is expected to relate to properties of film. The microstructure, electrical and mechanical properties of the inkjet printed Ag and Cu films were characterized as drying process. Model study on electrical resistivity of Ag film shows that the decomposition of capping molecule plays a key role in microstructure evolution and electrical resistivity. The effect of ambient in thermal treatment of inkjet printed Cu film also investigated in this purport. The adhesion strength as a mechanical property was measured by 4 point bend test using sandwiched structure. Strengthening of adhesion was observed as densification of inkjet printed film.
{"title":"Effect of microstructure on electrical and mechanical properties: Impurities of inkjet-printed Ag and Cu interconnects","authors":"Seol-Min Yi, Jung-Kyu Jung, S. Choi, Inyoung Kim, Hyunchul Jung, J. Joung, Young‐Chang Joo","doi":"10.1109/ECTC.2008.4550139","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550139","url":null,"abstract":"Inkjet printing technology is a pattern-on-demand technology which has numerous advantages. However, this technology needs an additional thermal treatment, i.e., drying process. This treatment results in microstructure evolution which is expected to relate to properties of film. The microstructure, electrical and mechanical properties of the inkjet printed Ag and Cu films were characterized as drying process. Model study on electrical resistivity of Ag film shows that the decomposition of capping molecule plays a key role in microstructure evolution and electrical resistivity. The effect of ambient in thermal treatment of inkjet printed Cu film also investigated in this purport. The adhesion strength as a mechanical property was measured by 4 point bend test using sandwiched structure. Strengthening of adhesion was observed as densification of inkjet printed film.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115198969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550086
P. Lall, C. Bhat, M. Hande, V. More, R. Vaidya, R. Pandher, J. Suhling, K. Goebel
Requirements for system availability for ultra-high reliability electronic systems such as airborne and space electronic systems are driving the need for advanced heath monitoring techniques for early detection of the onset of damage. Aerospace-electronic systems usually face a very harsh environment, requiring them to survive the high strain rates, e.g. during launch and re-entry and thermal environments including extreme low and high temperatures. Traditional health monitoring methodologies have relied on reactive methods of failure detection often providing little on no insight into the remaining useful life of the system. Detection of system-state significantly prior to catastrophic failure can significantly impact the reliability and availability of electronic systems. Previously, Lall, et. al. [2004, 2005, 2006, 2007] have developed methodologies for health management and interrogation of system state of electronic systems based on leading indicators. Examples of damage pre-cursors include micro-structural evolution, intermetallics, stress and stress gradients. Pre-cursors have been developed for both eutectic 63Sn37Pb and Sn4Ag0.5Cu alloy systems on a variety of area-array architectures. In this paper, a mathematical approach for interrogation of system state under cyclic thermo-mechanical stresses has been developed for 6-different leadfree solder alloy systems. Thermal cycles may be experienced by electronics due to power cycling or environmental cycling. Data has been collected for leading indicators of failure for alloy systems including, Sn3Ag0.5Cu, Sn3Ag0.7Cu, SnlAg0.5Cu, Sn0.3Ag0.5Cu0.1Bi, Sn0.2Ag0.5Cu0.1Bi0.1Ni, 96.5Sn3.5Ag second-level interconnects under the application of cyclic thermo-mechanical loads. Methodology presented resides in the pre-failure space of the system in which no macro-indicators such as cracks or delamination exist. Systems subjected to thermo-mechanical damage have been interrogated for system state and the computed damage state correlated with known imposed damage. The approach involves the use of condition monitoring devices which can be interrogated for damage proxies at finite time-intervals. Interrogation techniques are based on derivation of damage proxies, and system prior damage based non-linear least-squares methods including the Levenberg-Marquardt Algorithm. The system's residual life is computed based on residual-life computation algorithms.
{"title":"Interrogation of system state for damage assessment in lead-free electronics subjected to thermo-mechanical loads","authors":"P. Lall, C. Bhat, M. Hande, V. More, R. Vaidya, R. Pandher, J. Suhling, K. Goebel","doi":"10.1109/ECTC.2008.4550086","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550086","url":null,"abstract":"Requirements for system availability for ultra-high reliability electronic systems such as airborne and space electronic systems are driving the need for advanced heath monitoring techniques for early detection of the onset of damage. Aerospace-electronic systems usually face a very harsh environment, requiring them to survive the high strain rates, e.g. during launch and re-entry and thermal environments including extreme low and high temperatures. Traditional health monitoring methodologies have relied on reactive methods of failure detection often providing little on no insight into the remaining useful life of the system. Detection of system-state significantly prior to catastrophic failure can significantly impact the reliability and availability of electronic systems. Previously, Lall, et. al. [2004, 2005, 2006, 2007] have developed methodologies for health management and interrogation of system state of electronic systems based on leading indicators. Examples of damage pre-cursors include micro-structural evolution, intermetallics, stress and stress gradients. Pre-cursors have been developed for both eutectic 63Sn37Pb and Sn4Ag0.5Cu alloy systems on a variety of area-array architectures. In this paper, a mathematical approach for interrogation of system state under cyclic thermo-mechanical stresses has been developed for 6-different leadfree solder alloy systems. Thermal cycles may be experienced by electronics due to power cycling or environmental cycling. Data has been collected for leading indicators of failure for alloy systems including, Sn3Ag0.5Cu, Sn3Ag0.7Cu, SnlAg0.5Cu, Sn0.3Ag0.5Cu0.1Bi, Sn0.2Ag0.5Cu0.1Bi0.1Ni, 96.5Sn3.5Ag second-level interconnects under the application of cyclic thermo-mechanical loads. Methodology presented resides in the pre-failure space of the system in which no macro-indicators such as cracks or delamination exist. Systems subjected to thermo-mechanical damage have been interrogated for system state and the computed damage state correlated with known imposed damage. The approach involves the use of condition monitoring devices which can be interrogated for damage proxies at finite time-intervals. Interrogation techniques are based on derivation of damage proxies, and system prior damage based non-linear least-squares methods including the Levenberg-Marquardt Algorithm. The system's residual life is computed based on residual-life computation algorithms.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122755826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4549950
Tsung-Fu Tsai, Jing-Yao Chang, Chien-Wei Chien, J. Juang, Li-Cheng Shen
Immersion solder bumping, a mask-less and low cost processing, brings feasibility to the ultra-fine pitch chip-to- chip interconnection; however, how to make the uniform micro-bump is still a great challenge. In this paper, the uniform micro-bumps with very thin Sn-3.0Ag-0.5Cu (SAC305) solder layer on electroless nickel under bump metallization (UBM) are achieved. The test chips we used have 6,507 SAC305 solder micro-bumps with a pitch of 30 um. Two test chips are bonded to each other, and the optimum bonding conditions for a sufficient bonding quality are determined. The interfacial microstructure of the bonded samples before and after aging at 150degC for 168 hours is also investigated. The present results shows that the rapid phase growth at the solder/UBM interface would have a great impact on solder joint reliability.
{"title":"Ternary lead-free SnAgCu micro-bumps for ultra-fine pitch chip-to-chip interconnection","authors":"Tsung-Fu Tsai, Jing-Yao Chang, Chien-Wei Chien, J. Juang, Li-Cheng Shen","doi":"10.1109/ECTC.2008.4549950","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4549950","url":null,"abstract":"Immersion solder bumping, a mask-less and low cost processing, brings feasibility to the ultra-fine pitch chip-to- chip interconnection; however, how to make the uniform micro-bump is still a great challenge. In this paper, the uniform micro-bumps with very thin Sn-3.0Ag-0.5Cu (SAC305) solder layer on electroless nickel under bump metallization (UBM) are achieved. The test chips we used have 6,507 SAC305 solder micro-bumps with a pitch of 30 um. Two test chips are bonded to each other, and the optimum bonding conditions for a sufficient bonding quality are determined. The interfacial microstructure of the bonded samples before and after aging at 150degC for 168 hours is also investigated. The present results shows that the rapid phase growth at the solder/UBM interface would have a great impact on solder joint reliability.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116612825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4549972
Cheng Yang, M. Yuen, Bing Xu
Conductive polymers have a vast market in integrated circuits (IC) and microsystems packaging to enhance mechanical, thermal, electrical performance, and cost effectiveness[1]. Isotropically conductive adhesives (ICAs) have been explored for attaching encapsulated surface mount components on rigid and flexible printed circuits [2]. However, the practical use of conductive adhesives in surface mount applications is limited because of the weak electric conductivity. Jiang et al [3] used nano-sized silver particles as a candidate for conducting filers in order to reduce the sintering temperature, but the contact resistance is still high. Some groups [4, 5] studied a series of methods such as using carboxylic acid group containing chemicals as surfactants to enhance the conductivity of ICAs in a variety of conditions, but because the micron-sized silver fillers have a high sintering temperature, the enhancement in conductivity is still limited. In order to further improve the conductivity of ICAs and minimize the cost, we experimented on a series of materials for silver surface pretreatment. We noticed an about 20 times improvement in conductivity of the modified ICA than the control sample (75% silver content in all samples). The volume resistivity of the optimum formulation reached the level of 10-6 Omegaldrcm. We also analyzed the adhesion strength and thermal property of the modified ICA material. The study indicated that both the electrical properties and the mechanical property were improved without negatively affecting the other physical properties, and they are both remain stable after subjecting to the 85degC and 85% relative humidity conditioning test.
{"title":"Using novel materials to enhance the efficiency of conductive polymer","authors":"Cheng Yang, M. Yuen, Bing Xu","doi":"10.1109/ECTC.2008.4549972","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4549972","url":null,"abstract":"Conductive polymers have a vast market in integrated circuits (IC) and microsystems packaging to enhance mechanical, thermal, electrical performance, and cost effectiveness[1]. Isotropically conductive adhesives (ICAs) have been explored for attaching encapsulated surface mount components on rigid and flexible printed circuits [2]. However, the practical use of conductive adhesives in surface mount applications is limited because of the weak electric conductivity. Jiang et al [3] used nano-sized silver particles as a candidate for conducting filers in order to reduce the sintering temperature, but the contact resistance is still high. Some groups [4, 5] studied a series of methods such as using carboxylic acid group containing chemicals as surfactants to enhance the conductivity of ICAs in a variety of conditions, but because the micron-sized silver fillers have a high sintering temperature, the enhancement in conductivity is still limited. In order to further improve the conductivity of ICAs and minimize the cost, we experimented on a series of materials for silver surface pretreatment. We noticed an about 20 times improvement in conductivity of the modified ICA than the control sample (75% silver content in all samples). The volume resistivity of the optimum formulation reached the level of 10-6 Omegaldrcm. We also analyzed the adhesion strength and thermal property of the modified ICA material. The study indicated that both the electrical properties and the mechanical property were improved without negatively affecting the other physical properties, and they are both remain stable after subjecting to the 85degC and 85% relative humidity conditioning test.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128383900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550055
Jiongxin Lu, C. Wong
Novel materials for embedded capacitor applications are in great demands, for which high dielectric constant (k), low dielectric loss and process compatibility with the printed circuit boards (PCBs) are the most important prerequisites. We have systematically investigated an efficient way to enhance the dielectric performance of the high-k nanocomposites by the selection of the appropriate filler, its size, size distribution, surface property and morphology (aggregation status). The effect of the size and size distribution of metal nanoparticles in the nanocomposite on the dielectric properties of the nanocompsite were studied on an in-situ formed silver (Ag) incorporated carbon black (CB)/polymer composites system. In-situ formed Ag nanoparticles in the Ag/CB/epoxy composites increased the dielectric constant (k) value and decreased dissipation factor (Df). The size and size distribution of metal nanoparticles in the nanocomposite were found to have significant influence on the dielectric properties of the nanocomposite system. Smaller size and narrower size distribution of Ag nanoparticles resulted in lower dielectric loss tangent. The investigation of the morphology in terms of the aggregation status of nanoparticles on the dielectric properties of the nanocomposite revealed that assembly of the nanoparticles impact the dielectric performance of the nanocomposite in terms of the interfacial polarization and conducting property. The Ag/epoxy nanocomposite containing Ag nanoparticle with more discrete morphology rendered much lower dielectric loss tangent compared to the nanocomposites with Ag nanoparticles of more aggregated morphology.
{"title":"Dielectric performance enhancement of nanoparticle-based materials for embedded passive applications","authors":"Jiongxin Lu, C. Wong","doi":"10.1109/ECTC.2008.4550055","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550055","url":null,"abstract":"Novel materials for embedded capacitor applications are in great demands, for which high dielectric constant (k), low dielectric loss and process compatibility with the printed circuit boards (PCBs) are the most important prerequisites. We have systematically investigated an efficient way to enhance the dielectric performance of the high-k nanocomposites by the selection of the appropriate filler, its size, size distribution, surface property and morphology (aggregation status). The effect of the size and size distribution of metal nanoparticles in the nanocomposite on the dielectric properties of the nanocompsite were studied on an in-situ formed silver (Ag) incorporated carbon black (CB)/polymer composites system. In-situ formed Ag nanoparticles in the Ag/CB/epoxy composites increased the dielectric constant (k) value and decreased dissipation factor (Df). The size and size distribution of metal nanoparticles in the nanocomposite were found to have significant influence on the dielectric properties of the nanocomposite system. Smaller size and narrower size distribution of Ag nanoparticles resulted in lower dielectric loss tangent. The investigation of the morphology in terms of the aggregation status of nanoparticles on the dielectric properties of the nanocomposite revealed that assembly of the nanoparticles impact the dielectric performance of the nanocomposite in terms of the interfacial polarization and conducting property. The Ag/epoxy nanocomposite containing Ag nanoparticle with more discrete morphology rendered much lower dielectric loss tangent compared to the nanocomposites with Ag nanoparticles of more aggregated morphology.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129182235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4549999
K. Liu, J. Priest, J. Xue, Jarsh Lin, C. Kao, T. Wang, Y. Lai
Manufacturability and reliability of a custom CSP SRAM mounted on an interposer is discussed in this paper. In order to provide a reliable device for high reliability applications, an SRAM interposer structure was designed to ensure high reliability on every level of solder joint interconnects. Finite element modeling method was used as a mean to evaluate the reliability of various configurations of the protection methods. Test vehicles were built to run reliability tests on selected configurations from FEA simulation to evaluate the integrity and robustness of the SRAM interposer. An under fill process was chosen to be the protection method in production because of its reliability performance. However, extra efforts are needed for implementation during production in order to address the manufacturability concern.
{"title":"Manufacturability and reliability of a high-speed CSP SRAM on an interposer package","authors":"K. Liu, J. Priest, J. Xue, Jarsh Lin, C. Kao, T. Wang, Y. Lai","doi":"10.1109/ECTC.2008.4549999","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4549999","url":null,"abstract":"Manufacturability and reliability of a custom CSP SRAM mounted on an interposer is discussed in this paper. In order to provide a reliable device for high reliability applications, an SRAM interposer structure was designed to ensure high reliability on every level of solder joint interconnects. Finite element modeling method was used as a mean to evaluate the reliability of various configurations of the protection methods. Test vehicles were built to run reliability tests on selected configurations from FEA simulation to evaluate the integrity and robustness of the SRAM interposer. An under fill process was chosen to be the protection method in production because of its reliability performance. However, extra efforts are needed for implementation during production in order to address the manufacturability concern.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129197453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550267
Y. Abe, K. Iwaya
The production of the CMOS and CCD sensor packages for the cellular phone has been increasing rapidly. The CMOS and CCD sensor packages are composed with the holder, glass, lens, substrate, sensor and so on. The adhesive to seal up a holder and substrate is necessary. Heat curing adhesive is usually used, and it must have curability at low temperature and enough adhesion. The projection that was arranged by a retainer of a holder and the hole which was emptied into a substrate are used to fix the place, since the position or an axis gap occurs by vibration during transportation and curing. The position or axis gap is the serious problem for an image sensor module. The image sensor packages are becoming smaller and thinner, therefore it becomes difficult to arrange space for opening a hole on a substrate. In addition, it becomes little adhesion areas, too. We suggest that the temporary adhesion is possible by UV or heat in a short period of time. By prefixing, it is not necessary to arrange a projection, hole and an assembly jig for fix the place.
{"title":"The hybrid curing adhesive for image sensor module","authors":"Y. Abe, K. Iwaya","doi":"10.1109/ECTC.2008.4550267","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550267","url":null,"abstract":"The production of the CMOS and CCD sensor packages for the cellular phone has been increasing rapidly. The CMOS and CCD sensor packages are composed with the holder, glass, lens, substrate, sensor and so on. The adhesive to seal up a holder and substrate is necessary. Heat curing adhesive is usually used, and it must have curability at low temperature and enough adhesion. The projection that was arranged by a retainer of a holder and the hole which was emptied into a substrate are used to fix the place, since the position or an axis gap occurs by vibration during transportation and curing. The position or axis gap is the serious problem for an image sensor module. The image sensor packages are becoming smaller and thinner, therefore it becomes difficult to arrange space for opening a hole on a substrate. In addition, it becomes little adhesion areas, too. We suggest that the temporary adhesion is possible by UV or heat in a short period of time. By prefixing, it is not necessary to arrange a projection, hole and an assembly jig for fix the place.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123894370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550151
J. Nah, S. Buchwalter, P. Gruber, D. Shih, B. Furman
We report here preliminary results on a new Cu-cored flip chip structure combining C4NP (Controlled Collapse Chip Connect New Process) with Cu spheres for high density interconnections. C4NP is a new wafer bumping technology developed by IBM in which molten solder is injected into a mold and then transferred to the UBM (Under Bump Metallurgy) pads on the wafer. This simple and parallel process has shown the capability to combine low cost attributes with high performance capabilities. C4NP allows a larger number of interconnections with finer pitch than screen printing methods because it eliminates the volume reduction problem of solder paste. Also, C4NP allows more freedom in selecting the composition of solder bumps when compared with the electroplating method. To make Cu-cored flip chip interconnections with C4NP, Cu spheres are arrayed in the cavities on a mold which matches the CTE of the wafer. The Cu spheres are then transferred from the Si mold to C4NP solder bumps on the wafer by using the same process used for C4NP solder transfer. Then, after dicing, the diced chip is flip chip assembled on the substrate which has been pre-soldered. This combination of C4NP and Cu spheres is a dry process with potential for low cost, because it does not need thick photoresist, lithography, or plating process steps. Our early laboratory demonstrations of Cu-cored bumping have processed individual chips rather than full wafers; but, based on our manufacturing experience with C4NP solder bumping, we expect the process to be readily extendible to wafer scale. The C4NP Cu-cored flip chip joints offer potential advantages in stress mitigation and electrical performance. The centered Cu sphere in the joint ensures greater stand-off for fine pitch, which facilitates the underfill process and improves fatigue resistance due to the taller bump. The low electrical resistivity of Cu enhances current carrying capacity. The small Sn/Cu ratio in the bump would decrease UBM consumption and solder depletion under high current stressing. The high thermal conductivity of Cu also enhances heat transfer from the chip to the substrate. Due to the high Cu/Sn ratio in the flip chip interconnections, the higher Young's modulus of Cu over solder could be a concern for stress concentration on the IC despite the higher stand-off height provided by the Cu-core bump. However, in the C4NP Cu-cored flip chip structure, since the transfer mold is used for inserting Cu spheres into the flip chip joints, Cu spheres can be selectively deployed only to the joints where the composite bumps are required, whereas the other, highly stressed joints can be electrically connected without Cu spheres. Therefore, the selective use of composite interconnects may allow stress to be minimized while optimizing electrical performance.
{"title":"C4NP Cu-cored Pb-free flip chip interconnections","authors":"J. Nah, S. Buchwalter, P. Gruber, D. Shih, B. Furman","doi":"10.1109/ECTC.2008.4550151","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550151","url":null,"abstract":"We report here preliminary results on a new Cu-cored flip chip structure combining C4NP (Controlled Collapse Chip Connect New Process) with Cu spheres for high density interconnections. C4NP is a new wafer bumping technology developed by IBM in which molten solder is injected into a mold and then transferred to the UBM (Under Bump Metallurgy) pads on the wafer. This simple and parallel process has shown the capability to combine low cost attributes with high performance capabilities. C4NP allows a larger number of interconnections with finer pitch than screen printing methods because it eliminates the volume reduction problem of solder paste. Also, C4NP allows more freedom in selecting the composition of solder bumps when compared with the electroplating method. To make Cu-cored flip chip interconnections with C4NP, Cu spheres are arrayed in the cavities on a mold which matches the CTE of the wafer. The Cu spheres are then transferred from the Si mold to C4NP solder bumps on the wafer by using the same process used for C4NP solder transfer. Then, after dicing, the diced chip is flip chip assembled on the substrate which has been pre-soldered. This combination of C4NP and Cu spheres is a dry process with potential for low cost, because it does not need thick photoresist, lithography, or plating process steps. Our early laboratory demonstrations of Cu-cored bumping have processed individual chips rather than full wafers; but, based on our manufacturing experience with C4NP solder bumping, we expect the process to be readily extendible to wafer scale. The C4NP Cu-cored flip chip joints offer potential advantages in stress mitigation and electrical performance. The centered Cu sphere in the joint ensures greater stand-off for fine pitch, which facilitates the underfill process and improves fatigue resistance due to the taller bump. The low electrical resistivity of Cu enhances current carrying capacity. The small Sn/Cu ratio in the bump would decrease UBM consumption and solder depletion under high current stressing. The high thermal conductivity of Cu also enhances heat transfer from the chip to the substrate. Due to the high Cu/Sn ratio in the flip chip interconnections, the higher Young's modulus of Cu over solder could be a concern for stress concentration on the IC despite the higher stand-off height provided by the Cu-core bump. However, in the C4NP Cu-cored flip chip structure, since the transfer mold is used for inserting Cu spheres into the flip chip joints, Cu spheres can be selectively deployed only to the joints where the composite bumps are required, whereas the other, highly stressed joints can be electrically connected without Cu spheres. Therefore, the selective use of composite interconnects may allow stress to be minimized while optimizing electrical performance.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"4 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114116094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550271
Gawon Kim, A. Lu, Fan Wei, L. L. Wai, Joungho Kim
Recently, the timing control of high-frequency signals is strongly demanded due to the high integration density in three-dimensional (3D) LTCC-based SiP applications. Therefore, to control the skew or timing delay, new 3D delay lines will be proposed. For frailty of the signal via, we adopt the concept of coaxial line and proposed an advanced signal via structure with quasi coaxial ground (QCOX-GND) vias. We will show the simulated results using EM and circuit simulator.
{"title":"3D strip meander delay line structure for multilayer LTCC-based SiP applications","authors":"Gawon Kim, A. Lu, Fan Wei, L. L. Wai, Joungho Kim","doi":"10.1109/ECTC.2008.4550271","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550271","url":null,"abstract":"Recently, the timing control of high-frequency signals is strongly demanded due to the high integration density in three-dimensional (3D) LTCC-based SiP applications. Therefore, to control the skew or timing delay, new 3D delay lines will be proposed. For frailty of the signal via, we adopt the concept of coaxial line and proposed an advanced signal via structure with quasi coaxial ground (QCOX-GND) vias. We will show the simulated results using EM and circuit simulator.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"75 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116350238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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