Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452560
Li Tian, Kuibo Lan, Binghai Liu, Jing-Jing Li, Y. Che, Gaojie Wen, Jinrong Song
With multi-metal layers and scaling down we occurred many difficulties in FA (Failure Analysis). Failure isolation for FA has more challenge with smaller defects and process changes. Conventional FA techniques couldn't meet need of analysis, so the advanced nano-techniques must be developed and applied in FA [1]-[2]. By characterizing the electrical behavior on devices, these FA techniques (for example nanoprobing, EBAC, C-AFM, etc) precisely locates defects before any PF A is performed and allows for deeper understanding of the root cause. Nanoprobing are commonly utilized to measure electrical characterization with nanoscale area and under-layer circuit in F A lab. EBAC applications are to locate the high resistance, open circuit of interconnection, the connected path of a circuit, etc. The main application of Conductive Atomic Force Microscope (C-AFM) for high/low resistance and junction leakages differentiation had proven to be very useful in determining the failure mechanism. In this paper, the principle of advanced FA nano-techniques were introduced simply. Then three real cases with different failure mechanism were shared with applying these nano-techniques. In first case nanoprobing help to confirm resistive/open failure; in second case EBAC analysis revealed short failure between adjacent metal lines; in third case C-AFM technique was applied to find out implant/crystal defect which caused timing delay failure.
{"title":"The Application of Advanced Nano-Techniques in Failure Analysis for Different Failure Mechanism","authors":"Li Tian, Kuibo Lan, Binghai Liu, Jing-Jing Li, Y. Che, Gaojie Wen, Jinrong Song","doi":"10.1109/IPFA.2018.8452560","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452560","url":null,"abstract":"With multi-metal layers and scaling down we occurred many difficulties in FA (Failure Analysis). Failure isolation for FA has more challenge with smaller defects and process changes. Conventional FA techniques couldn't meet need of analysis, so the advanced nano-techniques must be developed and applied in FA [1]-[2]. By characterizing the electrical behavior on devices, these FA techniques (for example nanoprobing, EBAC, C-AFM, etc) precisely locates defects before any PF A is performed and allows for deeper understanding of the root cause. Nanoprobing are commonly utilized to measure electrical characterization with nanoscale area and under-layer circuit in F A lab. EBAC applications are to locate the high resistance, open circuit of interconnection, the connected path of a circuit, etc. The main application of Conductive Atomic Force Microscope (C-AFM) for high/low resistance and junction leakages differentiation had proven to be very useful in determining the failure mechanism. In this paper, the principle of advanced FA nano-techniques were introduced simply. Then three real cases with different failure mechanism were shared with applying these nano-techniques. In first case nanoprobing help to confirm resistive/open failure; in second case EBAC analysis revealed short failure between adjacent metal lines; in third case C-AFM technique was applied to find out implant/crystal defect which caused timing delay failure.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116212567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452491
J. Kim, M. Jin, H. Sagong, S. Pae
A systematic study of accurate reliability projection in lOnm FinFETs are discussed in this paper. As the semiconductor process technology continuously scales down to achieve optimum performance, reliability margin from the minimal spacing is also reduced. In many cases, conventional reliability modeling of BTI, HCI, and TDDB can be done but more effort can be put to improve the reliability modeling and characterization work to enable more critical space margin and verify through cleverly stressing it, thereby demonstrate the excellent product level quality and ensure reliability robustness.
{"title":"Reliability Assessment of 10nm FinFET Process Technology","authors":"J. Kim, M. Jin, H. Sagong, S. Pae","doi":"10.1109/IPFA.2018.8452491","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452491","url":null,"abstract":"A systematic study of accurate reliability projection in lOnm FinFETs are discussed in this paper. As the semiconductor process technology continuously scales down to achieve optimum performance, reliability margin from the minimal spacing is also reduced. In many cases, conventional reliability modeling of BTI, HCI, and TDDB can be done but more effort can be put to improve the reliability modeling and characterization work to enable more critical space margin and verify through cleverly stressing it, thereby demonstrate the excellent product level quality and ensure reliability robustness.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"223 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116535230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452594
Yu-Ting Lin, B. Lai, C. Tsao, Yi-Sheng Lin, Yu-Hsiang Hsiao
In this study we demonstrate the use of phase shift of lock-in thermography (LIT) a powerful technique in characterizing the Z profile of 2.5D packages. It is interesting to have a good understanding of how a given package structure correlates with LIT phase shift. We create a short defect to validate the experimental phase model and the approach would be useful in applying to other type of 2.5D lCs.
{"title":"Study of Phase Shift of Lock-In Thermography and Its Application in 2.5D IC Package","authors":"Yu-Ting Lin, B. Lai, C. Tsao, Yi-Sheng Lin, Yu-Hsiang Hsiao","doi":"10.1109/IPFA.2018.8452594","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452594","url":null,"abstract":"In this study we demonstrate the use of phase shift of lock-in thermography (LIT) a powerful technique in characterizing the Z profile of 2.5D packages. It is interesting to have a good understanding of how a given package structure correlates with LIT phase shift. We create a short defect to validate the experimental phase model and the approach would be useful in applying to other type of 2.5D lCs.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122796160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452583
S. Moon, A. Quah, D. Nagalingam, K. H. Yip, C.Q. Chen, Y. Tam, P. T. Ng, H. Ng, G. Ang, J. Lam, Z. Mai
Successful fault localization is heavily dependent on the ability to replicate the failure mode in the analytical scanning optical microscope (SOM) system for defect isolation. However, typical SOM configuration with confined stage space is limited to about 4 probes – 4 SMUs resources for bench measurement. This has impeded the successful debug of functional IDDQ/powerdown leakage failure which may require higher pin counts to enter into leakage mode. In this paper, the static fault localization capability of such failures is enhanced with an engineering approach to simplify the biasing conditions for static debug within the SOM system with limited test resources. This is especially useful in a foundry environment that manufactures a wide variety of products from differentiated process lines. Several case studies were described to demonstrate how this optimized electrical FA flow was applied with great success to debug multiple challenging low yield functional leakage issues.
{"title":"Achieving Simplified Biasing Conditions with Pin Reduction Approach to enhance Static Fault Localization Capability","authors":"S. Moon, A. Quah, D. Nagalingam, K. H. Yip, C.Q. Chen, Y. Tam, P. T. Ng, H. Ng, G. Ang, J. Lam, Z. Mai","doi":"10.1109/IPFA.2018.8452583","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452583","url":null,"abstract":"Successful fault localization is heavily dependent on the ability to replicate the failure mode in the analytical scanning optical microscope (SOM) system for defect isolation. However, typical SOM configuration with confined stage space is limited to about 4 probes – 4 SMUs resources for bench measurement. This has impeded the successful debug of functional IDDQ/powerdown leakage failure which may require higher pin counts to enter into leakage mode. In this paper, the static fault localization capability of such failures is enhanced with an engineering approach to simplify the biasing conditions for static debug within the SOM system with limited test resources. This is especially useful in a foundry environment that manufactures a wide variety of products from differentiated process lines. Several case studies were described to demonstrate how this optimized electrical FA flow was applied with great success to debug multiple challenging low yield functional leakage issues.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124617930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452521
Xiaoxuan Li, Xintong Zru, Mei Zhen Ng, R. R. Nistala, Z. Mo, C. Seet
Materials characterization at micro- and nano- scale is important for developing robust processes in wafer fabrication. In this paper, the techniques of nanoindentation and SEM imaging are employed to study the material hardness and grain size of Al films grown under different conditions. The methodology developed by Oliver and Phar is used for Al hardness measurements while ASTM International Standard E112-12 was followed in estimating the Al grain size. It will be shown that deposition temperature of Al thin film is the bigger factor in influencing the grain size of the resulting Al film as compared to changes made to its underlying bottom liner (TiN). However, in terms of film hardness, the elimination of the bottom liner exerts a greater influence as compared to deposition temperature.
{"title":"The Impact of Film Deposition Temperature and Bottom Liner on the Hardness and Grain Size of Al Films Investigated Using Nanoindentation and SEM Techniques","authors":"Xiaoxuan Li, Xintong Zru, Mei Zhen Ng, R. R. Nistala, Z. Mo, C. Seet","doi":"10.1109/IPFA.2018.8452521","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452521","url":null,"abstract":"Materials characterization at micro- and nano- scale is important for developing robust processes in wafer fabrication. In this paper, the techniques of nanoindentation and SEM imaging are employed to study the material hardness and grain size of Al films grown under different conditions. The methodology developed by Oliver and Phar is used for Al hardness measurements while ASTM International Standard E112-12 was followed in estimating the Al grain size. It will be shown that deposition temperature of Al thin film is the bigger factor in influencing the grain size of the resulting Al film as compared to changes made to its underlying bottom liner (TiN). However, in terms of film hardness, the elimination of the bottom liner exerts a greater influence as compared to deposition temperature.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116973687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452178
T. Takezaki, M. Kawano, S. Machida, D. Ryuzaki
We present the first through-transmission images in scanning acoustic tomography (SAT) using a capacitive micromachined ultrasound transducer (CMUT) as a receiving probe. A CMUT cell with a narrow gap of 30 nm was used to obtain high receive sensitivity. A 30-MHz receiving CMUT probe with a −3-dB fractional bandwidth of 109 % was used in the through-transmission technique of SAT. In the imaging of artificial linear voids formed in a Si wafer using a 50-MHz piezoelectric transmitting probe, the lateral resolution was approximately 65 µm, In the reception of the transmitted pulse through a 2-mm thick acryl plate, the signal-to-noise ratio of the CMUT probe was 1.7 times higher than that of a 25-MHz piezoelectric one. In the imaging of a 2.3-mm thick ball grid array (BGA) package using the 50-MHz piezoelectric transmitting probe, the CMUT probe was more sensitive than the piezoelectric probe by 10 dB in the frequency range of 20 to 30 MHz. The resolution of the CMUT probe was higher than that of the piezoelectric one.
{"title":"Through-Transmission Scanning Acoustic Tomography Using Capacitive Micromachined Ultrasound Transducer","authors":"T. Takezaki, M. Kawano, S. Machida, D. Ryuzaki","doi":"10.1109/IPFA.2018.8452178","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452178","url":null,"abstract":"We present the first through-transmission images in scanning acoustic tomography (SAT) using a capacitive micromachined ultrasound transducer (CMUT) as a receiving probe. A CMUT cell with a narrow gap of 30 nm was used to obtain high receive sensitivity. A 30-MHz receiving CMUT probe with a −3-dB fractional bandwidth of 109 % was used in the through-transmission technique of SAT. In the imaging of artificial linear voids formed in a Si wafer using a 50-MHz piezoelectric transmitting probe, the lateral resolution was approximately 65 µm, In the reception of the transmitted pulse through a 2-mm thick acryl plate, the signal-to-noise ratio of the CMUT probe was 1.7 times higher than that of a 25-MHz piezoelectric one. In the imaging of a 2.3-mm thick ball grid array (BGA) package using the 50-MHz piezoelectric transmitting probe, the CMUT probe was more sensitive than the piezoelectric probe by 10 dB in the frequency range of 20 to 30 MHz. The resolution of the CMUT probe was higher than that of the piezoelectric one.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133356969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452598
Yanlin Pan, Yuzhe Zhao, P. K. Tan, Z. Mai, F. Rival, J. Lam
This paper presents the impact of coating techniques for TEM sample preparation on ultra low-k dielectric devices after progressive-FIB cross-section analysis. The ultra low-k materials used as inter-metal dielectrics (IMD) has a k value less than 2.6. In the experimental study on three commonly used protective coatings (sputtered Pt, e-beam deposited insulator and PECVD oxide) for the 28 nm technology node with ultra low-k IMD, PECVD oxide coating was found to be an ideal choice for the TEM sample preparation with the least low-k dielectric deformation or damage. In-situ e-beam deposited insulator in a dual-beam FIB tool equipped with a GIS for insulator deposition is a convenient and commonly used method. However, the e-beam can introduce a considerable damage to the ultra low-k IMD during the e-beam deposition. Sputtered Pt can achieve a damage-free profile of an ultra low-k IMD, but we have to sacrifice certain portion of the target area in the final FIB cleaning process during TEM sample preparation. This makes sputtered Pt not suitable for the TEM sample preparation on a defect with a small size (<100 nm).
{"title":"Problems of and Solutions for Coating Techniques for TEM Sample Preparation on Ultra Low-k Dielectric Devices after Progressive-FIB Cross-section Analysis","authors":"Yanlin Pan, Yuzhe Zhao, P. K. Tan, Z. Mai, F. Rival, J. Lam","doi":"10.1109/IPFA.2018.8452598","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452598","url":null,"abstract":"This paper presents the impact of coating techniques for TEM sample preparation on ultra low-k dielectric devices after progressive-FIB cross-section analysis. The ultra low-k materials used as inter-metal dielectrics (IMD) has a k value less than 2.6. In the experimental study on three commonly used protective coatings (sputtered Pt, e-beam deposited insulator and PECVD oxide) for the 28 nm technology node with ultra low-k IMD, PECVD oxide coating was found to be an ideal choice for the TEM sample preparation with the least low-k dielectric deformation or damage. In-situ e-beam deposited insulator in a dual-beam FIB tool equipped with a GIS for insulator deposition is a convenient and commonly used method. However, the e-beam can introduce a considerable damage to the ultra low-k IMD during the e-beam deposition. Sputtered Pt can achieve a damage-free profile of an ultra low-k IMD, but we have to sacrifice certain portion of the target area in the final FIB cleaning process during TEM sample preparation. This makes sputtered Pt not suitable for the TEM sample preparation on a defect with a small size (<100 nm).","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133492179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452179
Xin Li, Jing Yang, P. Salinas
The BRAM block is a configurable memory module that attaches to a variety of BRAM interface controller. BRAM serves as a relatively large memory structure (i.e. larger than distributed RAMs or a bunch of D-flip-flop grouped together, but much smaller than off chip memory resources). In addition, multiple blocks can be cascaded to create still larger memory. The failure configuration type of BRAM in read operation was screened out by automatic test equipment (ATE). The failure pattern was created in Vivado which integrated logic analyzer (ILA) was inserted to monitor the failure BRAM data and compared against good BRAM data. The successful fault isolation of BRAM failure was mainly relied on pattern analysis as well as BRAM configuration.
{"title":"Electrical Diagnosis of 7 Series FPGAs Read Sequence Dependent Bram Failure Using Pattern Analysis","authors":"Xin Li, Jing Yang, P. Salinas","doi":"10.1109/IPFA.2018.8452179","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452179","url":null,"abstract":"The BRAM block is a configurable memory module that attaches to a variety of BRAM interface controller. BRAM serves as a relatively large memory structure (i.e. larger than distributed RAMs or a bunch of D-flip-flop grouped together, but much smaller than off chip memory resources). In addition, multiple blocks can be cascaded to create still larger memory. The failure configuration type of BRAM in read operation was screened out by automatic test equipment (ATE). The failure pattern was created in Vivado which integrated logic analyzer (ILA) was inserted to monitor the failure BRAM data and compared against good BRAM data. The successful fault isolation of BRAM failure was mainly relied on pattern analysis as well as BRAM configuration.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133653269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452488
Beomjun Kim, Juhyun Kim, Wookhyun Cho, Seongjun Cho, Seok-jun Won, Jinsung Kim
As device feature becomes smaller, the different types of failure mechanism increases. Electrical Failure Analysis (EFA) becomes more challenging and complex. Especially functional test failures where conventional isolation techniques such as photon emission microscopy (PEM) and optical beam induced resistance change (OBIRCH) are not effective to pinpoint the exact failure position, advanced dynamic EFA methodologies are required. Soft failures on advanced logic are more pervasive in recent years [1]. Typically, such failures respond to temperature, power supply voltage or frequency and have been one of the most difficult types of defects to isolate. Dynamic Laser Stimulation (DLS)[2] is widely used for soft defect analysis and it is an effective and quick method to localize soft defects in integrated circuits (IC). In this paper, two FA cases are presented to emphasize the effectiveness of DLS in localizing soft defects on 10nm logic device.
{"title":"Soft Defect Analysis on Advanced Logic Integrated Circuit by Dynamic Laser Stimulation","authors":"Beomjun Kim, Juhyun Kim, Wookhyun Cho, Seongjun Cho, Seok-jun Won, Jinsung Kim","doi":"10.1109/IPFA.2018.8452488","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452488","url":null,"abstract":"As device feature becomes smaller, the different types of failure mechanism increases. Electrical Failure Analysis (EFA) becomes more challenging and complex. Especially functional test failures where conventional isolation techniques such as photon emission microscopy (PEM) and optical beam induced resistance change (OBIRCH) are not effective to pinpoint the exact failure position, advanced dynamic EFA methodologies are required. Soft failures on advanced logic are more pervasive in recent years [1]. Typically, such failures respond to temperature, power supply voltage or frequency and have been one of the most difficult types of defects to isolate. Dynamic Laser Stimulation (DLS)[2] is widely used for soft defect analysis and it is an effective and quick method to localize soft defects in integrated circuits (IC). In this paper, two FA cases are presented to emphasize the effectiveness of DLS in localizing soft defects on 10nm logic device.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"279 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133947111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452554
Yulong Zhang, Lulu Wang, Bo Gao, Lixin Wang, Jiajun Luo
Because of the nature of multilayered structure and their metal characteristics, it is difficult to conduct failure analysis on multilayer-metal-packaged power devices with abnormal thermal characteristics using conventional techniques. In order to overcome this challenge, a systematic solution is proposed. Firstly, the failure cause of abnormal thermal response for power devices is identified as the problem of heat dissipation through electrical tests and analysis of diode forward voltage $(V_{mathrm{SD}})$ curves. Secondly, specific failure sites of power devices were located by the structure function analysis and the X-CT test. Finally, the failure site was analyzed by physical failure analysis techniques, and the specific failure cause was validated and further analyzed by microscopic observations and EDS. It was found that the oxidation of back metallization led to the formation of solder voids which resulted in the above failure.
{"title":"Failure Analysis of Multilayer-Metal-Packaged Power Devices for Abnormal Thermal Response","authors":"Yulong Zhang, Lulu Wang, Bo Gao, Lixin Wang, Jiajun Luo","doi":"10.1109/IPFA.2018.8452554","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452554","url":null,"abstract":"Because of the nature of multilayered structure and their metal characteristics, it is difficult to conduct failure analysis on multilayer-metal-packaged power devices with abnormal thermal characteristics using conventional techniques. In order to overcome this challenge, a systematic solution is proposed. Firstly, the failure cause of abnormal thermal response for power devices is identified as the problem of heat dissipation through electrical tests and analysis of diode forward voltage $(V_{mathrm{SD}})$ curves. Secondly, specific failure sites of power devices were located by the structure function analysis and the X-CT test. Finally, the failure site was analyzed by physical failure analysis techniques, and the specific failure cause was validated and further analyzed by microscopic observations and EDS. It was found that the oxidation of back metallization led to the formation of solder voids which resulted in the above failure.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133186813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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