Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452559
Longda Zhou, Bo Tang, Hong Yang, Hao Xu, Yongliang Li, E. Simoen, H. Yin, Huilong Zhu, Chao Zhao, Wenwu Wang, Dapeng Chen, Tianchun Ye
In this study, ultra-fast methods were used to measure the threshold voltage shift $(Deltamathrm{V}_{mathrm{T}})$ of the negative bias temperature instability (NBTI) in p-channel complementary metal oxide semiconductor field effect transistors (p-CMOSFETs) with a high-klmetal gate (HK/MG) stack. The voltage (Vg,str) and temperature (T) dependence of the NBTI time exponent (n) were studied under a wide range of stress conditions, and the results demonstrated a strong T dependence of n above room temperature (RT) and that the field reduction effect played an important role in determining the dependence of $n$ on Vg,str and T. With the direct current current-voltage (DCIV) method, the similarity of n, activation energy (EA) and voltage acceleration factor $(Gamma)$ between the trap generation $(Delta mathrm{N}_{mathrm{T}})$ and $Delta mathrm{V}_{mathrm{T}}$ indicates that $Delta mathrm{N}_{mathrm{T}}$ is the dominant subcomponent at higher values of T. The impact of the field reduction effect on the time exponents of $Deltamathrm{V}_{mathrm{T}}$ and $Deltamathrm{V}_{mathrm{T}}$, EA, and $Gamma$ were also investigated.
{"title":"Physical Mechanism Underlying the Time Exponent Shift in the Ultra-fast NBTI of High-k/Metal gated p-CMOSFETs","authors":"Longda Zhou, Bo Tang, Hong Yang, Hao Xu, Yongliang Li, E. Simoen, H. Yin, Huilong Zhu, Chao Zhao, Wenwu Wang, Dapeng Chen, Tianchun Ye","doi":"10.1109/IPFA.2018.8452559","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452559","url":null,"abstract":"In this study, ultra-fast methods were used to measure the threshold voltage shift $(Deltamathrm{V}_{mathrm{T}})$ of the negative bias temperature instability (NBTI) in p-channel complementary metal oxide semiconductor field effect transistors (p-CMOSFETs) with a high-klmetal gate (HK/MG) stack. The voltage (Vg,str) and temperature (T) dependence of the NBTI time exponent (n) were studied under a wide range of stress conditions, and the results demonstrated a strong T dependence of n above room temperature (RT) and that the field reduction effect played an important role in determining the dependence of $n$ on Vg,str and T. With the direct current current-voltage (DCIV) method, the similarity of n, activation energy (EA) and voltage acceleration factor $(Gamma)$ between the trap generation $(Delta mathrm{N}_{mathrm{T}})$ and $Delta mathrm{V}_{mathrm{T}}$ indicates that $Delta mathrm{N}_{mathrm{T}}$ is the dominant subcomponent at higher values of T. The impact of the field reduction effect on the time exponents of $Deltamathrm{V}_{mathrm{T}}$ and $Deltamathrm{V}_{mathrm{T}}$, EA, and $Gamma$ were also investigated.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128976335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452517
Ronald C. Apolinaria, David Joseph Rimbon, E. J. de La Cruz
Defect localization on a digital block is challenging, since modern gate densities makes in-circuit micro-probing to do voltage mapping almost impossible. Additionally, large top metal layer areas often preclude the use of top-side analysis to validate a fault isolation result. However, with in-depth circuit analysis, the correlation between electrical failure mode and fault isolation result can be established, which facilitates identification of the most probable defective node within the faulty block. Further fault localization techniques, such as curve trace micro-probing and OBIRCH analysis, perform a vital role in identifying the defect location. A case study is presented to demonstrate that the failure mechanism can be successfully determined using these techniques.
{"title":"Digital Block Defect Localization using in-depth Circuit Analysis for Electrical Verification and Fault Isolation Correlation","authors":"Ronald C. Apolinaria, David Joseph Rimbon, E. J. de La Cruz","doi":"10.1109/IPFA.2018.8452517","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452517","url":null,"abstract":"Defect localization on a digital block is challenging, since modern gate densities makes in-circuit micro-probing to do voltage mapping almost impossible. Additionally, large top metal layer areas often preclude the use of top-side analysis to validate a fault isolation result. However, with in-depth circuit analysis, the correlation between electrical failure mode and fault isolation result can be established, which facilitates identification of the most probable defective node within the faulty block. Further fault localization techniques, such as curve trace micro-probing and OBIRCH analysis, perform a vital role in identifying the defect location. A case study is presented to demonstrate that the failure mechanism can be successfully determined using these techniques.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128958805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452603
Ke-Ying Lin, Yu Chi Wang
A resistive short IV curve was detected in a stacked-die device after a highly accelerated stress test (HAST). Lock-in thermography (LIT), a non-destructive fault isolation technique, was applied to localize the fault location in the top die of the intact package. Thereafter, backside sample preparation and physical failure analysis (PFA) were performed and revealed the die crack issue causing the fault.
{"title":"Case Study of a Resistive Short in a Stacked-Die Device","authors":"Ke-Ying Lin, Yu Chi Wang","doi":"10.1109/IPFA.2018.8452603","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452603","url":null,"abstract":"A resistive short IV curve was detected in a stacked-die device after a highly accelerated stress test (HAST). Lock-in thermography (LIT), a non-destructive fault isolation technique, was applied to localize the fault location in the top die of the intact package. Thereafter, backside sample preparation and physical failure analysis (PFA) were performed and revealed the die crack issue causing the fault.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130978143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452536
K. Patel, J. Cottom, M. Bosman, A. Kenyon, A. Shluger
In this study, Density Functional Theory (DFT) calculations were used to model the incorporation and diffusion of Ag in Ag/a-Si02/Pt resistive random-access memory (RRAM) devices. The Ag clustering mechanism is vital for understanding device operation and at this stage is unknown. In this paper an O vacancy (Vo) mediated cluster model is presented, where the Vo is identified as the principle site for $mathrm{Ag}^{+}$ reduction. The $mathrm{Ag}^{+}$ interstitial is energetically favored at the Fermi energies of Ag and Pt, indicating that $mathrm{Ag}^{+}$ ions are not reduced at the Pt electrode via electron tunneling. Instead, $mathrm{Ag}^{+}$ ions bind to Vo forming the $[mathrm{Ag}/mathrm{Vo}]^{+}$ complex, reducing $mathrm{Ag}^{+}$ via charge transfer from the Si atoms in the vacancy. The $[mathrm{Ag}/mathrm{Vo}]^{+}$ complex is then able to trap an electron forming $[mathrm{Ag}/mathrm{Vo}]^{0}$ at the Fermi energy of Pt. This complex is then able to act as a nucleation site for of Ag clustering with the formation of $[mathrm{Ag}2/mathrm{Vo}]^{+}$ which is reduced by the above mechanism.
{"title":"Theoretical Study of Ag Interactions in Amorphous Silica RRAM Devices","authors":"K. Patel, J. Cottom, M. Bosman, A. Kenyon, A. Shluger","doi":"10.1109/IPFA.2018.8452536","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452536","url":null,"abstract":"In this study, Density Functional Theory (DFT) calculations were used to model the incorporation and diffusion of Ag in Ag/a-Si02/Pt resistive random-access memory (RRAM) devices. The Ag clustering mechanism is vital for understanding device operation and at this stage is unknown. In this paper an O vacancy (Vo) mediated cluster model is presented, where the Vo is identified as the principle site for $mathrm{Ag}^{+}$ reduction. The $mathrm{Ag}^{+}$ interstitial is energetically favored at the Fermi energies of Ag and Pt, indicating that $mathrm{Ag}^{+}$ ions are not reduced at the Pt electrode via electron tunneling. Instead, $mathrm{Ag}^{+}$ ions bind to Vo forming the $[mathrm{Ag}/mathrm{Vo}]^{+}$ complex, reducing $mathrm{Ag}^{+}$ via charge transfer from the Si atoms in the vacancy. The $[mathrm{Ag}/mathrm{Vo}]^{+}$ complex is then able to trap an electron forming $[mathrm{Ag}/mathrm{Vo}]^{0}$ at the Fermi energy of Pt. This complex is then able to act as a nucleation site for of Ag clustering with the formation of $[mathrm{Ag}2/mathrm{Vo}]^{+}$ which is reduced by the above mechanism.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126841071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452537
C. Ison, R. Spurrier, M. Somintac, R. Asuncion
The demand for higher input/output (I/O) capability, smaller package footprint, low cost, combined with good electrical properties and better electromigration performance has made the copper pillar (CuP) bump an excellent first-level interconnect in flip chip devices built in the recent years. The ability to successfully qualify a new package technology, for this case, CuP flip chip, is dependent on a robust package design, an optimal and stable assembly process, a comprehensive stress plan, and of equal importance, is the development of an electrical test methodology that can detect issues exacerbated by the stress, as well as, the availability of fault isolation methods to rootcause these failures. In this paper, we present the detection of both intrinsic and extrinsic CuP bump interconnect reliability issues exacerbated by temperature cycling through the boundary scan test. The CuP flip chip package-designed electrical and physical failure analyses (FA) used to rootcause the failures were presented. Assembly process improvements to address the root cause of the extrinsic failure modes, as well as interconnect design improvements, to eliminate the contribution of the manufacturing process/package design to the intrinsic failure mechanisms reliability testing aims to expose, were also discussed.
{"title":"Detection and Fault Isolation of Elevated Resistive Paths in Copper Pillar (CuP) Flip Chip Package Device","authors":"C. Ison, R. Spurrier, M. Somintac, R. Asuncion","doi":"10.1109/IPFA.2018.8452537","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452537","url":null,"abstract":"The demand for higher input/output (I/O) capability, smaller package footprint, low cost, combined with good electrical properties and better electromigration performance has made the copper pillar (CuP) bump an excellent first-level interconnect in flip chip devices built in the recent years. The ability to successfully qualify a new package technology, for this case, CuP flip chip, is dependent on a robust package design, an optimal and stable assembly process, a comprehensive stress plan, and of equal importance, is the development of an electrical test methodology that can detect issues exacerbated by the stress, as well as, the availability of fault isolation methods to rootcause these failures. In this paper, we present the detection of both intrinsic and extrinsic CuP bump interconnect reliability issues exacerbated by temperature cycling through the boundary scan test. The CuP flip chip package-designed electrical and physical failure analyses (FA) used to rootcause the failures were presented. Assembly process improvements to address the root cause of the extrinsic failure modes, as well as interconnect design improvements, to eliminate the contribution of the manufacturing process/package design to the intrinsic failure mechanisms reliability testing aims to expose, were also discussed.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126426681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452611
L. Ying, Walter Juerzen, C. C. Fei
In this study, flakes were analysed using several imaging tools including optical scope, SEM & TEM which were complemented with EDX analysis for elemental investigation of the flakes. Flakes formed on copper bond pad after flux cleaning process were characterized due to the fact that there were very few studies found in current literature. With in-depth analysis results interpretation of each method, a cross sectional schematic was proposed illustrating the interaction of flake on copper bond pad after flux cleaning process. Based on SEM & TEM analysis results, no evidence of IMC formation of the flake to copper bond pad was reported. From this flake characterization study, it was recommended to the assembly process experts to reduce or eliminate flakes formation on bond pad surface after flux cleaning process as accumulation of flakes on bond pad's surface would endanger robust wire bonding and also good adhesion quality and reliability assurance of semiconductor product in the long run.
{"title":"Characterization of Flakes on Copper Bond Pad after Flux Cleaning Process","authors":"L. Ying, Walter Juerzen, C. C. Fei","doi":"10.1109/IPFA.2018.8452611","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452611","url":null,"abstract":"In this study, flakes were analysed using several imaging tools including optical scope, SEM & TEM which were complemented with EDX analysis for elemental investigation of the flakes. Flakes formed on copper bond pad after flux cleaning process were characterized due to the fact that there were very few studies found in current literature. With in-depth analysis results interpretation of each method, a cross sectional schematic was proposed illustrating the interaction of flake on copper bond pad after flux cleaning process. Based on SEM & TEM analysis results, no evidence of IMC formation of the flake to copper bond pad was reported. From this flake characterization study, it was recommended to the assembly process experts to reduce or eliminate flakes formation on bond pad surface after flux cleaning process as accumulation of flakes on bond pad's surface would endanger robust wire bonding and also good adhesion quality and reliability assurance of semiconductor product in the long run.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122495089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452565
N. Chinone, Yasuo Cho
The local deep level transient spectroscopy, which measures traps with high lateral resolution using sharp tip, was investigated as functions of DC bias. The results showed that the physical origin which was detected by local-DLTS was mainly interface trap. Furthermore, two-dimensional (2D) quantitative profiling of interface traps as a function of time constant was demonstrated. Comparison between images of different time constant revealed that interface traps with different time constant had different lateral distribution, which suggests that 2D distribution of interface traps depends on their energy level. These results show that local-DLTsis promising for microscopic investigation of interface traps.
{"title":"Quantitative Imaging of MOS Interface Trap Distribution by Using Local Deep Level Transient Spectroscopy","authors":"N. Chinone, Yasuo Cho","doi":"10.1109/IPFA.2018.8452565","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452565","url":null,"abstract":"The local deep level transient spectroscopy, which measures traps with high lateral resolution using sharp tip, was investigated as functions of DC bias. The results showed that the physical origin which was detected by local-DLTS was mainly interface trap. Furthermore, two-dimensional (2D) quantitative profiling of interface traps as a function of time constant was demonstrated. Comparison between images of different time constant revealed that interface traps with different time constant had different lateral distribution, which suggests that 2D distribution of interface traps depends on their energy level. These results show that local-DLTsis promising for microscopic investigation of interface traps.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115896772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452612
Y. Shen, Krishnan Y Ogaspari, I. C. Lam Tay, Jie Zhu, Z. Mo
In this paper, we demonstrate the various applications of the ETEM Si plasmon imaging technique in semiconductor failure analysis. The mechanism of the plasmon imaging will be discussed briefly, then followed by four case studies. The capability of Si plasmon imaging to distinguish the silicon oxide (e.g. gate oxide) and the silicon materials (e.g. poly gate and substrate) is its key advantage over the conventional imaging techniques. Si plasmon imaging not only can identify the defective residues but also can be performed at high magnification to investigate the gate oxide and its interfaces with poly or substrate.
{"title":"Application of Si Plasmon Imaging in Semiconductor Failure Analysis","authors":"Y. Shen, Krishnan Y Ogaspari, I. C. Lam Tay, Jie Zhu, Z. Mo","doi":"10.1109/IPFA.2018.8452612","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452612","url":null,"abstract":"In this paper, we demonstrate the various applications of the ETEM Si plasmon imaging technique in semiconductor failure analysis. The mechanism of the plasmon imaging will be discussed briefly, then followed by four case studies. The capability of Si plasmon imaging to distinguish the silicon oxide (e.g. gate oxide) and the silicon materials (e.g. poly gate and substrate) is its key advantage over the conventional imaging techniques. Si plasmon imaging not only can identify the defective residues but also can be performed at high magnification to investigate the gate oxide and its interfaces with poly or substrate.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115378809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452610
J. Budroweit, M. Sznajder
Software-Defined Radios (SDR) are commonly used in state-of-the-art radio systems and are already well established in the space industry. A SDR usually describes the signal processing of a radio application in software and is often implemented into Field Programmable Gate Arrays (FPGA) or Digital Signal Processors (DSP). Most RF front-ends are strictly specified and realized for an executed application and are thus not re-configurable. With the release of new Radio Frequency Integrated Circuit (RFIC) devices, a significant portion of RF front end specifications have become programmable and alterable. This paper presents the use case and selected radiation test results of such RFIC technologies for small satellite radio applications, primary designed for low earth orbit (LEO) missions.
{"title":"Total Ionizing Dose Effects on a Highly Integrated RF Transceiver for Small Satellite Radio Applications in Low Earth Orbit","authors":"J. Budroweit, M. Sznajder","doi":"10.1109/IPFA.2018.8452610","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452610","url":null,"abstract":"Software-Defined Radios (SDR) are commonly used in state-of-the-art radio systems and are already well established in the space industry. A SDR usually describes the signal processing of a radio application in software and is often implemented into Field Programmable Gate Arrays (FPGA) or Digital Signal Processors (DSP). Most RF front-ends are strictly specified and realized for an executed application and are thus not re-configurable. With the release of new Radio Frequency Integrated Circuit (RFIC) devices, a significant portion of RF front end specifications have become programmable and alterable. This paper presents the use case and selected radiation test results of such RFIC technologies for small satellite radio applications, primary designed for low earth orbit (LEO) missions.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115619156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452512
Akeel Nazakat, Li Yungui, Renee Liu, Vincent Chew
Static curve trace is an essential test method to discover parametric damage on a signal without adding stimulus to an electronic component, it is relatively quick process, and resembling to a detailed continuity test. Yet, its drawback comes when pad signal that we measured, especially VDD power line, routed only at specific or outer pad circuitries, leaving various internal untested circuits within the integrated circuit. This consequence in actual defect site cannot be detected in certain areas. A novel approach to combine layout circuitry study and focus ion beam (FIB) edit are used to create additional power (VDD) to this untested internal circuits to have an extensive characterization of failure mode coupled with fault localization techniques. This paper demonstrates the effectiveness of this method with low IDDQ leakage failure analysis.
{"title":"Novel Techniques of FIB Edit on VDD Routing in Internal Circuit for IDDQ Leakage Failure Analysis","authors":"Akeel Nazakat, Li Yungui, Renee Liu, Vincent Chew","doi":"10.1109/IPFA.2018.8452512","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452512","url":null,"abstract":"Static curve trace is an essential test method to discover parametric damage on a signal without adding stimulus to an electronic component, it is relatively quick process, and resembling to a detailed continuity test. Yet, its drawback comes when pad signal that we measured, especially VDD power line, routed only at specific or outer pad circuitries, leaving various internal untested circuits within the integrated circuit. This consequence in actual defect site cannot be detected in certain areas. A novel approach to combine layout circuitry study and focus ion beam (FIB) edit are used to create additional power (VDD) to this untested internal circuits to have an extensive characterization of failure mode coupled with fault localization techniques. This paper demonstrates the effectiveness of this method with low IDDQ leakage failure analysis.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"264 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114470666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：