Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452546
Sheng-Min Chen, C. Tseng, Kuan-Chieh Huang
In semiconductors, when the F concentration is high, the F atom on the bond pad surface has a higher risk of causing pad corrosion, jeopardizing the bonding process, and causing reliability problems. Therefore, occurrence of F atom on the pad surface should be minimized. In order to ensure the quality, F-concentration pad surface test is important. General F concentration analysis uses the AES analysis method. However, AES is a semi-quantitative instrument, which means that if one sample is analyzed multiple times, a fluctuation in test results can be observed. This fluctuation can lead to misjudgment of data. Due to machine instability and process instability, even tiny fluctuations can interfere with each other. Thus, in order to effectively clarify minor fluctuation problems, correct action is crucial for wafer manufacturing. This article proposes a suitable range to effectively judge the AES data and use the SPC (Statistical Process Control) method to track it.
{"title":"Prevent Auger Analysis Misjudgment on Bond Pad Surface Element Concentration in the SPC Method","authors":"Sheng-Min Chen, C. Tseng, Kuan-Chieh Huang","doi":"10.1109/IPFA.2018.8452546","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452546","url":null,"abstract":"In semiconductors, when the F concentration is high, the F atom on the bond pad surface has a higher risk of causing pad corrosion, jeopardizing the bonding process, and causing reliability problems. Therefore, occurrence of F atom on the pad surface should be minimized. In order to ensure the quality, F-concentration pad surface test is important. General F concentration analysis uses the AES analysis method. However, AES is a semi-quantitative instrument, which means that if one sample is analyzed multiple times, a fluctuation in test results can be observed. This fluctuation can lead to misjudgment of data. Due to machine instability and process instability, even tiny fluctuations can interfere with each other. Thus, in order to effectively clarify minor fluctuation problems, correct action is crucial for wafer manufacturing. This article proposes a suitable range to effectively judge the AES data and use the SPC (Statistical Process Control) method to track it.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131866139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452492
O. Amster, K. Rubin, Yongliang Yang, D. Iyer, A. Messinger, R. Crowder
Two doped semiconductor samples are measured using probe-based Scanning Microwave Impedance Microscopy (sMIM). One is a plan-view polished CMOS image sensor and the other is a cross-section polished power device. Both samples are imaged with sMIM using two different approaches: the first using a dual pass method with dC/dV images acquired simultaneously with sMIM during the first pass in contact mode, and the second pass at a fixed offset from the surface. The second method uses a non-resonant mode where C- V are acquired at specific lateral locations. The C- V curves are used to determine polarity compared to dC/dV and also to distinguish p-n junctions, characterize doping concentration, and build images at constant DC values to discern subtle changes not evident in traditional SCM imaging.
{"title":"Nano C-V imaging of Semiconductor Devices with Scanning Microwave Impedance Microscopy","authors":"O. Amster, K. Rubin, Yongliang Yang, D. Iyer, A. Messinger, R. Crowder","doi":"10.1109/IPFA.2018.8452492","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452492","url":null,"abstract":"Two doped semiconductor samples are measured using probe-based Scanning Microwave Impedance Microscopy (sMIM). One is a plan-view polished CMOS image sensor and the other is a cross-section polished power device. Both samples are imaged with sMIM using two different approaches: the first using a dual pass method with dC/dV images acquired simultaneously with sMIM during the first pass in contact mode, and the second pass at a fixed offset from the surface. The second method uses a non-resonant mode where C- V are acquired at specific lateral locations. The C- V curves are used to determine polarity compared to dC/dV and also to distinguish p-n junctions, characterize doping concentration, and build images at constant DC values to discern subtle changes not evident in traditional SCM imaging.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134498275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper describes as integrated technique of Electro Optical Frequency Mapping (EOFM) and Electro Optical Probing (EOP) to localize open failure mode with traditional FA analysis approach. The technique was performed in analog devices on advanced SOI-based circuits. Two case studies were presented to demonstrate on how the newly introduced fault localization techniques work. These techniques can help to isolate or narrow down the suspected failing components.
{"title":"Integrating EOP/EOFM as a Complimentary Localization Technique for Open Via/Contact","authors":"Nutthapon Jandee, Damrong Korbsrisawat, Ferdie Paulino","doi":"10.1109/IPFA.2018.8452501","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452501","url":null,"abstract":"The paper describes as integrated technique of Electro Optical Frequency Mapping (EOFM) and Electro Optical Probing (EOP) to localize open failure mode with traditional FA analysis approach. The technique was performed in analog devices on advanced SOI-based circuits. Two case studies were presented to demonstrate on how the newly introduced fault localization techniques work. These techniques can help to isolate or narrow down the suspected failing components.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134089651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452544
C. T. Chua, Q. Liu, S. Chef, K. Sanchez, P. Pcrdu, C. Gan
Picosecond pulsed laser, customarily perceived to offer advantages of flexibility and ease of testing over heavy ion particle accelerator test, was conducted on a chain of inverters during Single Event Effect (SEE) evaluation. In this paper, we report on the unexpected permanent damage induced by 1064 nm pulsed laser on test structures fabricated with 65 nm bulk CMOS process technology. Light emission microscopy (EMMI) localized hotspots within the area previously scanned by the pulsed laser. Electro Optical Frequency Mapping (EOFM) verified the undesired termination of signal propagation along the chain of inverters while Electro Optical Probing (EOP) confirmed the unexpected phase change and eventual loss of the output signal waveform. Focused Ion Beam (FIB), Transmission Microscopy (TEM) and Energy Dispersive X-ray spectroscopy (EDX) confirmed the physical failure and identified nickel as the diffusing species. This paper aims to advise caution to the research communities (both space radiation and optical failure analysis) in employing similar laser test technique and highlights the need to define the safe operating region of such technique, especially for emerging technology nodes.
{"title":"Failure Analysis of Damages on Advanced Technologies Induced by Picosecond Pulsed Laser During Space Radiation SEE Testing","authors":"C. T. Chua, Q. Liu, S. Chef, K. Sanchez, P. Pcrdu, C. Gan","doi":"10.1109/IPFA.2018.8452544","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452544","url":null,"abstract":"Picosecond pulsed laser, customarily perceived to offer advantages of flexibility and ease of testing over heavy ion particle accelerator test, was conducted on a chain of inverters during Single Event Effect (SEE) evaluation. In this paper, we report on the unexpected permanent damage induced by 1064 nm pulsed laser on test structures fabricated with 65 nm bulk CMOS process technology. Light emission microscopy (EMMI) localized hotspots within the area previously scanned by the pulsed laser. Electro Optical Frequency Mapping (EOFM) verified the undesired termination of signal propagation along the chain of inverters while Electro Optical Probing (EOP) confirmed the unexpected phase change and eventual loss of the output signal waveform. Focused Ion Beam (FIB), Transmission Microscopy (TEM) and Energy Dispersive X-ray spectroscopy (EDX) confirmed the physical failure and identified nickel as the diffusing species. This paper aims to advise caution to the research communities (both space radiation and optical failure analysis) in employing similar laser test technique and highlights the need to define the safe operating region of such technique, especially for emerging technology nodes.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134108362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452494
B. Tsai, S. J. Chang, C. S.Ho, K. Chou, I. Wei, P. Tseng
The effects of silicide-blocked (SAB) oxide and contact etch stop layer (CESL) on the retention characteristic of one-time programming (OTP) nonvolatile memory (NVM) are experimentally evaluated through various deposition process conditions. The OTP retention is characterized after a baking condition of 250°C for 4 hrs. Our results suggest the NH3 and SiH4gas base deposition process effectively make improvements on OTP data retention. And the thicker the SAB film, the better the data retention.
{"title":"The OTP Data Retention Improvement on CESL and SAB Film Scheme","authors":"B. Tsai, S. J. Chang, C. S.Ho, K. Chou, I. Wei, P. Tseng","doi":"10.1109/IPFA.2018.8452494","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452494","url":null,"abstract":"The effects of silicide-blocked (SAB) oxide and contact etch stop layer (CESL) on the retention characteristic of one-time programming (OTP) nonvolatile memory (NVM) are experimentally evaluated through various deposition process conditions. The OTP retention is characterized after a baking condition of 250°C for 4 hrs. Our results suggest the NH3 and SiH4gas base deposition process effectively make improvements on OTP data retention. And the thicker the SAB film, the better the data retention.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115553124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452498
Marek Sikul, K. Novotný, M. Kemmler, A. Rummel
Following the trend of continuous structure downsizing, it is becoming increasingly challenging to perform standard failure analyses. For instance, nanoprobing on sub-14 nm technology nodes requires well-prepared samples, ultra-sharp tips and especially thermal and mechanical stability. Moreover, standard mechanical polishing starts to fail on lower metal layers due to their very small thickness. In this paper we propose a method of site-specific gas-assisted homogeneous delayering followed by in-situ nanoprobing measurement in a single FIB/SEM system.
{"title":"SEM-Based Nanoprobing on In-Situ Delayered Advanced 10 nm Technology Node IC","authors":"Marek Sikul, K. Novotný, M. Kemmler, A. Rummel","doi":"10.1109/IPFA.2018.8452498","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452498","url":null,"abstract":"Following the trend of continuous structure downsizing, it is becoming increasingly challenging to perform standard failure analyses. For instance, nanoprobing on sub-14 nm technology nodes requires well-prepared samples, ultra-sharp tips and especially thermal and mechanical stability. Moreover, standard mechanical polishing starts to fail on lower metal layers due to their very small thickness. In this paper we propose a method of site-specific gas-assisted homogeneous delayering followed by in-situ nanoprobing measurement in a single FIB/SEM system.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115744996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452593
Qu Ruoyuan, Sun Jiajia, Z. Wei, Gong Xin
Based on a failure analysis case of abnormal operating current of an ADC (Analog to Digital Convertor) chip, a step-by-step fault location method is introduced in this paper. The fault is located using this method, and FIB (focused ion beam) technology is involved to verify the accuracy of fault location. Meanwhile, another simulations verification method is adopted, which reveals that the failure reason lies in the reduction of the core capacitance in bandgap start-up circuit caused by inconsistencies of the process. At last, some suggestions are proposed to help fast location in the similar failure and to ensure that this risk can be effectively avoid in the future relevant design.
{"title":"Failure Analysis and Improvement of Bandgap Start-up Circuit by FIB","authors":"Qu Ruoyuan, Sun Jiajia, Z. Wei, Gong Xin","doi":"10.1109/IPFA.2018.8452593","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452593","url":null,"abstract":"Based on a failure analysis case of abnormal operating current of an ADC (Analog to Digital Convertor) chip, a step-by-step fault location method is introduced in this paper. The fault is located using this method, and FIB (focused ion beam) technology is involved to verify the accuracy of fault location. Meanwhile, another simulations verification method is adopted, which reveals that the failure reason lies in the reduction of the core capacitance in bandgap start-up circuit caused by inconsistencies of the process. At last, some suggestions are proposed to help fast location in the similar failure and to ensure that this risk can be effectively avoid in the future relevant design.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124879691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452489
Kuang Yuan Chao, Jeng Hung Pan, H. Chou, Shih Yuan Liu Chong, J. C. Chang, J. Lin, Chee Hong
Laser assisted device alteration (LADA) is a laser-based technique to verify device under test and has been widely used for soft failure debugging. This technique requires the device to be scanned with a laser while it is under active stimulation by the tester. By monitoring test results and scanning laser position, it gives the location of defect and critical path. In the case of complex logic failures in advanced technology nodes, defect localization continues to be a challenge in the failure analysis field. Dynamic electrical failure analysis (D-EFA) techniques and their derivatives can increase efficiency for defect localization techniques. In this paper, several soft failure case studies will be demonstrated by using LADA techniques and further nano-probing results will also be described by physical failure analysis (PFA).
{"title":"Laser Assisted Device Alteration, Efficient Application for Soft Failure Localization on Advanced Node","authors":"Kuang Yuan Chao, Jeng Hung Pan, H. Chou, Shih Yuan Liu Chong, J. C. Chang, J. Lin, Chee Hong","doi":"10.1109/IPFA.2018.8452489","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452489","url":null,"abstract":"Laser assisted device alteration (LADA) is a laser-based technique to verify device under test and has been widely used for soft failure debugging. This technique requires the device to be scanned with a laser while it is under active stimulation by the tester. By monitoring test results and scanning laser position, it gives the location of defect and critical path. In the case of complex logic failures in advanced technology nodes, defect localization continues to be a challenge in the failure analysis field. Dynamic electrical failure analysis (D-EFA) techniques and their derivatives can increase efficiency for defect localization techniques. In this paper, several soft failure case studies will be demonstrated by using LADA techniques and further nano-probing results will also be described by physical failure analysis (PFA).","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"394 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115923566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452536
K. Patel, J. Cottom, M. Bosman, A. Kenyon, A. Shluger
In this study, Density Functional Theory (DFT) calculations were used to model the incorporation and diffusion of Ag in Ag/a-Si02/Pt resistive random-access memory (RRAM) devices. The Ag clustering mechanism is vital for understanding device operation and at this stage is unknown. In this paper an O vacancy (Vo) mediated cluster model is presented, where the Vo is identified as the principle site for $mathrm{Ag}^{+}$ reduction. The $mathrm{Ag}^{+}$ interstitial is energetically favored at the Fermi energies of Ag and Pt, indicating that $mathrm{Ag}^{+}$ ions are not reduced at the Pt electrode via electron tunneling. Instead, $mathrm{Ag}^{+}$ ions bind to Vo forming the $[mathrm{Ag}/mathrm{Vo}]^{+}$ complex, reducing $mathrm{Ag}^{+}$ via charge transfer from the Si atoms in the vacancy. The $[mathrm{Ag}/mathrm{Vo}]^{+}$ complex is then able to trap an electron forming $[mathrm{Ag}/mathrm{Vo}]^{0}$ at the Fermi energy of Pt. This complex is then able to act as a nucleation site for of Ag clustering with the formation of $[mathrm{Ag}2/mathrm{Vo}]^{+}$ which is reduced by the above mechanism.
{"title":"Theoretical Study of Ag Interactions in Amorphous Silica RRAM Devices","authors":"K. Patel, J. Cottom, M. Bosman, A. Kenyon, A. Shluger","doi":"10.1109/IPFA.2018.8452536","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452536","url":null,"abstract":"In this study, Density Functional Theory (DFT) calculations were used to model the incorporation and diffusion of Ag in Ag/a-Si02/Pt resistive random-access memory (RRAM) devices. The Ag clustering mechanism is vital for understanding device operation and at this stage is unknown. In this paper an O vacancy (Vo) mediated cluster model is presented, where the Vo is identified as the principle site for $mathrm{Ag}^{+}$ reduction. The $mathrm{Ag}^{+}$ interstitial is energetically favored at the Fermi energies of Ag and Pt, indicating that $mathrm{Ag}^{+}$ ions are not reduced at the Pt electrode via electron tunneling. Instead, $mathrm{Ag}^{+}$ ions bind to Vo forming the $[mathrm{Ag}/mathrm{Vo}]^{+}$ complex, reducing $mathrm{Ag}^{+}$ via charge transfer from the Si atoms in the vacancy. The $[mathrm{Ag}/mathrm{Vo}]^{+}$ complex is then able to trap an electron forming $[mathrm{Ag}/mathrm{Vo}]^{0}$ at the Fermi energy of Pt. This complex is then able to act as a nucleation site for of Ag clustering with the formation of $[mathrm{Ag}2/mathrm{Vo}]^{+}$ which is reduced by the above mechanism.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126841071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452537
C. Ison, R. Spurrier, M. Somintac, R. Asuncion
The demand for higher input/output (I/O) capability, smaller package footprint, low cost, combined with good electrical properties and better electromigration performance has made the copper pillar (CuP) bump an excellent first-level interconnect in flip chip devices built in the recent years. The ability to successfully qualify a new package technology, for this case, CuP flip chip, is dependent on a robust package design, an optimal and stable assembly process, a comprehensive stress plan, and of equal importance, is the development of an electrical test methodology that can detect issues exacerbated by the stress, as well as, the availability of fault isolation methods to rootcause these failures. In this paper, we present the detection of both intrinsic and extrinsic CuP bump interconnect reliability issues exacerbated by temperature cycling through the boundary scan test. The CuP flip chip package-designed electrical and physical failure analyses (FA) used to rootcause the failures were presented. Assembly process improvements to address the root cause of the extrinsic failure modes, as well as interconnect design improvements, to eliminate the contribution of the manufacturing process/package design to the intrinsic failure mechanisms reliability testing aims to expose, were also discussed.
{"title":"Detection and Fault Isolation of Elevated Resistive Paths in Copper Pillar (CuP) Flip Chip Package Device","authors":"C. Ison, R. Spurrier, M. Somintac, R. Asuncion","doi":"10.1109/IPFA.2018.8452537","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452537","url":null,"abstract":"The demand for higher input/output (I/O) capability, smaller package footprint, low cost, combined with good electrical properties and better electromigration performance has made the copper pillar (CuP) bump an excellent first-level interconnect in flip chip devices built in the recent years. The ability to successfully qualify a new package technology, for this case, CuP flip chip, is dependent on a robust package design, an optimal and stable assembly process, a comprehensive stress plan, and of equal importance, is the development of an electrical test methodology that can detect issues exacerbated by the stress, as well as, the availability of fault isolation methods to rootcause these failures. In this paper, we present the detection of both intrinsic and extrinsic CuP bump interconnect reliability issues exacerbated by temperature cycling through the boundary scan test. The CuP flip chip package-designed electrical and physical failure analyses (FA) used to rootcause the failures were presented. Assembly process improvements to address the root cause of the extrinsic failure modes, as well as interconnect design improvements, to eliminate the contribution of the manufacturing process/package design to the intrinsic failure mechanisms reliability testing aims to expose, were also discussed.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126426681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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