Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452182
G. Tao, R. Koster, A. Romanescu, S. Theeuwen, R. van Dalen, H. Bosch, Tsung-Miau Wang, Shih-Yuan Chen, Y. Jhuang, Yung-Wen Cheng
Lots of studies have been dedicated to NBTI/PBTI in CMOS technologies, where the gate stack is most important. In this paper, we report our study of NBTI/PBTI in LDMOST technologies for RF Power applications. The observed BTI effect is associated to the backend of the processes.
{"title":"Study of Biased Temperature Instabilities in LDMOST technologies","authors":"G. Tao, R. Koster, A. Romanescu, S. Theeuwen, R. van Dalen, H. Bosch, Tsung-Miau Wang, Shih-Yuan Chen, Y. Jhuang, Yung-Wen Cheng","doi":"10.1109/IPFA.2018.8452182","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452182","url":null,"abstract":"Lots of studies have been dedicated to NBTI/PBTI in CMOS technologies, where the gate stack is most important. In this paper, we report our study of NBTI/PBTI in LDMOST technologies for RF Power applications. The observed BTI effect is associated to the backend of the processes.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126926940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452520
H. Younan
IN this paper, the differences between EDS and AES are discussed. One can full understand what limitation of EDS technique is and why AES is better tool to determine F contamination on a normal Al bondpad. During application we cannot directly compare EDS result to AES result as EDS is a bulk analysis technique, while AES is surface analysis technique. For surface contamination analysis, a practice rule should be followed: “EDS clean is not clean” and “Auger clean is clean”. It is fully recommended for us to use AES to analyse and monitor surface F contamination level on a normal Al bondpad.
{"title":"Can We Use EDS to Determine Fluorine Contamination Level on A Normal Al Bondpad?","authors":"H. Younan","doi":"10.1109/IPFA.2018.8452520","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452520","url":null,"abstract":"IN this paper, the differences between EDS and AES are discussed. One can full understand what limitation of EDS technique is and why AES is better tool to determine F contamination on a normal Al bondpad. During application we cannot directly compare EDS result to AES result as EDS is a bulk analysis technique, while AES is surface analysis technique. For surface contamination analysis, a practice rule should be followed: “EDS clean is not clean” and “Auger clean is clean”. It is fully recommended for us to use AES to analyse and monitor surface F contamination level on a normal Al bondpad.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122967295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452499
F. Hui, Xianhu Liang, W. Fang, W. Leong, Haozhe Wang, H. Yang, Yuanyuan Shi, M. A. Villena, J. Kong, M. Lanza
Large-area multilayer hexagonal boron nitride (h-BN) dielectric stacks can be grown on different metallic substrates by chemical vapor deposition (CVD). The high temperatures used during the growth produce the polycrystallization of the metallic substrates (leading to different crystallographic orientations at the surface of each grain), which may influence the catalytic activity of the CVD process on different grains, as well as the properties of the h-BN stacks grown on them. In this work we compare the uniformity of multilayer h-BN dielectric stacks grown via CVD on two different metallic substrates: Pt and Cu. Our study reveals that using Pt substrates leads to h-BN thickness fluctuations from one Pt grain to another, while this effect remarkably reduced when the h-BN is grown on Cu substrates. Therefore, the use of Cu substrates seems to be more convenient for h-BN production and integration at the wafer level.
{"title":"Uniformity of Multilayer Hexagonal Boron Nitride Dielectric Stacks Grown by Chemical Vapor Deposition on Platinum and Copper Substrates","authors":"F. Hui, Xianhu Liang, W. Fang, W. Leong, Haozhe Wang, H. Yang, Yuanyuan Shi, M. A. Villena, J. Kong, M. Lanza","doi":"10.1109/IPFA.2018.8452499","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452499","url":null,"abstract":"Large-area multilayer hexagonal boron nitride (h-BN) dielectric stacks can be grown on different metallic substrates by chemical vapor deposition (CVD). The high temperatures used during the growth produce the polycrystallization of the metallic substrates (leading to different crystallographic orientations at the surface of each grain), which may influence the catalytic activity of the CVD process on different grains, as well as the properties of the h-BN stacks grown on them. In this work we compare the uniformity of multilayer h-BN dielectric stacks grown via CVD on two different metallic substrates: Pt and Cu. Our study reveals that using Pt substrates leads to h-BN thickness fluctuations from one Pt grain to another, while this effect remarkably reduced when the h-BN is grown on Cu substrates. Therefore, the use of Cu substrates seems to be more convenient for h-BN production and integration at the wafer level.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125288205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452574
He Sheng-zong, Wang You-liang, Peng Ze-ya, Zhang Yin, Chen Jin-Tao, Zhu Bin-Rue, Jiang Jian-feng
Power devices are widely used. Due to over burning and incidental destruction, direct failure analysis can't easily identify the real cause of failure. It is an essential technology for the analysis department of power device users to find out the evidence of the failure cause quickly and effectively, and verify it. Taking the application scenario of household appliances as an example, a large number of failure cases of MOSFET, IPM, IGBT for household appliances are summarized. A typical case set with different defects caused by packaging defects, process manufacturing and insufficient application protection is formed. Corresponding analysis strategies and skills and essentials are established. The summary of these failure cases and methods has a guiding role in the material selection, product design, manufacture and application protection for power devices.
{"title":"Case Study and Application on Failure Analysis for Power Device","authors":"He Sheng-zong, Wang You-liang, Peng Ze-ya, Zhang Yin, Chen Jin-Tao, Zhu Bin-Rue, Jiang Jian-feng","doi":"10.1109/IPFA.2018.8452574","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452574","url":null,"abstract":"Power devices are widely used. Due to over burning and incidental destruction, direct failure analysis can't easily identify the real cause of failure. It is an essential technology for the analysis department of power device users to find out the evidence of the failure cause quickly and effectively, and verify it. Taking the application scenario of household appliances as an example, a large number of failure cases of MOSFET, IPM, IGBT for household appliances are summarized. A typical case set with different defects caused by packaging defects, process manufacturing and insufficient application protection is formed. Corresponding analysis strategies and skills and essentials are established. The summary of these failure cases and methods has a guiding role in the material selection, product design, manufacture and application protection for power devices.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114067594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452508
J. Gambino
For Moore's law technology qualifications, the Back-End of Line (BEOL) reliability focuses on electromigration, stress migration, Time Dependent Dielectric Breakdown (TDDB), and Chip-Package Interaction (CPI). For More-Than-Moore technology qualifications, some additional BEOL reliability tests are often required. Power semiconductors used in automotive applications are exposed to higher temperatures and higher currents than devices used in consumer products. Hence, the BEOL reliability includes power-temperature cycling stresses, high current pulsed stresses, high temperature storage above 200°C, and unique package connections such as 2mil Cu wirebonds or Cu clips.
{"title":"BEOL Reliability for More- Than-Moore Devices","authors":"J. Gambino","doi":"10.1109/IPFA.2018.8452508","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452508","url":null,"abstract":"For Moore's law technology qualifications, the Back-End of Line (BEOL) reliability focuses on electromigration, stress migration, Time Dependent Dielectric Breakdown (TDDB), and Chip-Package Interaction (CPI). For More-Than-Moore technology qualifications, some additional BEOL reliability tests are often required. Power semiconductors used in automotive applications are exposed to higher temperatures and higher currents than devices used in consumer products. Hence, the BEOL reliability includes power-temperature cycling stresses, high current pulsed stresses, high temperature storage above 200°C, and unique package connections such as 2mil Cu wirebonds or Cu clips.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122068862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452589
Ikuo Arata, Masanori Kobayashi, S. Matsuda, H. Terada
The solid immersion lens (SIL) has been critical for extending the useful life of optical microscopy for semiconductor failure analysis. By matching the refractive index of the Si device under test (DUT) the Si SIL allows the collection of light at wide angles that would otherwise be internally reflected inside the DUT, thereby increasing numerical aperture and resolution by a factor of 3.5. Increasingly smaller semiconductor feature sizes require shorter laser wavelengths to get adequate resolution from optical microscopy [1] - [3]. Si SILs present limitations for shorter wavelengths since they do not transmit light below 1100nm. A replacement material is needed with high transmittance at shorter wavelengths and a high refractive index close to that of Si (~3.5). This paper focuses on GaP (Gallium Phosphide) with good transparency down to 600nm and high refractive index (3.3), but traditionally poorer optical quality than Si. We optically characterized GaP substrates and fabricated GaP SILs from those substrates for use in a confocal laser scanning microscope and were able to achieve the theoretical resolution limit when coupled with an optimized backing objective.
{"title":"Evaluation of Gallium Phosphide Substrate for Solid Immersion Lens","authors":"Ikuo Arata, Masanori Kobayashi, S. Matsuda, H. Terada","doi":"10.1109/IPFA.2018.8452589","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452589","url":null,"abstract":"The solid immersion lens (SIL) has been critical for extending the useful life of optical microscopy for semiconductor failure analysis. By matching the refractive index of the Si device under test (DUT) the Si SIL allows the collection of light at wide angles that would otherwise be internally reflected inside the DUT, thereby increasing numerical aperture and resolution by a factor of 3.5. Increasingly smaller semiconductor feature sizes require shorter laser wavelengths to get adequate resolution from optical microscopy [1] - [3]. Si SILs present limitations for shorter wavelengths since they do not transmit light below 1100nm. A replacement material is needed with high transmittance at shorter wavelengths and a high refractive index close to that of Si (~3.5). This paper focuses on GaP (Gallium Phosphide) with good transparency down to 600nm and high refractive index (3.3), but traditionally poorer optical quality than Si. We optically characterized GaP substrates and fabricated GaP SILs from those substrates for use in a confocal laser scanning microscope and were able to achieve the theoretical resolution limit when coupled with an optimized backing objective.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114983908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452516
Aniketha Udupa Kuppar, Xu Zeng, C. Ng, Y. J. Lim, H. Yao, E. J. Khor, R. Chockalingam, Juan Boon Tan
Stress Induced Voiding of a nose type Single Via is studied. Typical nose type single via stress voiding structure has top and bottom wide metal plates originating from the pads and tapering to a narrow metal line connected by single via enabling the Kelvin type of measurements. In this paper, effect of removal of either of the top or bottom metal plates on the formation of stress induced voids at an elevated temperature is studied and results are characterized. It is found from the study that presence of bottom metal plates is vital for the void accumulation resulting in stress voiding failure.
{"title":"A Study on Effect of Top and Bottom Metal Plates on Stress Induced Voiding of Nose Type Single Via Structure","authors":"Aniketha Udupa Kuppar, Xu Zeng, C. Ng, Y. J. Lim, H. Yao, E. J. Khor, R. Chockalingam, Juan Boon Tan","doi":"10.1109/IPFA.2018.8452516","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452516","url":null,"abstract":"Stress Induced Voiding of a nose type Single Via is studied. Typical nose type single via stress voiding structure has top and bottom wide metal plates originating from the pads and tapering to a narrow metal line connected by single via enabling the Kelvin type of measurements. In this paper, effect of removal of either of the top or bottom metal plates on the formation of stress induced voids at an elevated temperature is studied and results are characterized. It is found from the study that presence of bottom metal plates is vital for the void accumulation resulting in stress voiding failure.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115175998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452174
I. Vogt, R. Leihkauf, T. Nakamura, C. Boit
We present various results of electro-optical frequency mapping (EOFM) simulations and experiments on different pn-junctions. The results give detailed insight into EOFM signal causes (also parasitic) present in modern ICs, Over 350 EOFM simulations draw a precise quantitative picture of EOFM signal dependence on temperature, doping levels, voltage and laser bandwidth. Additional analysis of the reflected laser-light allows for an estimation and improvement of EOFM signal quality dependent on substrate thickness and interference pattern.
{"title":"New Laser Voltage Signal Insights from EOFM Simulations and Measurements on different pn-junctions","authors":"I. Vogt, R. Leihkauf, T. Nakamura, C. Boit","doi":"10.1109/IPFA.2018.8452174","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452174","url":null,"abstract":"We present various results of electro-optical frequency mapping (EOFM) simulations and experiments on different pn-junctions. The results give detailed insight into EOFM signal causes (also parasitic) present in modern ICs, Over 350 EOFM simulations draw a precise quantitative picture of EOFM signal dependence on temperature, doping levels, voltage and laser bandwidth. Additional analysis of the reflected laser-light allows for an estimation and improvement of EOFM signal quality dependent on substrate thickness and interference pattern.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115342803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452551
C. Hartfield, C. Schmidt, A. Gu, S. Kelly
X-ray imaging has been a key non-destructive analysis method for electronic packages and printed circuit boards (PCB) for over two decades. Applications such as artificial intelligence (AI), 5G, high-performance computing and internet-of-things (IOT) mandate higher IO density and 3D scaling at the device, package and system levels, thereby increasing the need for nondestructive imaging at high resolution and preferably in 3D. The first lab-based submicron X-ray microscopes (XRM) using focused-optics emerged in 2000 [1], based on components from synchrotron technology. This innovation enabled high-resolution 3D X-ray tomography on full packages. Since then a new type of XRM architecture in a lab-based instrument has emerged with spatial resolution in the tens of nanometers, when using a suitably prepared sample. When adopted in failure analysis (FA) workflows, submicron and nanoscale XRM enable successful failure analysis outcomes from PCB to die BEOL levels, even in complex samples. In addition, the unique capability to nondestructively acquire 3D images at high resolution is now driving the development of submicron XRM as a measurement solution offering rich 3D data and statistics to support advanced package development and manufacturing. XRM is continuing to grow in importance as the electronics industry develops more complex and integrated structures across all levels of the supply chain.
{"title":"From PCB to BEOL: 3D X-Ray Microscopy for Advanced Semiconductor Packaging","authors":"C. Hartfield, C. Schmidt, A. Gu, S. Kelly","doi":"10.1109/IPFA.2018.8452551","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452551","url":null,"abstract":"X-ray imaging has been a key non-destructive analysis method for electronic packages and printed circuit boards (PCB) for over two decades. Applications such as artificial intelligence (AI), 5G, high-performance computing and internet-of-things (IOT) mandate higher IO density and 3D scaling at the device, package and system levels, thereby increasing the need for nondestructive imaging at high resolution and preferably in 3D. The first lab-based submicron X-ray microscopes (XRM) using focused-optics emerged in 2000 [1], based on components from synchrotron technology. This innovation enabled high-resolution 3D X-ray tomography on full packages. Since then a new type of XRM architecture in a lab-based instrument has emerged with spatial resolution in the tens of nanometers, when using a suitably prepared sample. When adopted in failure analysis (FA) workflows, submicron and nanoscale XRM enable successful failure analysis outcomes from PCB to die BEOL levels, even in complex samples. In addition, the unique capability to nondestructively acquire 3D images at high resolution is now driving the development of submicron XRM as a measurement solution offering rich 3D data and statistics to support advanced package development and manufacturing. XRM is continuing to grow in importance as the electronics industry develops more complex and integrated structures across all levels of the supply chain.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122523419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452504
A. Alimin, S. Hatta, N. Soin
In this paper, the influence of design parameters on hot carrier injection (HCI) degradation of shallow trench isolation (STI) based n-channel laterally diffused metal-oxide-semiconductor (n-LDMOS) transistors using TCAD simulation was analyzed. The design parameters involved in this study were STI depth, gate oxide thickness as well as p-substrate doping concentration simulated based on the stress-measure testing technique. The effect on the device parameters such as on-resistance (Ron), impact ionization rate, and interface traps concentration had been investigated and explained in detail. From the results obtained, it is found that larger STI depth and larger gate oxide thickness shows lower HCI effect. The Ron degradation is observed to reduce by 52.2% and 79.76% when the STI depth is increased to $0.3 mu mathrm{m}$ and $0.4 mu mathrm{m}$ respectively for 10ks stress time. It is also observed that higher p-substrate doping concentration exhibits higher HCI degradation.
利用TCAD仿真分析了设计参数对基于浅沟槽隔离(STI)的n沟道横向扩散金属氧化物半导体(n-LDMOS)晶体管热载流子注入(HCI)退化的影响。本研究涉及的设计参数是STI深度，栅极氧化物厚度以及基于应力测量测试技术模拟的p-衬底掺杂浓度。对器件参数如导通电阻(Ron)、冲击电离率和界面阱浓度的影响进行了详细的研究和解释。结果表明，较大的STI深度和较大的栅极氧化物厚度对HCI的影响较小。当STI深度分别增加到$0.3 mu mathm {m}$和$0.4 mu mathm {m}$时，10ks应力时间下，Ron降解率分别降低了52.2%和79.76%。p-底物掺杂浓度越高，HCI降解越明显。
{"title":"Influence of Design Considerations on Hot Carrier Injection Degradation of STI-based LDMOS Transistors","authors":"A. Alimin, S. Hatta, N. Soin","doi":"10.1109/IPFA.2018.8452504","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452504","url":null,"abstract":"In this paper, the influence of design parameters on hot carrier injection (HCI) degradation of shallow trench isolation (STI) based n-channel laterally diffused metal-oxide-semiconductor (n-LDMOS) transistors using TCAD simulation was analyzed. The design parameters involved in this study were STI depth, gate oxide thickness as well as p-substrate doping concentration simulated based on the stress-measure testing technique. The effect on the device parameters such as on-resistance (Ron), impact ionization rate, and interface traps concentration had been investigated and explained in detail. From the results obtained, it is found that larger STI depth and larger gate oxide thickness shows lower HCI effect. The Ron degradation is observed to reduce by 52.2% and 79.76% when the STI depth is increased to $0.3 mu mathrm{m}$ and $0.4 mu mathrm{m}$ respectively for 10ks stress time. It is also observed that higher p-substrate doping concentration exhibits higher HCI degradation.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"202 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116171523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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