Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210142
Doug Kwan, Jing Yu, B. Janakiraman
Smart handheld devices are ubiquitous today and software plays an important role on them. Therefore a compiler and related tools can improve devices by generating efficient, compact and secure code. In this paper, we share our experience of applying various compilation techniques at Google to improve software running on smart handheld devices, using our mobile platforms as examples. At Google we use the GNU toolchain for generating code on different platforms and for conducting compiler research and development. We have developed new techniques, added features and functionality in the GNU tools. Some of these results are now used for smart handheld devices.
{"title":"Google's C/C++ toolchain for smart handheld devices","authors":"Doug Kwan, Jing Yu, B. Janakiraman","doi":"10.1109/VLSI-TSA.2012.6210142","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210142","url":null,"abstract":"Smart handheld devices are ubiquitous today and software plays an important role on them. Therefore a compiler and related tools can improve devices by generating efficient, compact and secure code. In this paper, we share our experience of applying various compilation techniques at Google to improve software running on smart handheld devices, using our mobile platforms as examples. At Google we use the GNU toolchain for generating code on different platforms and for conducting compiler research and development. We have developed new techniques, added features and functionality in the GNU tools. Some of these results are now used for smart handheld devices.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134640749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210166
F. Gámiz, N. Rodriguez, S. Cristoloveanu
The new concept of Triple-Gate 1T-DRAM cell features N/P body partition that enables the physical separation of hole storage and electron current. The hole concentration controls the partial or full depletion of the N-core. The cell is compatible with ultimate scaling and shows attractive performance (long retention, wide memory window, simple programming, nondestructive reading, and very low-power operation) for embedded systems.
{"title":"A 20nm low-power triple-gate multibody 1T-DRAM cell","authors":"F. Gámiz, N. Rodriguez, S. Cristoloveanu","doi":"10.1109/VLSI-TSA.2012.6210166","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210166","url":null,"abstract":"The new concept of Triple-Gate 1T-DRAM cell features N/P body partition that enables the physical separation of hole storage and electron current. The hole concentration controls the partial or full depletion of the N-core. The cell is compatible with ultimate scaling and shows attractive performance (long retention, wide memory window, simple programming, nondestructive reading, and very low-power operation) for embedded systems.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121295181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210141
Tim Whitfield
Driven by increased complexity, cost and shorter time to market, subsystem re-use is now adopted by most of the major semiconductor companies. This presentation will show a “2012 Compute Subsystem” for application processors targeting low power, screen based devices such as smartphones, and tablets, giving a detailed breakdown of the key hardware and software technology employed. The presentation will outline the development decisions made for the 2012 compute subsystem using Cortex-A15 and Mali-600 processors.
{"title":"The 2012 ARM powered compute subsystem - delivering the smart handheld platform","authors":"Tim Whitfield","doi":"10.1109/VLSI-TSA.2012.6210141","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210141","url":null,"abstract":"Driven by increased complexity, cost and shorter time to market, subsystem re-use is now adopted by most of the major semiconductor companies. This presentation will show a “2012 Compute Subsystem” for application processors targeting low power, screen based devices such as smartphones, and tablets, giving a detailed breakdown of the key hardware and software technology employed. The presentation will outline the development decisions made for the 2012 compute subsystem using Cortex-A15 and Mali-600 processors.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122902448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210149
X. Gong, Zhu Zhu, E. Kong, Ran Cheng, S. Subramanian, K. Goh, Y. Yeo
We report the demonstration of an ultra-thin-body In0.7Ga0.3As-on-nothing N-MOSFET where a self-aligned cavity is formed right beneath the channel layer. Self-aligned Pd-InGaAs source/drain (S/D) contacts were integrated. The gate length LG of 130 nm is the smallest achieved with self-aligned contacts. With effective reduction of subsurface leakage current by the III-V-on-nothing device structure, DIBL of 248 mV/V and SS of 135 mV/decade were achieved.
{"title":"Ultra-thin-body In0.7Ga0.3As-on-nothing N-MOSFET with Pd-InGaAs source/drain contacts enabled by a new self-aligned cavity formation technology","authors":"X. Gong, Zhu Zhu, E. Kong, Ran Cheng, S. Subramanian, K. Goh, Y. Yeo","doi":"10.1109/VLSI-TSA.2012.6210149","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210149","url":null,"abstract":"We report the demonstration of an ultra-thin-body In0.7Ga0.3As-on-nothing N-MOSFET where a self-aligned cavity is formed right beneath the channel layer. Self-aligned Pd-InGaAs source/drain (S/D) contacts were integrated. The gate length LG of 130 nm is the smallest achieved with self-aligned contacts. With effective reduction of subsurface leakage current by the III-V-on-nothing device structure, DIBL of 248 mV/V and SS of 135 mV/decade were achieved.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123398315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210116
Ming-Fu Tsai, B. K. Lu, M. Fan, C. Pao, Yin-Nien Chen, V. Hu, P. Su, C. Chuang
We propose a methodology to simulate realistic 2D Line Edge Roughness (LER) pattern for NanoWire (NW) MOSFETs in TCAD platform. This approach predicts the device characteristic and variations including Vth, Ion and Subthreshold Swing (S.S.) fluctuations more accurately compared with prior literature considering two types of primarily 1D NW geometry variation [1]. Based on the proposed simulation approach, we carry out a comprehensive analysis using 3D atomistic TCAD and mixed-mode Monte Carlo simulations on the impacts of Wire-LER on the variability of NW MOSFET device characteristics, stability of 6T SRAM operating in subthreshold region and logic circuits. The results are extensively compared with previous approaches to illustrate the deficiency of modeling and predictions based on 1D NW geometry variation.
{"title":"Impacts of wire-LER on Nanowire MOSFET devices, subthreshold SRAM and logic circuits","authors":"Ming-Fu Tsai, B. K. Lu, M. Fan, C. Pao, Yin-Nien Chen, V. Hu, P. Su, C. Chuang","doi":"10.1109/VLSI-TSA.2012.6210116","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210116","url":null,"abstract":"We propose a methodology to simulate realistic 2D Line Edge Roughness (LER) pattern for NanoWire (NW) MOSFETs in TCAD platform. This approach predicts the device characteristic and variations including Vth, Ion and Subthreshold Swing (S.S.) fluctuations more accurately compared with prior literature considering two types of primarily 1D NW geometry variation [1]. Based on the proposed simulation approach, we carry out a comprehensive analysis using 3D atomistic TCAD and mixed-mode Monte Carlo simulations on the impacts of Wire-LER on the variability of NW MOSFET device characteristics, stability of 6T SRAM operating in subthreshold region and logic circuits. The results are extensively compared with previous approaches to illustrate the deficiency of modeling and predictions based on 1D NW geometry variation.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132247062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210172
Y. Tong, B. Liu, P. S. Lim, Qian Zhou, Y. Yeo
We report the demonstration of a new effective Schottky barrier height (ΦBn) reduction technology for NiGe/n-type Germanium (n-Ge) contacts using ion implantation of selenium (Se) or sulfur (S) followed by their segregation at the NiGe/n-Ge interface. Both Se and S are found to segregate at NiGe/n-Ge interface after germanide formation, giving ΦBn as low as ~0.1 eV. Nickel monogermanide was formed for samples annealed at 350 °C for 30 s. In addition, both Se and S implants cause surface amorphization which possibly leads to improved uniformity of NiGe thickness.
{"title":"Novel selenium implant and segregation for reduction of effective Schottky barrier height in NiGe/n-Ge contacts","authors":"Y. Tong, B. Liu, P. S. Lim, Qian Zhou, Y. Yeo","doi":"10.1109/VLSI-TSA.2012.6210172","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210172","url":null,"abstract":"We report the demonstration of a new effective Schottky barrier height (ΦBn) reduction technology for NiGe/n-type Germanium (n-Ge) contacts using ion implantation of selenium (Se) or sulfur (S) followed by their segregation at the NiGe/n-Ge interface. Both Se and S are found to segregate at NiGe/n-Ge interface after germanide formation, giving ΦBn as low as ~0.1 eV. Nickel monogermanide was formed for samples annealed at 350 °C for 30 s. In addition, both Se and S implants cause surface amorphization which possibly leads to improved uniformity of NiGe thickness.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132510320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210169
M. Fan, V. Hu, Yin-Nien Chen, P. Su, C. Chuang
This paper investigates the viability and compares the merits of small-signal differential sensing and large-signal single-ended sensing scheme for FinFET SRAM under fin Line-Edge-Roughness (fin LER) and Work-Function-Variation (WFV). The local random variation of selected cell, leakage (and its variation) from unselected cells on the selected Bit-Line (BL), and variation of sense amplifier offset voltage (for differential sensing) and trip voltage (for large-signal sensing) are considered simultaneously at subthreshold (Vdd=0.4V) and superthreshold (Vdd=1.0V) regions. For differential sensing, the subthreshold sensing margin is severely degraded by the variation in Bitline voltage and sufficient time before enabling the sense amplifier is required to improve the limited margin. For large-signal sensing scheme, we show that there is large disparity between the sense “0” margin and sense “1” margin with the significantly worse sense “0” margin limiting the affordable number of cells per Bitline. The possibility of using double-fin PFET in large-signal sensing inverter to improve the sense “0” margin is examined, and shown to be of limited benefit, especially for operation in subthreshold region. Compared with BULK CMOS, the superior electrostatic integrity and variability of FinFET enhances/enables the feasibility of differential sensing in subthreshold/superthreshold SRAM applications.
{"title":"Comparison of differential and large-signal sensing scheme for subthreshold/superthreshold FinFET SRAM considering variability","authors":"M. Fan, V. Hu, Yin-Nien Chen, P. Su, C. Chuang","doi":"10.1109/VLSI-TSA.2012.6210169","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210169","url":null,"abstract":"This paper investigates the viability and compares the merits of small-signal differential sensing and large-signal single-ended sensing scheme for FinFET SRAM under fin Line-Edge-Roughness (fin LER) and Work-Function-Variation (WFV). The local random variation of selected cell, leakage (and its variation) from unselected cells on the selected Bit-Line (BL), and variation of sense amplifier offset voltage (for differential sensing) and trip voltage (for large-signal sensing) are considered simultaneously at subthreshold (Vdd=0.4V) and superthreshold (Vdd=1.0V) regions. For differential sensing, the subthreshold sensing margin is severely degraded by the variation in Bitline voltage and sufficient time before enabling the sense amplifier is required to improve the limited margin. For large-signal sensing scheme, we show that there is large disparity between the sense “0” margin and sense “1” margin with the significantly worse sense “0” margin limiting the affordable number of cells per Bitline. The possibility of using double-fin PFET in large-signal sensing inverter to improve the sense “0” margin is examined, and shown to be of limited benefit, especially for operation in subthreshold region. Compared with BULK CMOS, the superior electrostatic integrity and variability of FinFET enhances/enables the feasibility of differential sensing in subthreshold/superthreshold SRAM applications.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115062450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-23DOI: 10.1109/VLSI-TSA.2012.6210171
C. Xu, P. Batude, M. Vinet, M. Mouis, M. Cassé, B. Sklénard, B. Colombeau, Q. Rafhay, C. Tabone, J. Berthoz, B. Previtali, J. Mazurier, L. Brunet, L. Brevard, F. Khaja, J. Hartmann, F. Allain, A. Toffoli, R. Kies, C. Le Royer, S. Morvan, A. Pouydebasque, X. Garros, A. Pakfar, C. Tavernier, O. Faynot, T. Poiroux
For the first time, low temperature (LT) anneal at 625°C has been demonstrated for dopants activation enabling similar ION/IOFF trade-off as standard spike anneal (>;1000°C), down to 30nm gate length (LG) for both n&p FETs. Similar short channel effect control has been achieved in LT n&p FETs as its high temperature (HT) counterparts. Influence of dopant implant tilt on LT device performance is analyzed and guidelines for device performance optimization are proposed. This demonstration paves the way to 3D sequential integration with equal performance for stacked transistors and for bottom transistors.
{"title":"Improvements in low temperature (<625°C) FDSOI devices down to 30nm gate length","authors":"C. Xu, P. Batude, M. Vinet, M. Mouis, M. Cassé, B. Sklénard, B. Colombeau, Q. Rafhay, C. Tabone, J. Berthoz, B. Previtali, J. Mazurier, L. Brunet, L. Brevard, F. Khaja, J. Hartmann, F. Allain, A. Toffoli, R. Kies, C. Le Royer, S. Morvan, A. Pouydebasque, X. Garros, A. Pakfar, C. Tavernier, O. Faynot, T. Poiroux","doi":"10.1109/VLSI-TSA.2012.6210171","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210171","url":null,"abstract":"For the first time, low temperature (LT) anneal at 625°C has been demonstrated for dopants activation enabling similar ION/IOFF trade-off as standard spike anneal (>;1000°C), down to 30nm gate length (LG) for both n&p FETs. Similar short channel effect control has been achieved in LT n&p FETs as its high temperature (HT) counterparts. Influence of dopant implant tilt on LT device performance is analyzed and guidelines for device performance optimization are proposed. This demonstration paves the way to 3D sequential integration with equal performance for stacked transistors and for bottom transistors.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132968422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-01DOI: 10.1109/VLSI-TSA.2012.6210139
G. Huang
The growth of smartphone market shows that more people want to customize their handsets with applications that suit their interests and lifestyle. To realize consumers' requirements, device manufacturers need something that has to have high-performing processor, high-performing mobile broadband modems as well as high performing connectivity technologies. It is a key for wireless platform vendor to offer complete platforms. The recent trend in the wireless industry has clearly been to transfer the platform development from the handset makers to platform companies such as ST-Ericsson. Companies like ST-Ericsson can master all the parts of the mobile platform to build complete, optimized systems integrating application processors, modems and connectivity. By offering the complete platforms, ST-Ericsson is powering a broad range of next generation smartphones, tablets, and other smart devices. These integrated solutions can then be sold to the whole market, rather than sold to limited individual customers.
{"title":"Powerful smartphone solutions unleashing new technology innovations","authors":"G. Huang","doi":"10.1109/VLSI-TSA.2012.6210139","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210139","url":null,"abstract":"The growth of smartphone market shows that more people want to customize their handsets with applications that suit their interests and lifestyle. To realize consumers' requirements, device manufacturers need something that has to have high-performing processor, high-performing mobile broadband modems as well as high performing connectivity technologies. It is a key for wireless platform vendor to offer complete platforms. The recent trend in the wireless industry has clearly been to transfer the platform development from the handset makers to platform companies such as ST-Ericsson. Companies like ST-Ericsson can master all the parts of the mobile platform to build complete, optimized systems integrating application processors, modems and connectivity. By offering the complete platforms, ST-Ericsson is powering a broad range of next generation smartphones, tablets, and other smart devices. These integrated solutions can then be sold to the whole market, rather than sold to limited individual customers.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115471614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/vlsi-tsa.2012.6210107
Brian Lee
This paper describes a fundamental building block and architecture of future high density storage class memory products. A review of 3D architecture is presented. A detailed review of cross point select devices and memory cells are conducted followed by their integration scheme. A critical review of its challenges and potential solutions are proposed.
{"title":"Review of 3D high density storage class memory (SCM) architecture","authors":"Brian Lee","doi":"10.1109/vlsi-tsa.2012.6210107","DOIUrl":"https://doi.org/10.1109/vlsi-tsa.2012.6210107","url":null,"abstract":"This paper describes a fundamental building block and architecture of future high density storage class memory products. A review of 3D architecture is presented. A detailed review of cross point select devices and memory cells are conducted followed by their integration scheme. A critical review of its challenges and potential solutions are proposed.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"525 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130215144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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